JPH05297931A - Digital signal processor - Google Patents

Abstract

PURPOSE:To increase the count number that is multiplied by an input signal to improve the arithmetic accuracy by securing such a constitution where an arithmetic part which performs an operation including the term to be multiplied by a sampling period can operate synchronously with a sampling period longer than other arithmethic parts. CONSTITUTION:An LPF 3 and a decimator 5 are connected in series to an input part of a computing element 1 which performs an integral operation witha transmission function G2 (z). The decimator 5 supplies the smapling period of a discrete time signal X (n) serving as a non-processing signal supplied via the LPE 3 to the element 1 after multiplying the sampling period by L. Meanwhile an inpolator 6 and an LPF 4 are connected to the output part of the element 1. The inpolator 6 multiplies the sampling period of the element 1 by 1/L, and the signal synchronouns with the smapling periods accoradnct with other computing elements are outputted. In such a constitution, the element 1 can perform the arithmetic processing synchronously with a sampling period of L times as mush as those of other computing elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus suitable for controlling industrial equipment.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional general digital signal processing apparatus. In this figure,
x (n) is a discrete time signal at time n, and is sequentially input to this digital signal processing device at intervals of the sampling period T. 1, 1, ... Are arithmetic units, respectively, for the input signal, predetermined transfer functions G ₁ (z), G ₂ (z),
..., digital signal processing according to G _L (z) is performed. The signal processing result y ₁ (n), y in each computing unit 1, 1, ...
₂ (n), ..., Y _L (n) are added by the adder 2. These signal processing results are subjected to rounding processing or rounding down of values below the decimal point so as to match the number of digits of data required by a subsequent device such as a D / A (digital / analog) converter. Then, the resulting final digital signal Y (n) is supplied to the succeeding device.

For example, a digital signal processing device functioning as a PID controller performs arithmetic processing corresponding to the following transfer functions G ₁ (z), G ₂ (z) and G ₃ (z) in the configuration of FIG. It can be configured by providing three arithmetic units 1, 1, 1. These three computing units function as a proportional regulator, an integral regulator, and a differential regulator, respectively. G ₁ (z) = K _P (1) G ₂ (z) = K _I · T / (1-z ⁻¹ ) (2) G ₃ (z) = K _D (1-z ⁻¹ ) / T ( 3) In the above equations (1), (2), and (3), K _P , K _I, and K _D are the gains of the proportional regulator, integral regulator, and derivative regulator. Further, T is a digital signal to be processed,
That is, it is the sampling period of the discrete time signal x (n), and z ⁻¹ is a delay element corresponding to the delay processing for one sampling period. Here, in order for the differential controller and the proportional controller to exhibit excellent responsiveness even in a high frequency region, it is necessary to make the sampling period as short as possible.

[0004]

By the way, a digital signal processing device including a circuit for performing an integration operation, for example, has a sampling period T for a signal to be integrated, as shown in the above equation (2). The process of multiplying by. Here, when another arithmetic circuit is required to have excellent responsiveness even in a high frequency region, the sampling cycle of the digital signal processing device is set very fine (about 100 μs or less) for the reason described above. Therefore, in the integration calculation, the coefficient K _{I of} an extremely small value is added to the signal to be integrated.
-T (K _I is usually a value of about 10 ¹ to 10 ² ) is multiplied. Therefore, when the signal to be integrated is small, the result of processing such as rounding or truncation becomes 0, and normal integration operation cannot be performed.
This problem can be solved by lengthening the entire sampling period, but on the contrary, the responsiveness of proportional calculation and differential calculation is impaired. This problem becomes a particularly important problem when a digital signal processing device is used to control a device that requires highly accurate positioning, a magnetic levitation device, or the like. For example, FIG. 4 shows a result of measuring a displacement of a shaft when an external force is applied to the shaft by inserting a PID controller into a negative feedback system for suppressing fluctuation of the shaft of a magnetic bearing by a conventional digital signal processing device. It is a thing. Here, the sampling period of the PID controller is 50μ.
s. Further, in FIG. 4, the vertical axis represents the value of the detection signal obtained from the detector that detects the axial displacement, and 10 mV corresponds to the axial displacement of 1 μm. FIG. 4 shows how the shaft swings in the range of 7 μm due to an external force. This is because the integral calculation does not function normally for the processed signal corresponding to the 7 μm range input to the digital signal processing device.

The present invention has been made in view of the above-mentioned circumstances, and provides a digital signal processing device capable of highly accurately executing arithmetic processing including a term multiplied by a sampling period, such as integral calculation. The purpose is to

[0006]

According to the present invention, in a digital signal processing apparatus which sequentially executes a predetermined arithmetic processing in synchronization with a predetermined sampling cycle, an arithmetic operation including a term multiplied by the sampling cycle in the arithmetic processing is performed. The arithmetic unit operates in synchronization with a sampling period longer than the arithmetic units that perform other arithmetic processes, and the input unit of the arithmetic unit that performs the arithmetic operation includes the term multiplied by the sampling period. It is characterized in that a decimator for converting the sampling cycle of 1 to the sampling cycle corresponding to the arithmetic unit is connected.

[0007]

According to the above configuration, the arithmetic unit that performs the arithmetic operation including the term that multiplies the sampling period operates in synchronization with the longer sampling period than the other arithmetic units. Therefore, the coefficient by which the input signal is multiplied can be increased. Therefore, the arithmetic processing in the arithmetic unit is performed with high accuracy.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a digital signal processing apparatus according to an embodiment of the present invention. In this figure, the parts corresponding to those in FIG. 3 described above are designated by the same reference numerals, and the description thereof will be omitted. In the digital signal processing apparatus shown in FIG. 1, the input of the arithmetic unit 1 (the transfer function G ₂ (z)) performs integral calculation, low-pass filter (hereinafter, L
A PF) 3 and a decimator 5 are inserted in series. Further, an interpolator 6 and an LPF 4 are inserted in series at the output of the arithmetic unit 1 that performs the integral calculation. With this configuration, the arithmetic unit that performs the integral calculation performs the arithmetic processing in synchronization with the sampling period L times the sampling period of the other arithmetic units. Also, the decimator 5 is an LP
Discrete-time signal x, which is the processed signal supplied through F3
This is a device for converting the sampling period of (n) to L times and supplying it to the arithmetic unit 1. Such a decimator 5 has, for example, a counter that counts the number of samples of the discrete-time signal x (n) sequentially supplied, and an arithmetic unit 1 that calculates a sample at that time every time L samples are counted by this counter. Can be configured by a circuit for sending to. The interpolator 6 is a device that interpolates the integration result (discrete time signal) obtained from the computing unit 1 on the time axis. The interpolator 6 converts the sampling cycle of the output signal of the arithmetic unit 1 into 1 / L, and as a signal synchronized with the sampling cycle corresponding to the other arithmetic units other than the arithmetic unit 1 that performs the integral calculation. Is output.

According to this structure, by increasing L, it is possible to increase the coefficient K _I · T by which the signal to be integrated in the integration operation is multiplied. Therefore,
Even when the value of the input signal x (n) is small, the integral calculation can be normally performed. Further, since the arithmetic units other than the arithmetic unit 1 that performs the integral calculation operate at a short sampling cycle, the entire digital signal processing maintains excellent responsiveness up to high frequencies.

FIG. 2 shows the results when the same digital signal processor according to the above embodiment is used to carry out the same control for suppressing the fluctuation of the shaft of the magnetic bearing as described above with reference to FIG. An arithmetic unit 1 that performs integration when configuring this device
Only the sampling cycle of was set to 20 times the sampling cycle of other computing units. Comparing FIG. 2 and FIG. 4, it can be seen that the present device completely improves the swing of the shaft.

In the above embodiment, the case has been described where the signals output from the respective arithmetic units 1, 1, ... Are added as digital signals and the result is output as a signal processing result. It may be converted into a signal and then added to be used as a signal processing result. In such cases,
The desired effect can be obtained without connecting the interpolator 6 to the subsequent stage of the computing unit 1 that performs the integral computation. If folding distortion due to decimation is not a problem, use LP
When it is not necessary to correct F3 and the signal after the interpolation, LPF4 can be omitted. In addition, the configuration of the above-described embodiment can be regarded as an expanded or modified version of a transfer function or a part thereof. In addition, it is a naturally conceivable modification that all or part of the above-mentioned configuration is converted to software.

[0012]

As described above, in the digital signal processing device according to the present invention, the arithmetic unit that performs the arithmetic operation including the term multiplied by the sampling period is synchronized with the longer sampling period than the arithmetic units that perform other arithmetic processing. And a decimator for converting the sampling period of the input discrete-time signal into a sampling period corresponding to the arithmetic unit is connected to the input unit of the arithmetic unit that performs the operation including the term multiplied by the sampling period. Therefore, even when the value of the signal to be processed is small, a high calculation accuracy can be obtained for the calculation including the term that multiplies the sampling period, and the calculation unit that performs another calculation process performs the calculation at the predetermined sampling period. Therefore, there is an effect that excellent responsiveness is maintained even at high frequencies.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an effect of the same embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional digital signal processing device.

FIG. 4 is a diagram illustrating a problem when vibration suppression control of a shaft of a magnetic bearing is performed by a conventional digital signal processing device.

[Explanation of symbols]

 1 ... calculator, 5 ... decimator.

Claims (1)

[Claims] 1. In a digital signal processing device that sequentially executes a predetermined calculation process in synchronization with a predetermined sampling period, a calculation unit that performs a calculation including a term multiplied by the sampling period in the calculation process is a different calculation process. In the input unit of the arithmetic unit that operates in synchronization with a longer sampling period than the arithmetic unit that performs, and that includes a term multiplied by the sampling period, the sampling period of the input discrete time signal is input to the arithmetic unit. A digital signal processing device, characterized in that a decimator for converting to a corresponding sampling period is connected.