JPH05299520A - Method for formation of contact hole in semiconductor element - Google Patents

Abstract

PURPOSE:To form a contact hole in an excellent dimension-controllable manner by the difference in etching rates of an interlayer insulating film and the film formed thereon, to improve the step coverage of the upper layer wiring by making an angle to the contact hole, and to improve the reliability of a wiring. CONSTITUTION:In the title contact hole forming method for a semiconductor element on which a multilayer wiring operation is conducted, a first layer wiring 22 is formed, then an interlayer insulating film 23 is formed, and an upper layer (plasma silicon nitride film) 24 having a slow etching rate is formed. Then, the upper layer 24 is isotropically etched using a resist pattern 25, and anisotropic etching is conducted on the entire surface after the resist pattern 25 has been removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole for obtaining electrical conduction.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view showing a step of forming a contact hole in a multilayer wiring structure in the conventional method for manufacturing a semiconductor device. In this figure, 11 shows up to the previous step of the first layer wiring, 12 is the first layer wiring, 13 is an interlayer insulating film,
Reference numeral 14 is a resist, and 15 is a second layer wiring.

A method of forming a contact hole in a semiconductor device will be described below with reference to this drawing. First, according to a conventional manufacturing method, as shown in FIG. 2A, a first layer wiring (5000 Å) 12, an interlayer insulating film (10000 Å) 1
3 and the resist pattern 14 are formed respectively.

Next, as shown in FIG. 2B, the insulating film 13 is isotropically etched by 3000 Å using the resist pattern 14 as a mask. Then, as shown in FIG. 2C, the remaining 700 of the insulating film 13 is anisotropically etched.
Etch 0Å. After this, resist pattern 1
4 is removed, and as shown in FIG. 2D, the second layer wiring (5
000Å) 15 is formed. Generally, wet etching is used for isotropic etching and dry etching is used for anisotropic etching.

[0005]

However, in the above-mentioned prior art, in FIG. 2B, the resist pattern droops and the dimensions of the mask are deviated. The contact hole may not be opened.

Second inside the contact hole
The step coverage of the layer wiring is not sufficient, the conduction between the first layer wiring and the second layer wiring cannot be obtained, or the second layer wiring is disconnected. There is a problem such as that, which causes a decrease in the reliability of the wiring. In order to eliminate the above-mentioned problems that the contact holes cannot be opened according to the design dimensions, the step coverage of the upper layer wiring is insufficient, and the reliability of the wiring is reduced, the upper layer of the interlayer insulating film is formed. By providing a layer with a slow etching rate, isotropic etching,
By anisotropically etching, the wall of the contact hole is angled to form a contact hole with good dimensional control due to the difference in etching rate between the interlayer insulating film and the upper layer formed thereon. Moreover, it is an object of the present invention to provide a method for forming a contact hole of a semiconductor device, which can improve the step coverage of the upper layer wiring by increasing the angle of the contact hole and thus improve the reliability of the wiring.

[0007]

In order to achieve the above object, the present invention provides a method of forming a contact hole in a semiconductor device, which comprises a step of forming a first layer wiring, a step of forming an interlayer insulating film, A step of forming an upper layer having a slow etching rate, a step of isotropically etching the upper layer using a resist pattern, and a step of anisotropically etching the entire surface after removing the resist pattern are sequentially performed. It is the one.

Further, a step of forming the first layer wiring, a step of forming an interlayer insulating film which is reflowed by heat treatment, a step of forming an upper layer having a low etching rate, and a step of forming the upper layer isotropically by using a resist pattern. An etching step, a step of anisotropically etching the entire surface after removing the resist pattern, and a step of reflowing the interlayer insulating film by heat treatment to smooth the edge shape of the through hole are sequentially performed. It was done like this.

[0009]

According to the present invention, in the method of forming a contact hole of a semiconductor element, after forming an interlayer insulating film, an upper layer having a slow etching rate is formed. The upper layer is isotropically etched using a resist pattern, and then is anisotropically etched over the entire surface to form an angle on the inner wall of the contact hole, so that the contact hole can be formed with good dimensional control. Further, the step coverage is improved, and the reliability of the wiring can be improved.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a process of forming a contact hole of a semiconductor device showing a first embodiment of the present invention. In this figure, 21 indicates up to the previous step of the first layer wiring, 22 is the first layer wiring, 23 is an interlayer insulating film, 24 is an upper layer having a slower etching rate than the interlayer insulating film 23, 25
Is a resist pattern, and 26 is a second layer wiring.

The first embodiment will be described below with reference to FIG. First, as shown in FIG. 1A, the first layer wiring (5000 Å) 22, for example, an Al alloy wiring (or,
Tungsten wiring or polycrystalline silicon wiring may be used. ) Is formed, and then the interlayer insulating film (10000Å) 2
3. Form a silicon oxide film of ozone and TEOS (tetra-ethyl-ortho-silicate), for example.

Next, as shown in FIG. 1B, an upper layer (5000Å) 24, for example, a plasma silicon nitride film, which has a dry etching rate of 1/2 that of the interlayer insulating film 23, is formed, and a resist is formed. The pattern 25 is formed. Next, as shown in FIG. 1C, the upper layer 24 is isotropically etched using the resist pattern 25 as a mask.

Next, as shown in FIG. 1D, the resist pattern 25 is removed, and a contact hole is formed by anisotropic etching on the entire surface of the wafer. After this,
As shown in (e), the second layer wiring (5000Å) 26 is formed. Here, in the formation of the contact hole,
The film thicknesses A and B of the interlayer insulating film and the upper layer thereof are A / a = B / depending on the anisotropic etching rates a and b, respectively.
Set as b. Further, the dimension C that determines the angle of the inner wall of the contact hole is equal to the dimension B.

FIG. 3 is a sectional view showing a process of forming a contact hole of a semiconductor device showing a second embodiment of the present invention. In this figure, 31 indicates up to the pre-process of the first layer wiring.
Reference numeral 2 is a first layer wiring, for example, a polycrystalline silicon wiring that withstands reflow (heating and flowing), 33 is an interlayer insulating film that is reflowed by heat treatment, and 34 is a second layer wiring.

The second embodiment will be described below with reference to this drawing. As shown in FIG. 3A, a contact hole is formed by the process of FIGS. 1A to 1D of the first embodiment. Next, as shown in FIG. 3B, the interlayer insulating film 33, for example, the BPSG film or the PSG film is reflowed by heat treatment.

Next, as shown in FIG. 3C, the second layer wiring 34 is formed. Here, the reflow of the interlayer insulating film 33 further improves the coverage of the second layer wiring 34 because the corners of the contact holes of the interlayer insulating film 33 are eliminated. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0017]

As described in detail above, according to the present invention, after forming an interlayer insulating film, an upper layer having a slower etching rate is formed, and this upper layer is isotropic by using a resist pattern. Since the contact hole is formed by performing anisotropic etching on the entire surface after performing anisotropic etching, the contact hole with good dimensional control is used because the difference in etching rate between the interlayer insulating film and the upper layer is used. Can be formed.

Since the inner wall of the contact hole can be angled, the step coverage of the second layer wiring is improved. Further, when heat treatment can be performed in the step, if the reflowing interlayer insulating film is used, the step coverage of the second layer wiring is further improved by the reflowing of the interlayer insulating film.

With such an effect, the reliability of the wiring can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a process of forming a contact hole of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a sectional view of a conventional semiconductor element contact hole forming step.

FIG. 3 is a sectional view of a step of forming a contact hole of a semiconductor device showing a second embodiment of the present invention.

[Explanation of symbols]

22, 32 First layer wiring 23, 33 Interlayer insulating film 24 Upper layer (plasma silicon nitride film) 25 having a slower etching rate than the interlayer insulating film 23 Resist pattern 26, 34 Second layer wiring

Claims (2)

[Claims] 1. A method of forming a contact hole of a semiconductor device having a multilayer wiring, comprising: (a) forming a first layer wiring; (b) forming an interlayer insulating film; and (c) an etching rate. Forming a slow upper layer, (d) performing isotropic etching on the upper layer using a resist pattern, and (e) performing anisotropic etching on the entire surface after removing the resist pattern. A method for forming a contact hole of a semiconductor device, which is characterized by sequentially performing. 2. (a) a step of forming a first layer wiring; (b) a step of forming an interlayer insulating film which is reflowed by heat treatment; (c) a step of forming an upper layer having a slow etching rate; ) A step of isotropically etching the upper layer using a resist pattern, (e) a step of anisotropically etching the entire surface after removing the resist pattern, and (f) a heat treatment of the interlayer insulating film. A method of forming a contact hole of a semiconductor element, which comprises sequentially performing reflow and smoothing the edge shape of the through hole.