JPH05299530A - Resin-sealed semiconductor device and manufacturing method thereof - Google Patents

Resin-sealed semiconductor device and manufacturing method thereof

Info

Publication number
JPH05299530A
JPH05299530A JP4098044A JP9804492A JPH05299530A JP H05299530 A JPH05299530 A JP H05299530A JP 4098044 A JP4098044 A JP 4098044A JP 9804492 A JP9804492 A JP 9804492A JP H05299530 A JPH05299530 A JP H05299530A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
semiconductor chip
metal thin
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4098044A
Other languages
Japanese (ja)
Inventor
Yasufumi Uchida
康文 内田
Tadashi Yamaguchi
忠士 山口
Kenji Nagasaki
健二 長崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4098044A priority Critical patent/JPH05299530A/en
Publication of JPH05299530A publication Critical patent/JPH05299530A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】 【目的】 リード部のない表面実装型樹脂封止半導体装
置。 【構成】 ダイパッド(4)上の半導体チップ(6)の
端子部をその周辺に設けた導体部(2)に金属細線
(1)により夫々ワイヤボンドし、それを上記夫々の金
属細線の一部が上面に露出するように樹脂封止し、露出
した金属細線をプリント基板上の配線への接合に用い
る。
(57) [Abstract] [Purpose] Surface mount type resin-sealed semiconductor device without leads. [Structure] A terminal portion of a semiconductor chip (6) on a die pad (4) is wire-bonded to a conductor portion (2) provided around it by a metal thin wire (1), which is part of each of the metal thin wires. Is sealed with resin so as to be exposed on the upper surface, and the exposed thin metal wire is used for bonding to the wiring on the printed circuit board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、詳細
には樹脂封止型の半導体装置及びその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】半導体チップを汚染源及び機械的破壊か
ら保護することを目的とした樹脂封止半導体装置は周知
でありコストが低いこと及び量産性に優れていることに
より広く用いられている。この樹脂封止半導体装置では
ダイパッド上の半導体チップの種々の端子とそれに対応
した、比較的剛性の高いリードを金あるいは銅のような
金属細線で接続した後、樹脂モールドが行われ、しかる
後にリードの露出部分をプリント基板への実装すなわち
挿入あるいは表面実装型に適した形に加工しそして必要
であれば曲げ加工を行った後、メッキを行い、半導体装
置が形成される。
2. Description of the Related Art A resin-encapsulated semiconductor device intended to protect a semiconductor chip from a pollution source and mechanical damage is well known, and is widely used because of its low cost and excellent mass productivity. In this resin-encapsulated semiconductor device, various terminals of the semiconductor chip on the die pad and corresponding leads having relatively high rigidity are connected with a thin metal wire such as gold or copper, followed by resin molding, and then the leads are connected. The exposed portion of is processed into a shape suitable for mounting, that is, insertion or surface mounting on a printed circuit board, and if necessary, bent, and then plated to form a semiconductor device.

【0003】[0003]

【発明が解決しようとする課題】このような樹脂封止後
のリード部分の機械的及び化学的な加工によりいくつか
の問題が生じる。すなわち、この加工によりリード部分
に望ましくない変形が生じる可能性が高く、また、樹脂
封止部の損傷の可能性が高い。これら問題が解決された
としても、このようにしてつくられた半導体装置ではリ
ード部がその縁部から突出するために、その搬送あるい
は保管時にもその変形が生じうる。そのような形成は、
特に表面実装型の装置では大きな問題となる。
Some problems occur due to the mechanical and chemical processing of the lead portion after the resin sealing as described above. That is, there is a high possibility that this processing will cause undesired deformation of the lead portion, and there is a high possibility that the resin sealing portion will be damaged. Even if these problems are solved, in the semiconductor device manufactured in this way, the lead portion protrudes from the edge portion thereof, so that the deformation may occur during transportation or storage. Such formation is
In particular, it is a big problem in the surface mount type device.

【0004】すなわち、そのような変形によりしばしば
リード間の接触や、リード平坦度の低下が生じる。特に
この平坦度の低下はプリント基板表面への実装時にリー
ドが部分的にその表面から浮き上がらせ基板への接着を
不可能とすることがある。そのため、半導体装置の保管
や移送のための特殊なトレイ等の保護容器が必要とな
る。
That is, such deformation often causes contact between the leads and reduction in flatness of the leads. In particular, this decrease in flatness may cause the leads to partly float up from the surface during mounting on the surface of the printed board, making it impossible to adhere to the board. Therefore, a protective container such as a special tray for storing and transferring the semiconductor device is required.

【0005】本発明の目的はこのような種々の問題の根
源となるリード部を有しない表面実装型の樹脂封止型半
導体装置及びその製造方法を提供することである。
An object of the present invention is to provide a surface mount type resin-sealed semiconductor device which does not have a lead portion which is the root of various problems and a manufacturing method thereof.

【0006】[0006]

【課題を解決するための手段】本発明によれば、従来、
半導体チップの端子部とリードとを接続するために用い
られているワイヤボンド用金属細線自体を樹脂封止され
た半導体装置の上面に露出させてリードに代え、外部実
装プリント基板との接点として用いる。
SUMMARY OF THE INVENTION According to the present invention,
The wire-bonding thin metal wire itself used for connecting the terminal portion of the semiconductor chip and the lead is exposed on the upper surface of the resin-sealed semiconductor device and replaced with the lead, and is used as a contact with the externally mounted printed circuit board. ..

【0007】[0007]

【作用】従来、樹脂封止後に機械的加工を必要とするリ
ードがなくなるため、それに起因する諸問題は本来存在
しなくなる。本発明の半導体装置は予めハンダペースト
を配置したプリント基板に上下を逆にして配置され、適
当なリフロー処理により基板に固定される。
In the past, since there are no leads that require mechanical processing after resin encapsulation, various problems resulting from this are essentially nonexistent. The semiconductor device of the present invention is placed upside down on a printed board on which a solder paste has been placed in advance, and is fixed to the board by an appropriate reflow process.

【0008】[0008]

【実施例】図1は本発明による樹脂封止半導体装置10
の概略断面図である。図1において、ダイパッド4上に
半導体チップ6が配置される。このダイパッド4の上記
半導体チップ6が配置される領域の外側には絶縁耐熱性
の粘着テープ3が配置され、テープ3の上の、上記半導
体チップ4の端子部に対応した位置に導体部2が配置さ
れる。これら端子部と導体部2は夫々金属細線1で従来
通りにワイヤーポジティングにより接続される。そし
て、全体が適当な樹脂封止体5により封止されて本発明
の半導体装置10が作られている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a resin-sealed semiconductor device 10 according to the present invention.
FIG. In FIG. 1, the semiconductor chip 6 is arranged on the die pad 4. An insulating and heat resistant adhesive tape 3 is arranged outside the region of the die pad 4 on which the semiconductor chip 6 is arranged, and the conductor portion 2 is provided on the tape 3 at a position corresponding to the terminal portion of the semiconductor chip 4. Will be placed. The terminal portion and the conductor portion 2 are connected to each other by the metal wire 1 by wire positioning in the conventional manner. Then, the whole is sealed with a suitable resin sealing body 5 to manufacture the semiconductor device 10 of the present invention.

【0009】図1に示すように、これら金属細線1の中
央部分は樹脂封止体5の上面に露出している。図2は図
1の半導体装置10の平面図であり、この露出した金属
細線1を示している。
As shown in FIG. 1, the central portions of the metal thin wires 1 are exposed on the upper surface of the resin sealing body 5. FIG. 2 is a plan view of the semiconductor device 10 of FIG. 1, and shows the exposed thin metal wire 1.

【0010】このような構造を有する半導体装置10の
プリント基板12への実装例を図3に示す。図3におい
て、予めハンダペースト11を所定の個所に塗布した外
部実装プリント基板12に、半導体装置10を上下を逆
にして配置し、適当なリフロー装置を用いてハンダペー
ストを溶融し、露出した金属細線1を基板12上のプリ
ント配線(図示せず)に接合する。
An example of mounting the semiconductor device 10 having such a structure on the printed board 12 is shown in FIG. In FIG. 3, the semiconductor device 10 is placed upside down on the external mounting printed circuit board 12 to which the solder paste 11 has been applied in advance at predetermined locations, and the solder paste is melted using an appropriate reflow device to expose the exposed metal. The thin wire 1 is bonded to a printed wiring (not shown) on the substrate 12.

【0011】図4a及び4bは本発明の半導体装置10
の製造方法の一実施例の主要段階を示している。
4a and 4b show a semiconductor device 10 of the present invention.
The main steps of one embodiment of the manufacturing method of

【0012】図4aにおいて、ダイパッド4の周辺部に
絶縁耐熱性粘着テープ3を形成し、そして中央部に配置
されるべき半導体チップ6の種々の端子部に対応して、
導体部2を設ける。そして、中央部に半導体チップ6を
配置し、その端子部と導体部2を夫々金属細線1で接続
する。この際金属細線1の長さは両者を接続した状態で
その中央部分が図4aに点線10′で示す樹脂封止部の
上面より突出するように選ぶ。
In FIG. 4a, the insulating and heat-resistant adhesive tape 3 is formed on the peripheral portion of the die pad 4, and corresponding to various terminal portions of the semiconductor chip 6 to be arranged in the central portion,
The conductor portion 2 is provided. Then, the semiconductor chip 6 is arranged in the central portion, and its terminal portion and the conductor portion 2 are connected by the metal thin wires 1, respectively. At this time, the length of the thin metal wire 1 is selected so that the central portion thereof projects from the upper surface of the resin sealing portion shown by the dotted line 10 'in FIG.

【0013】次に、図4bに示すように上下の金型7
a,7b間に配置する。これにより、金属細線1の余剰
長さ部分は上側金型7aの底壁に線接触する状態とな
る。
Next, as shown in FIG. 4b, the upper and lower molds 7 are formed.
It is placed between a and 7b. As a result, the surplus length portion of the thin metal wire 1 comes into line contact with the bottom wall of the upper mold 7a.

【0014】次にこの金型の図示しないスプルー部から
金型内に適当な樹脂を注入する。
Next, an appropriate resin is injected into the mold through a sprue portion (not shown) of the mold.

【0015】このようにして図1の樹脂封止された半導
体装置が得られる。樹脂封止部5の上面に露出した金属
細線1の面積をプリント基板への接合に充分なものとす
るために、樹脂封止部5の上面を研磨するとよい。接合
の面積を最大とする研磨の深さは金属細線1の半径に対
応するものであるが、金属細線1と樹脂封止部5との密
着性を併せて確保するためには金属細線1の直径の約1
0%に相当するものとするとよいことが判った。
Thus, the resin-sealed semiconductor device of FIG. 1 is obtained. In order to make the area of the thin metal wire 1 exposed on the upper surface of the resin sealing portion 5 sufficient for bonding to the printed board, the upper surface of the resin sealing portion 5 may be polished. The polishing depth that maximizes the bonding area corresponds to the radius of the metal thin wire 1. However, in order to ensure the adhesion between the metal thin wire 1 and the resin sealing portion 5 as well, About 1 in diameter
It has been found that it should be equivalent to 0%.

【0016】この研磨の工程は上記のように行うことに
替えて、従来の樹脂封止半導体装置におけるリード部の
メッキ加工に先立って行われるホーニング工程を利用し
てもよい。
Instead of performing the polishing step as described above, a honing step performed prior to the plating process of the lead portion in the conventional resin-sealed semiconductor device may be used.

【0017】[0017]

【発明の効果】以上述べたように、本発明の半導体装置
は従来のごときリード部を有さないため、リードに対し
て行われるべき加工工程は一切なく、またリードに起因
する問題はすべて解決される。
As described above, since the semiconductor device of the present invention does not have a lead portion as in the conventional case, there is no processing step to be performed on the lead and all problems caused by the lead are solved. To be done.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による半導体装置の概略断面
図。
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】図1の半導体装置の平面図。FIG. 2 is a plan view of the semiconductor device of FIG.

【図3】図1の半導体装置のプリント基板への実装を示
す図。
FIG. 3 is a diagram showing mounting of the semiconductor device of FIG. 1 on a printed circuit board.

【図4】図1の半導体装置の製造工程の主要部を示す
図。
FIG. 4 is a view showing a main part of a manufacturing process of the semiconductor device of FIG.

【符号の説明】[Explanation of symbols]

1 ワイヤボンド金属細線 2 導体部 3 絶縁耐熱粘着テープ 4 ダイパッド 5 樹脂封止部 6 半導体チップ 7a,7b モールド金型 1 Wire Bond Metal Fine Wire 2 Conductor Section 3 Insulation Heat Resistant Adhesive Tape 4 Die Pad 5 Resin Sealing Section 6 Semiconductor Chip 7a, 7b Mold Die

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ダイパッド上に配置され、複数の端子部
を有する半導体チップと、上記半導体チップの配置され
る領域の外側のダイパッド部分に絶縁層を介して、上記
半導体チップの端子部に対応して配置される導体部分
と、上記半導体チップの端子部と上記導体部分とを夫々
接続する金属細線と、上記ダイパッド上の半導体チッ
プ、上記導体部及び上記金属細線を、夫々上記金属細線
の一部のみが上面に露出するように封止する樹脂封止部
と、を特徴として含む樹脂封止半導体装置。
1. A semiconductor chip disposed on a die pad and having a plurality of terminal portions, and a die pad portion outside a region where the semiconductor chip is disposed, corresponding to a terminal portion of the semiconductor chip via an insulating layer. Part of the metal thin wire, the metal thin wire connecting the terminal portion of the semiconductor chip and the conductor portion, respectively, the semiconductor chip on the die pad, the conductor portion and the metal thin wire, respectively. A resin-encapsulated semiconductor device, which comprises a resin encapsulation portion that encapsulates so that only one is exposed on the upper surface.
【請求項2】 ダイパッド上に複数の端子部を有する半
導体チップを配置すると共にその周辺のダイパッド部分
に絶縁層を介して上記端子部に対応して導体部分を配置
する段階と、上記半導体チップの端子部と上記導体部分
とを夫々充分長い金属細線により接続する段階と、上記
半導体チップ、上記導体部分及び上記金属細線を、上記
夫々の金属細線の一部のみが上側金型の底壁に接触する
ようにして上下の金型により形成される空胴に配置する
段階と、上記空胴に樹脂を注入し樹脂封止する段階を特
徴として含む、樹脂封止半導体装置の製造方法。
2. A step of disposing a semiconductor chip having a plurality of terminal portions on a die pad and disposing a conductor portion corresponding to the terminal portion via an insulating layer in a peripheral die pad portion, and a step of disposing the semiconductor chip. The step of connecting the terminal portion and the conductor portion with a sufficiently long metal thin wire, and the semiconductor chip, the conductor portion and the metal thin wire, and only a part of each metal thin wire contacts the bottom wall of the upper mold. A method of manufacturing a resin-encapsulated semiconductor device, which comprises the steps of: arranging in a cavity formed by the upper and lower molds in this manner, and injecting a resin into the cavity to perform resin sealing.
【請求項3】 前記樹脂封止する段階後に、前記樹脂封
止半導体装置の上面を研磨する段階を有する、請求項2
記載の樹脂封止半導体装置の製造方法。
3. The method according to claim 2, further comprising polishing the upper surface of the resin-sealed semiconductor device after the resin-sealing.
A method for manufacturing the resin-encapsulated semiconductor device described.
【請求項4】 前記研磨段階は前記金属細線の直径の約
10%が上記上面からの研磨により除去されるごとくに
行われることを特徴とする請求項3記載の樹脂封止半導
体装置の製造方法。
4. The method of manufacturing a resin-sealed semiconductor device according to claim 3, wherein the polishing step is performed such that about 10% of the diameter of the thin metal wire is removed by polishing from the upper surface. ..
JP4098044A 1992-04-17 1992-04-17 Resin-sealed semiconductor device and manufacturing method thereof Pending JPH05299530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4098044A JPH05299530A (en) 1992-04-17 1992-04-17 Resin-sealed semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4098044A JPH05299530A (en) 1992-04-17 1992-04-17 Resin-sealed semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH05299530A true JPH05299530A (en) 1993-11-12

Family

ID=14209152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4098044A Pending JPH05299530A (en) 1992-04-17 1992-04-17 Resin-sealed semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH05299530A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09134982A (en) * 1995-11-08 1997-05-20 Fujitsu Ltd Semiconductor device and manufacturing method thereof
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device with improved structure to avoid cracks and manufacturing process
KR20010061849A (en) * 1999-12-29 2001-07-07 박종섭 Wafer level package
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
KR100583491B1 (en) * 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method
JP2010206007A (en) * 2009-03-04 2010-09-16 Nec Corp Semiconductor device and method of manufacturing the same
US8169089B2 (en) 2008-06-24 2012-05-01 Elpida Memory, Inc. Semiconductor device including semiconductor chip and sealing material
EP2889924A1 (en) 2013-12-25 2015-07-01 Nichia Corporation Light emitting device
US9093612B2 (en) 2013-04-26 2015-07-28 Nichia Corporation Light emitting device
JP2016086047A (en) * 2014-10-24 2016-05-19 日亜化学工業株式会社 Light emitting device manufacturing method
EP3093877A3 (en) * 2015-05-14 2017-02-22 MediaTek, Inc Semiconductor package and fabrication method thereof
US9698307B2 (en) 2013-09-05 2017-07-04 Nichia Corporation Light emitting device
US9728694B2 (en) 2014-04-10 2017-08-08 Nichia Corporation Light emitting device and manufacturing method thereof
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device with improved structure to avoid cracks and manufacturing process
EP1039541A1 (en) * 1995-10-24 2000-09-27 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US6177725B1 (en) 1995-10-24 2001-01-23 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
EP1168440A1 (en) * 1995-10-24 2002-01-02 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US6459145B1 (en) 1995-10-24 2002-10-01 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor
US6569755B2 (en) 1995-10-24 2003-05-27 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
JPH09134982A (en) * 1995-11-08 1997-05-20 Fujitsu Ltd Semiconductor device and manufacturing method thereof
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
KR20010061849A (en) * 1999-12-29 2001-07-07 박종섭 Wafer level package
KR100583491B1 (en) * 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method
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