JPH0530331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a hybrid delay adjustment method in a two-line and four-line conversion circuit using a sampling system.

(Prior art) In a 2-wire 4-wire conversion circuit using a sampling system applied to subscriber circuits of electronic exchanges, input is input from the 4-wire side input terminal, and is transmitted via the 2-wire line and 2-line line terminal. In order to cancel the signal coming back to the 4-wire side output terminal, a hybrid circuit was inserted between the 4-wire side input terminal and the 4-wire side output terminal.

However, due to sampling or the slight influence in the band of a low-pass filter with a high cutoff (for example, an anti-aliasing filter inserted before and after an analog-to-digital converter or a digital-to-analog converter), the above-mentioned 4. A transmission delay occurs in the signal returning to the line side output terminal, and compared to the output signal of the hybrid circuit,
There is a possibility that deviations in amplitude and phase characteristics may occur, and as a result, the signal from the 4-wire side input terminal leaks to the 4-wire side output terminal, causing so-called echo, and there is a risk that the effective return loss may not be sufficient. .

In order to prevent this, it is sufficient to delay the output signal of the hybrid circuit by an amount corresponding to the transmission delay. Conventional hybrid circuits that take this point into consideration increase the sampling speed of the circuit operation to increase the sample clock. Effective return loss has been improved by delaying the output in intervals or by inserting a low-pass filter with a high cutoff that takes into account the amount of phase delay into the output or input of the hybrid circuit. .

(Problem to be Solved by the Invention) However, with the method of delaying in units of sample clock intervals, the operating speed of the hybrid circuit may change depending on the fineness of the delay adjustment, and depending on the amount of delay, the register may be changed. In addition, the system using a low-pass filter requires a large amount of hardware, and if the cutoff is low, it may have a negative effect on the amplitude characteristics within the band.

SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid delay adjustment method that enables adjustment of an appropriate delay amount of the output of a hybrid circuit with a small hardware amount when the delay amount is not particularly large.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a pair of 2-line line terminals and a signal generated at the 2-line line terminal via the pair of 2-line line terminals. an A/D converter that performs digital conversion; a first adder that receives the output signal of the A/D converter as one input; a four-wire side output terminal connected to the output of the first adder; a two-line line termination circuit whose input signal is the output signal of the /D converter; a second adder whose one input is the output signal of the two-line line termination circuit;
a D/A converter which converts the output of the second adder into digital/analog and supplies it to a two-line line terminal via a pair of two-line line terminals; It has a line side input terminal and a hybrid circuit inserted between the 4 line side input terminal and the other input of the first adder, and has a 2 line line and a 2 line input from the 4 line side input terminal. The signal that returns to one input of the first adder via the line terminal is the signal input from the 4-wire side input terminal and sent to the other input of the first adder via the hybrid circuit. In a 2-wire 4-wire conversion circuit hybrid delay adjustment method using a canceling sampling system, the current output value of the hybrid circuit and the previous output value are connected between the hybrid circuit and the other input of the first adder. , an interpolated value corresponding to a previous time by the delay time of the signal that is input from the 4-line side input terminal and returns to one input of the first adder via the 2-line line and the 2-line line terminal. A delay adjustment circuit is provided to calculate the

(Function) According to the present invention, between the hybrid circuit and the other input of the first adder, the current output value of the hybrid circuit and the previous output value are input from the 4-wire side input terminal. By providing a delay adjustment circuit that calculates an interpolated value corresponding to a previous time by the delay time of the signal returning to one input of the first adder via the two-line line and the two-line line terminal. ,
A signal substantially equivalently delayed by the delay time, that is, a signal substantially equivalent to the signal to be canceled can be input to the other input of the first adder.

(Example) Figure 1 shows an example of a subscriber circuit of an electronic exchange to which the method of the present invention is applied.
is the 2-wire line terminal, 3 is the 4-wire side output terminal, 4 is the 4-wire side input terminal, 5 is the 2-wire line terminal ZL with impedance ZL, 6 is the differential amplifier A, and 7 is the control current source.
gm, 8 is an analog-to-digital converter (A/D
9 is a digital/analog converter 9 (D/A converter), 10 is a two-line line termination circuit (ZT), 11 is a hybrid circuit H, 12 is a delay adjustment means (circuit) D, 13 and 14 are adders It is.

Both ends of the two-line line terminal 5, the input side of the differential amplifier 6, and the output side of the controlled current source 7 are connected to the two-line line terminals 1 and 2. The output side (terminal) of the differential amplifier 6 is connected to the input side of an A/D converter 8, and the output side of the A/D converter 8 is connected to the input terminal of an adder 14 via a two-wire line termination circuit 10. At the same time, it is connected to the four-wire side output terminal 3 via the adder 13. The four-wire side input terminal 4 is connected to the input side of a D/A converter 9 via an adder 14, and the output side of the D/A converter 9 is connected to the input side of a controlled current source 7. Further, the 4-line side input terminal 4 is connected to the other input terminal of an adder 13 via a hybrid circuit 11 and a delay adjustment circuit 12.

A drive current is supplied to the two-line line terminal 5 from a control current source 7, and the voltage generated across the two-line line terminal 5 is detected by a differential amplifier 6. The output signal of the differential amplifier 6 is converted from analog to digital by the A/D converter 8, and output to the 4-wire side output terminal 3 via the adder 13.
The signal is input to the adder 14 via the line termination circuit 10 and added to the signal input from the 4-line side input terminal 4. The output signal of the adder 14 is digital-to-analog converted by the D/A converter 9 to control the control current source 7.

Further, the signal inputted from the 4-line side input terminal 4 is inputted to the delay adjustment circuit 12 through the hybrid circuit 11, and at this time, it is delayed as described later and inputted to the adder 13. The signal from the delay adjustment circuit 12 is input from the signal from the A/D converter 8 to the 4-line side input terminal 4 and returns to the 4-line side output terminal 3 via the 2-line line and the 2-line line terminal 5. Cancel the signal.

Next, the principle of signal delay in the delay adjustment circuit 12 will be explained with reference to FIG. In FIG. 2, S1 is the output signal of the hybrid circuit 11;
2 indicates the signal to be canceled in the output signal of the A/D converter 8, and Δt indicates the amount of delay (time) of the signal S1 with respect to the signal S2. The signal S1 is actually obtained at every sampling interval (calculation speed) St of the hybrid circuit 11, and the signal S2 is also obtained at every sampling interval (usually the same as the sampling interval St) of the A/D converter 8. It will be done.

From the value of the signal S1 at time tn-1, tn, that is, the output value dn-1, dn of the hybrid circuit 11,
When calculating the interpolated value dI at a time before time tn by the delay amount Δt, dI = dn-1 + (dn-dn-1) (1-Δt/St)
...(1) becomes. This interpolated value dI is the output value of the signal S1 at a time before the delay amount Δt from time tn,
That is, it is approximately equal to the value of signal S2 at time tn.
Therefore, the delay adjustment circuit 12 calculates the above equation (1) and sets the interpolated value dI as the output value at time tn, that is, the current output value, thereby almost equivalently delaying the signal S1 by the time Δt. You can get the same effect.

FIG. 3 shows a specific configuration of the delay adjustment circuit 12 that executes the arithmetic processing. In Figure 3,
Ad1, Ad2 are adders, M is multiplier, R1, R2
is a register that stores signals in units of sampling time St. Register R1 has one stage, R2 generally has n stages, and the delay amount Δt is the sampling time St.
Necessary when larger than n=[Δt/St]
([ ] is a Gauss symbol.) The register R1 stores the output value dn-1 of the previous sample, and the adder Ad1 calculates the difference (dn-dn) from the output value dn.
-1) is calculated. This value is multiplied by (1-Δt/St) by multiplier M, and (dn-dn-1)(1-
Δt/St) is output. This value is further added to the adder
It is added to the output value dn−1 by Ad2, and the above (1)
The formula is calculated and an interpolated value dI is obtained.

As described above, according to the embodiment, it is possible to easily impart a delay effect to the output of the hybrid circuit with a small amount of hardware, and the amount of delay can be changed simply by changing the count of the multiplier M. Moreover, unlike the case of filter coefficients, the delay amount and the count are intuitively linked, making the setting easy. Therefore,
Even when trying to finely adjust the amount of delay, there is no need to increase the operating speed of the hybrid circuit.

FIG. 4 shows another specific configuration of the delay adjustment circuit 12, and here, instead of the above equation (1), the following
The calculation process of equation (2) is executed to obtain the interpolated value dI.

dI=dn-(dn-dn-1)Δt/St...(2) In addition, each component in the figure, namely adder Ad1,
Ad2, multiplier M, and registers R1 and R2 are the same as those in FIG.

In the above embodiment, the output values dn and dn-1 were linearly interpolated, so-called linear interpolation.
If quadratic interpolation is performed, the amount of hardware will increase to some extent, but the accuracy will further increase. Further, although the above embodiment has been explained using a hard image, similar effects can be obtained by program processing using a microprocessor or the like.

(Effects of the Invention) As explained above, according to the present invention, between the hybrid circuit and the other input of the first adder, the current output value of the hybrid circuit and the previous output value are A delay that calculates an interpolated value corresponding to a previous time by the delay time of the signal that is input from the line side input terminal and returns to one input of the first adder via the 2-line line and 2-line line terminal. By providing the adjustment circuit, the other input of the first adder is
It is possible to input a signal that is almost equivalently delayed by the delay time, that is, a signal that is almost the same as the signal to be canceled, and it is possible to easily add a delay effect to the output of the hybrid circuit with a small amount of hardware. Moreover, the amount of delay can be changed simply by changing the count during calculation, and therefore there is an advantage that even when attempting to finely adjust the amount of delay, there is no need to increase the operating speed of the hybrid circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a subscriber circuit of an electronic exchange to which the system of the present invention is applied;
FIG. 3 is an explanatory diagram showing the principle of signal delay according to the method of the present invention, FIG. 3 is an explanatory diagram showing a specific configuration of a delay adjustment circuit, and FIG. 4 is an explanatory diagram showing another specific configuration of the delay adjustment circuit. . 1, 2...2 line line terminal, 3...4 line side output terminal, 4...4 line side input terminal, 5...2 line line terminal, 6...differential amplifier, 7...control current source, 8...
...analog-digital converter, 9...digital-analog converter, 10...2-line line termination circuit, 11...hybrid circuit, 12...delay adjustment circuit, 13, 14...adder.

Claims (1)

[Scope of Claims] 1. A pair of two-line line terminals, an A/D converter that converts signals generated at the two-line line terminal via the pair of two-line line terminals from analog to digital, and the A/D converter. a first adder that takes the output signal of the A/D converter as an input signal, a 4-wire side output terminal connected to the output of the first adder, and a 2-wire line that takes the output signal of the A/D converter as an input signal. a termination circuit, a second adder which receives the output signal of the two-line line termination circuit as one input, and digitally converts the output of the second adder.
A D/A converter that performs analog conversion and supplies it to the 2-line line terminal via a pair of 2-line line terminals, a 4-line side input terminal connected to the other input of the second adder, and the 4-line side input a hybrid circuit inserted between the terminal and the other input of the first adder;
A signal that is input from the 4-line side input terminal and returns to one input of the first adder via the 2-line line and the 2-line line terminal is input from the 4-line side input terminal and passes through the hybrid circuit to the first adder. In a hybrid delay adjustment method for a 2-wire and 4-wire conversion circuit using a sampling system that cancels out signals sent to the other input of the first adder, there is a delay between the hybrid circuit and the other input of the first adder. , from the current output value of the hybrid circuit and the previous output value, is inputted from the 4-wire side input terminal and returned to one input of the first adder via the 2-wire line and the 2-line line terminal. A hybrid delay adjustment method characterized by comprising a delay adjustment circuit that calculates an interpolated value corresponding to an earlier time by the delay time of an incoming signal.