JPH053033B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic simulation of an information processing device using a test program, and particularly to a logic simulation device suitable for testing input/output instructions.

[Conventional technology]

With the increase in the scale of information processing devices, the computer time required for logic simulation is also increasing, and there is a desire to reduce this time.

Conventional simulation equipment is, for example, published in Japanese Patent Application Laid-Open No.
As described in Publication No. 148971, a test program used for testing an information processing device includes an initial setting section that sets the environment for executing test instructions, a test section that executes the test instructions, and a test section that executes the test instructions. It is divided into three parts: a result judgment section that judges execution results;
Only the test section is actually executed on a logic simulator,
The other two parts are executed at high speed by a pseudo procedure that executes instructions instead of the logic simulator, thereby reducing the computer time required for logic simulation using the test program.

The following describes the case of testing input/output instructions (IO instructions) using this type of logic simulation device.
The conventional operation will be explained using FIGS. 3 to 5.

FIG. 3 shows an example of the configuration of a conventional logic simulation device, in which an instruction execution pseudo procedure 1 and a logic simulator 2 communicate information via a communication routine 3, which is stored in a storage device pseudo procedure (MEM) 4. The test program is divided and executed. Here, instruction execution pseudo procedure 1
executes instructions at high speed on a logic function model that describes the functional operation of logic in a device under test using machine language instructions. The logic simulator 2 executes instructions on a logic circuit model that configures the logic of the information processing device under test using basic logic elements that can calculate the operation progress in detail.The logic circuit model is based on a central processing unit model (CPU). ) 5, an input/output processing unit model (IOP) 6, and an input/output unit model (IOU) 7.

FIG. 4 shows an example of a test program, which is composed of a plurality of sets of test cases each consisting of an initial setting section, a test section, and a result judgment section.

FIG. 5 shows the operation of each part when the test program of FIG. 4 is executed by the logic simulation device of FIG. 3.

First, in instruction execution pseudo procedure 1, MEM
Read CPU instructions a to b from 4. This read instruction switches the instruction execution mode from instruction execution pseudo procedure 1 to logic simulator 2.
If it is not a MODE switching command, the instruction execution pseudo procedure 1 executes the instruction and sets the environment for the IO instruction test. After that, when the instruction execution pseudo procedure 1 detects a MODE switching instruction, the communication routine 3 receives the report and transfers the information necessary for instruction execution from the instruction execution pseudo procedure 1 to the logic simulator 2, and changes the instruction execution mode. The instruction execution line pseudo programmer 1 is switched to the logic simulator 2.

In the logic simulator 2, when the CPU 5 reads an IO instruction from the MEM 4, the IOP is executed to execute the IO instruction.
6. The activated IOP6 is further IOU
7 and wait for the startup completion report from IOU7.
When IOP6 receives the startup completion report from IOU7,
Report startup completion to CPU5 and immediately IOU7
Start data transfer between

When the CPU 5 receives the startup completion report from the IOP 6, it executes an IO interrupt waiting loop operation that waits for input/output interrupts (IO interrupts) from the IOP 6 while reading and executing subsequent CPU instructions c to d from the MEM 4. start.

IOP6 transfers data between IOU7 and
When the data transfer completion report comes from IOU7, the CPU
5, causes an IO interrupt. CPU5 is IOP6
When an IO interrupt is reported, input/output interrupt processing (IO interrupt processing) is performed.

When the logic simulator 2 completes all input/output operations, the communication routine 3 receives the report and transfers the information necessary for instruction execution from the logic simulator 2 to the instruction execution pseudo procedure 1, and changes the instruction execution mode to the logic simulator 2. to the instruction execution pseudo procedure 1.

After that, in instruction execution pseudo procedure 1,
Read CPU instructions e to f. The instruction execution pseudo procedure 1 executes the CPU instruction while confirming that it is not a MODE switching instruction, and confirms the test result.

The above operation is repeated for each test case in the test program.

In addition, in the test program shown in Figure 4, MODE
The switching instruction is an instruction that is valid only in the instruction execution pseudo procedure 1. For example, following CPU instruction d
Since the MODE switching command was read by logic simulator 2 in this example, NO-
It is treated as an OPERATION instruction (NOP instruction) and nothing is executed.

[Problem that the invention seeks to solve]

Generally, IO instructions involve data transfer, so
The CPU on the logic simulator needs to detect the end of data transfer. Therefore, even after the start of the IO command is completed, the operation based on the end of data transfer remains as is.
Must wait for IO interrupt.

In this case, in the conventional logic simulation device as shown in FIG. 3, the CPU 5 must wait for an IO interrupt while executing the CPU instruction following the IO instruction. Since this is an IO instruction test, logical simulation of input/output operations such as data transfer and data transfer completion report should of course be performed, but it is not necessary to perform logical simulation of CPU instructions that are executed in parallel on the CPU5.
This will require additional computer time.

Generally, the CPU has a logical scale several times larger than the IOP, so the logical simulation time is quite large and cannot be ignored.

The purpose of the present invention is to reduce the overall logic simulation time by executing CPU instructions that are not subject to test at high speed using an instruction execution pseudo procedure in a logic simulation that tests IO instructions. It is in.

[Means for solving problems]

The above object is achieved by providing an instruction execution control pseudo-procedure that detects when to switch the operation mode of instruction execution between the logic simulator and the instruction execution pseudo-procedure during the execution of an IO instruction.

[Effect]

The instruction execution control pseudo procedure detects when the IOP is activated by the CPU to execute an IO instruction and the IOP reports completion of activation to the CPU, and reports this to the communication routine. Upon receiving the report, the communication routine switches the instruction execution operation mode from the logic simulator to the instruction execution pseudo procedure. When the instruction execution pseudo procedure detects a MODE switching instruction, it reports this to the communication routine. Upon receiving the report, the communication routine switches the instruction execution operation mode from the instruction execution pseudo procedure to the logic simulator.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a logic simulation device according to the present invention. This is the conventional logic simulation device shown in Figure 3.
By providing a new instruction execution control pseudo-procedure 8, the CPU 5 performs an IO interrupt waiting loop operation in which the CPU 5 reads an instruction and waits for an IO interrupt report while repeating instruction execution. This has been modified to perform an operation (IDLE loop operation) that waits for a report of the error.

FIG. 2 shows the operation of each part when the test program of FIG. 4 is executed by the logic simulation device of FIG. 1.

First, in the instruction execution pseudo procedure 1, the CPU
Read instructions a to b from MEM4. The read instruction switches the instruction execution mode from instruction execution pseudo procedure 1 to logic simulator 2.
If it is not a MODE switching command, the instruction execution pseudo procedure 1 executes the instruction and sets the environment for the IO instruction test. After that, when the instruction execution pseudo procedure 1 detects a MODE switching instruction, the communication routine 3 receives the report and transfers the information necessary for instruction execution from the instruction execution pseudo procedure 1 to the logic simulator 2, and changes the instruction execution mode. The instruction execution pseudo procedure 1 is switched to the logic simulator 2.

In the logic simulator 2, the instruction execution control pseudo procedure 8 first determines whether or not it is in an IO interrupt wait state. At first, since it is not in the IO interrupt waiting state, it is operated by the CPU 5 as is. CPU5 is
Reads the IO command from MEM4 and starts IOP6 to execute the IO command. The activated IOP 6 further activates the IOP 7 and waits for a activation completion report from the IOP 7. When the IOP 6 receives the startup completion report from the IOU 7 , it reports the startup completion to the CPU 5 and immediately starts data transfer with the IOU 7 .

The instruction execution control pseudo procedure 8 starts from the IOP6.
Detects the startup completion report reported to CPU5. In response to this, the communication routine 3 transfers the information necessary for instruction execution from the logic simulator 2 to the instruction execution pseudo procedure 1, and changes the instruction execution mode from the logic simulator 2 to the instruction execution pseudo procedure 1.
Switch to

In this case, the data transfer being executed between the IOP6 and IOU7 is interrupted to maintain continuity of operation after restarting.

After that, in instruction execution pseudo procedure 1,
Read CPU instructions c to d, confirm that they are not MODE switching instructions, and execute them. When the instruction execution pseudo procedure 1 detects a MODE switching instruction,
Upon receiving the report, the communication routine 3 transfers information necessary for instruction execution from the instruction execution pseudo procedure 1 to the logic simulator 2, and switches the instruction execution mode from the instruction execution pseudo procedure 1 to the logic simulator 2.

In the logic simulator 2, first, the previously interrupted data transfer between the IOP6 and IOU7 is resumed in a manner that maintains the continuity with that before the interruption.

Next, the instruction execution control pseudo procedure 8
Determine whether it is in the interrupt wait state. Currently, IOP
6. Since data is being transferred between IOU7, CPU5 is waiting for an IO interrupt based on the completion of data transfer.
IDLE waits for IO interrupt without executing any CPU instructions
Repeat loop action.

IOP6 transfers data between IOU7 and
When the data transfer completion report comes from IOU7, the CPU
5, causes an IO interrupt. When an IO interrupt is reported from IOP6, CPU5 handles input/output interrupt processing (IO
interrupt processing).

When the logic simulator 2 completes all input/output operations, the communication routine 3 receives the report and transfers the information necessary for instruction execution from the logic simulator 2 to the instruction execution pseudo procedure 1, and changes the instruction execution mode from the logic simulator 2 to the instruction execution pseudo procedure 1. Switch to instruction execution pseudo procedure 1.

After that, in instruction execution pseudo procedure 1,
Read CPU instructions e to f. The instruction execution pseudo procedure 1 executes the CPU instruction while confirming that it is not a MODE switching instruction, and confirms the test result.

The above operations are repeated for each test case in the test program.

〔Effect of the invention〕

As explained above, according to the present invention, in the logic simulation operation for testing IO instructions, the CPU does not execute any instructions during data transfer between the IOP and IOU, and executes the data transfer from the IOP based on the completion of data transfer.
Since it can wait for IO interrupts, logical simulation time can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a logic simulation device according to the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is a block diagram of a conventional logic simulation device, and FIG. 4 is a diagram of a test program. A diagram showing an example, FIG. 5 is an explanatory diagram of the operation of FIG. 3. 1...Instruction execution pseudo procedure, 2...Logic simulator, 3...Communication routine, 4...Storage device pseudo procedure, 5...Central processing unit model,
6... Input/output processing device model, 7... Input/output device model, 8... Instruction execution control pseudo procedure.

Claims (1)

[Claims] 1. A logic simulator that executes instructions on a logic circuit model that configures the logic of an information processing device under test using basic logic elements that can calculate the operation progress in detail, and an instruction execution pseudo procedure that executes instructions at high speed on a logical function model described using instructions; a storage device pseudo procedure that stores a test program to be executed by the logic simulator and the instruction execution pseudo procedure;
Transferring information necessary for instruction execution between the logic simulator and the instruction execution pseudo procedure;
A logic simulation device having a communication routine for switching an operation mode of instruction execution, wherein an instruction execution control pseudo procedure is provided between the logic simulator and the communication routine to detect when to switch the operation mode of instruction execution; When executing a test program for testing an instruction, the logic simulator executes an input/output instruction and an operation of waiting for a completion report of the input/output operation started by the input/output instruction, and the instruction execution pseudo procedure waits for the completion report of the input/output operation started by the input/output instruction, and the instruction execution pseudo procedure waits for the input/output operation started by the input/output instruction. A logic simulation device characterized by executing operations of system instructions.