JPH0530363Y2 - - Google Patents
Info
- Publication number
- JPH0530363Y2 JPH0530363Y2 JP1989124531U JP12453189U JPH0530363Y2 JP H0530363 Y2 JPH0530363 Y2 JP H0530363Y2 JP 1989124531 U JP1989124531 U JP 1989124531U JP 12453189 U JP12453189 U JP 12453189U JP H0530363 Y2 JPH0530363 Y2 JP H0530363Y2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor chips
- upper lid
- resin layer
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07553—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
(考案の属する技術分野)
本考案は、混成集積回路(ハイブリツドIC)
の回路基板上に実装される電子部品及び半導体チ
ツプの樹脂モールドケースに関するものである。[Detailed description of the invention] (Technical field to which the invention pertains) This invention relates to a hybrid integrated circuit (hybrid IC).
This relates to a resin molded case for electronic components and semiconductor chips mounted on a circuit board.
(従来技術とその問題点)
ハイブリツドICは、セラミツク又はエポキシ
樹脂基板上に配線パターン及び抵抗パターンが形
成され、半導体チツプやその他のチツプ状電子部
品が実装され必要に応じて防湿と機械的保護のた
めに各種の樹脂により封止された機能回路ユニツ
トである。ハイブリツドICの実装部品のうち半
導体チツプの封止方法と構造は、ハイブリツド
ICの小形化すなわち実装密度を向上するための
課題の一つである。(Prior art and its problems) Hybrid ICs have wiring patterns and resistance patterns formed on a ceramic or epoxy resin substrate, on which semiconductor chips and other chip-shaped electronic components are mounted, and where necessary moisture proofing and mechanical protection are provided. It is a functional circuit unit sealed with various resins for various purposes. Among the components mounted in hybrid ICs, the sealing method and structure of semiconductor chips are
This is one of the challenges to miniaturizing ICs, that is, improving packaging density.
第8図は従来の半導体チツプの樹脂による封止
(モールド)の例を示す構造図である。 FIG. 8 is a structural diagram showing an example of conventional resin sealing (molding) of a semiconductor chip.
第8図aは回路基板5に実装された半導体チツ
プ6とそのワイヤ7をモールド樹脂40のみによ
つて封止した部分の平面図であり、bはそのAA
断面図を示す。この構造では、モールド樹脂が加
熱硬化する際に一旦ゲル化して周囲に流れ広がり
ワイヤ7が露出する恐れがあるため、塗布量を多
くしなければならない。そのため加熱硬化後の回
路基板5に占める面積が大きく実装密度を向上す
る上での欠点となる。第8図cは上述の欠点を軽
減するために行われている構造であり、モールド
樹脂40が流れ広がるのを防ぐために枠41が接
着剤42によつて回路基板5に固定された例の平
面図であり、dはそのAA断面図である。この例
では樹脂の塗布量と固着面積についての改善はみ
られるが、枠41を接着する工程が追加されるこ
ととなる。第7図aはその場合の作業フローチヤ
ートの概要であるが、ステツプ71〜74に示す
ように接着作業とモールド作業がそれぞれ必要と
なり加工費が高いという欠点がある。 FIG. 8a is a plan view of a portion where the semiconductor chip 6 and its wires 7 mounted on the circuit board 5 are sealed only with the molding resin 40, and FIG.
A cross-sectional view is shown. In this structure, when the molding resin heats and hardens, there is a risk that it will once gel and flow around and expose the wire 7, so the amount of application must be increased. Therefore, the area occupied by the circuit board 5 after heating and curing is large, which is a disadvantage in improving the packaging density. FIG. 8c shows a structure implemented to alleviate the above-mentioned drawbacks, and is a plan view of an example in which a frame 41 is fixed to the circuit board 5 with an adhesive 42 to prevent the mold resin 40 from flowing and spreading. Figure d is the AA cross-sectional view. In this example, an improvement can be seen in the amount of resin applied and the fixed area, but the process of gluing the frame 41 will be added. FIG. 7a shows an outline of the work flowchart in that case, but there is a drawback that the process costs are high because bonding work and molding work are required, respectively, as shown in steps 71 to 74.
また、上述の第8図に示した2つの例では第8
図b,dの断面図で示すようにモールドされた上
面は丸味があり平坦ではない。このことは、最近
の実装技術で重要視されている面実装技術
(Surface Mount Technology)による実装自動
化を適用することができない。すなわち、実装自
動化にはプリント配線板等の回路基板面に抵抗、
コンデンサ、コイル等多数のチツプ部品を搭載す
るために、多数のチツプ部品がそれぞれ収容され
たマガジンから各チツプ部品を空気による吸引ノ
ズルによつて吸着し、回路基板面の所定の位置ま
で運んで装着する自動実装装置が用いられる。そ
のため最近のチツプ部品は、吸引ノズルによつて
吸着できるようにチツプ部品の上面が平坦である
ことが条件の一つとなつている。ハイブリツド
ICも自動実装部品の対象となるためには、上面
が平坦であることが条件であるが、第8図に示し
た従来のモールドの形状はいずれも上面平坦の条
件を満足していない。 Furthermore, in the two examples shown in FIG.
As shown in the cross-sectional views of Figures b and d, the upper surface of the mold is rounded and not flat. This makes it impossible to apply mounting automation using surface mount technology, which has become important in recent mounting technologies. In other words, for automated mounting, resistors and
In order to mount a large number of chip parts such as capacitors and coils, each chip part is picked up by an air suction nozzle from a magazine containing a large number of chip parts, and then transported to a predetermined position on the circuit board surface and mounted. Automatic mounting equipment is used. Therefore, one of the requirements for recent chip parts is that the top surface of the chip part be flat so that it can be sucked by a suction nozzle. hybrid
In order for an IC to be an automatically mounted component, it must have a flat top surface, but none of the conventional mold shapes shown in FIG. 8 satisfy the condition of a flat top surface.
従来のモールド構造の一つに、図示は省略した
が、金型を用いてモールド樹脂を圧入して形成す
るトランスフアー成型法による構造がある。この
方法は上面平坦モールド品が得られるが、金型と
圧入装置が高価であり、大量生産には適している
が、最近の機器の多様化に伴う多品種少量生産に
は適さない。 Although not shown in the drawings, one of the conventional mold structures is a structure based on a transfer molding method in which a mold resin is press-fitted using a metal mold. Although this method allows molded products with a flat top surface to be obtained, the mold and press-fitting equipment are expensive, and although it is suitable for mass production, it is not suitable for high-mix, low-volume production due to the recent diversification of equipment.
(本考案の目的)
本考案の目的は、上述のような欠点を解決する
ために、上面平坦で、しかも簡単なモールド作業
によつて樹脂モールドすることのできる混成集積
回路用樹脂モールドケースを提供することにあ
る。(Purpose of the present invention) In order to solve the above-mentioned drawbacks, the purpose of the present invention is to provide a resin molded case for a hybrid integrated circuit that has a flat top surface and can be resin-molded by a simple molding operation. It's about doing.
(考案の構成と作用)
本考案による混成集積回路用樹脂モールドケー
スは、混成集積回路の基板上に実装された電子部
品及び半導体チツプと該半導体チツプの配線用ワ
イヤとを保護するために、
前記実装された電子部品及び半導体チツプとワ
イヤとを囲む内周により形成される空間を有し、
該電子部品及び半導体チツプとワイヤの高さより
高い寸法の方形状枠と、
該枠の底面に固着した肉薄の加熱硬化形樹脂層
と、
前記枠の外周と等しいかまたはそれ以下の外周
の面積を有する上面が平坦な方形平板状の上蓋
と、
該上蓋の底面に固着し前記枠の内周より大きく
外周より小さい外周を有し前記上蓋を前記枠に載
せて前記空間内に収容された状態の電子部品及び
半導体チツプを加熱硬化によりモールドすべき加
熱硬化形モールド樹脂層と
より構成されたことを特徴とするものである。(Structure and operation of the invention) The resin molded case for a hybrid integrated circuit according to the invention has the above-mentioned features in order to protect the electronic components and semiconductor chips mounted on the substrate of the hybrid integrated circuit, and the wiring wires of the semiconductor chips. It has a space formed by an inner periphery surrounding the mounted electronic components and semiconductor chips and wires,
A rectangular frame with dimensions higher than the height of the electronic components, semiconductor chips and wires, a thin thermosetting resin layer fixed to the bottom of the frame, and an outer circumferential area equal to or less than the outer circumference of the frame. a rectangular plate-shaped upper lid having a flat upper surface; and a rectangular plate-shaped upper lid having a flat upper surface; and an outer periphery fixed to the bottom surface of the upper lid and larger than the inner periphery of the frame and smaller than the outer periphery of the frame, and the upper lid is placed on the frame and housed in the space. It is characterized by comprising a heat-curing molding resin layer on which electronic parts and semiconductor chips are molded by heat-curing.
以下図面により本考案を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第1図は、本考案の第1の実施例を示す斜視図
である。第1図aは混成集積回路基板5に実装さ
れた半導体チツプ6とその配線用ワイヤ7を、本
考案による接着用樹脂層2が固着された枠1とモ
ールド樹脂層4が固着された上蓋3とによつて封
止する状態を上方斜めから見た図であり、第1図
bは下方斜めから見た図である。 FIG. 1 is a perspective view showing a first embodiment of the present invention. FIG. 1a shows a semiconductor chip 6 mounted on a hybrid integrated circuit board 5 and its wiring wires 7, a frame 1 to which an adhesive resin layer 2 according to the present invention is fixed, and an upper lid 3 to which a mold resin layer 4 is fixed. FIG. 1b is a view obliquely viewed from above, and FIG. 1b is a view obliquely viewed from below.
第2図は本考案のモールドケースによつて回路
基板5上の半導体チツプを封止した後の外観を示
す斜視図である。第3図aはその平面図、bは
AA断面図を示す。第2図の10は外部電極を示
し、第3図bの4′は加熱硬化後のモールド樹脂
を示す。他の番号はすべて第1図の場合と同一の
部分を示す。 FIG. 2 is a perspective view showing the appearance of the semiconductor chip on the circuit board 5 after being sealed with the molded case of the present invention. Figure 3 a is its plan view, b is
AA cross-sectional view is shown. Reference numeral 10 in FIG. 2 indicates the external electrode, and reference numeral 4' in FIG. 3b indicates the molded resin after being heated and hardened. All other numbers indicate the same parts as in FIG.
第4図は、第1図の実施例の上蓋3を枠1の上
に載せた状態を示す縦断面図であり、加熱硬化前
の状態である。a〜cの違いは、上蓋3の大きさ
である。上蓋3に固着されたモールド樹脂層4の
面積は、a,b,cともに枠1の外周より小さく
枠の内周より大きく、枠1に載せたとき内側の空
間に収容された半導体チツプ6のワイヤ7に接触
しないような寸法であり、加熱してモールド樹脂
層4がゲル化したとき枠1の内側に流れ込むよう
になつている。上蓋3の面積は、aの場合は枠1
の外形に等しくモールド樹脂層が内部空間に充填
されたとき枠1の上面に接して全体の蓋となる。
bの場合は枠1の外形より小さく内形より大きい
のでモールド後はaと同様に枠1の上面に接した
状態となる。cの場合は枠1の内形より小さいた
めモールド後は枠1の内側に嵌まつた形となる。
いずれも加熱硬化によるモールド封止効果は同じ
であるが、bの場合は上蓋3とモールド樹脂層4
の面積は等しいので、樹脂層4が固着した状態の
上蓋3を製作するとき、数十倍の面積の上蓋材に
樹脂層を固着した後所望の寸法に裁断することに
よつて多数の樹脂層付き上蓋を生産することがで
きるため量産性に優れている。 FIG. 4 is a longitudinal sectional view showing the upper lid 3 of the embodiment shown in FIG. 1 placed on the frame 1, and shows the state before being heated and hardened. The difference between a to c is the size of the upper lid 3. The areas a, b, and c of the molded resin layer 4 fixed to the upper lid 3 are smaller than the outer circumference of the frame 1 and larger than the inner circumference of the frame, and when placed on the frame 1, the area of the semiconductor chip 6 accommodated in the inner space is The size is such that it does not come into contact with the wire 7, and when the molded resin layer 4 is heated and gelled, it flows into the inside of the frame 1. The area of the upper lid 3 is frame 1 in case of a.
When the inner space is filled with a molded resin layer equal to the outer shape of the frame 1, it comes into contact with the upper surface of the frame 1 and forms a lid for the entire frame.
In the case of b, the outer diameter is smaller than the inner diameter of the frame 1, so after molding, it will be in contact with the top surface of the frame 1, as in the case of a. In the case of c, since it is smaller than the inner shape of the frame 1, it will fit inside the frame 1 after molding.
The mold sealing effect by heat curing is the same in both cases, but in the case of b, the upper lid 3 and the mold resin layer 4
Since the areas of are equal, when manufacturing the top cover 3 with the resin layer 4 fixed, the resin layer is fixed to the top cover material several tens of times the area and then cut to the desired size to create a large number of resin layers. It has excellent mass productivity because it can produce a top cover with a lid.
モールド樹脂層4の量(体積)は、加熱硬化し
た後少なくとも半導体チツプ6とワイヤ7が覆わ
れ上蓋3に部分的に接合されておればよく、多く
ても上蓋3の周囲から多少はみ出す程度で実験的
に求められる。 The amount (volume) of the mold resin layer 4 should be such that at least the semiconductor chip 6 and the wire 7 are covered and partially bonded to the top cover 3 after being heated and hardened, and at most it should protrude slightly from the periphery of the top cover 3. Required experimentally.
第5図a,bは本考案による第2の応用実施例
を示す平面図とAA断面図である。前述の第1の
実施例と異なる点は、上蓋3に固着する樹脂層2
2が枠1の上面が接する部分にのみ形成されてい
るところである。この構造は半導体チツプ6が既
に例えばシリコンによつてコーテイングされてい
るとき、そのワイヤを保護する場合に用いられ
る。 FIGS. 5a and 5b are a plan view and a sectional view along line AA, showing a second applied embodiment of the present invention. The difference from the first embodiment described above is that the resin layer 2 fixed to the upper lid 3
2 is formed only in the portion where the upper surface of the frame 1 contacts. This structure is used to protect the wires when the semiconductor chip 6 is already coated, for example with silicon.
第5図c,dは本考案による第3の応用実施例
を示す平面図とAA断面図である。この場合は封
止対象は多種多数の寸法の異なるチツプ状電子部
品9であり、面実装用として上面を平坦にするこ
とを目的とした箱形ケース8の基板接合面に接着
用樹脂層2を固着させた構造である。 FIGS. 5c and 5d are a plan view and an AA sectional view showing a third applied embodiment of the present invention. In this case, the objects to be sealed are a wide variety of chip-shaped electronic components 9 with different dimensions, and an adhesive resin layer 2 is applied to the substrate bonding surface of the box-shaped case 8, which is intended to have a flat top surface for surface mounting. It is a fixed structure.
第5図e,fは第4の実施例を示す平面図と
AA断面図である。この実施例の保護モールドの
対象は半導体チツプ6とチツプ状電子部品9であ
る。他の番号も第5図a〜dで説明したものと同
じである。 Figures 5e and 5f are plan views showing the fourth embodiment.
It is an AA sectional view. The objects of the protective mold in this embodiment are a semiconductor chip 6 and a chip-shaped electronic component 9. The other numbers are also the same as those explained in FIGS. 5a to 5d.
第6図は本考案による接着用樹脂層2及びモー
ルド樹脂層4について説明するための樹脂反応曲
線を示す特性図である。この特性図は例えば100
〜160℃の加熱槽の中での加熱時間に対する樹脂
の形状変化を示すもので、枠1及び上蓋3の上に
固着させる樹脂は時間t1とt2との中間の所定の時
間を経過後に加熱槽から取り出して冷却し、固形
状となつたものを使用する。この状態の樹脂は本
硬化時よりは接着強度は弱いが取り扱い時に剥離
する心配はない。このようにして形成された本考
案による接着用樹脂層2付き枠1及びモールド樹
脂層4付き上蓋3を混成集積回路基板上に封止用
モールドケースとして実装するときは、所定の位
置に載置して加熱することによつて再び第6図の
ゲル状になり、そのまま加熱を続けることによ
り、硬化が始まり充分な時間後本硬化の状態とな
つてモールドが完成される。 FIG. 6 is a characteristic diagram showing resin reaction curves for explaining the adhesive resin layer 2 and the mold resin layer 4 according to the present invention. This characteristic diagram is for example 100
This shows the change in the shape of the resin with respect to the heating time in a heating tank at ~ 160 ° C. Take it out from the heating tank, cool it, and use it when it becomes solid. Although the adhesive strength of the resin in this state is weaker than that when it is fully cured, there is no need to worry about it peeling off during handling. When mounting the frame 1 with the adhesive resin layer 2 and the upper cover 3 with the mold resin layer 4 formed in this way on a hybrid integrated circuit board as a mold case for sealing, place them in a predetermined position. By heating it, it becomes the gel-like state shown in FIG. 6 again, and by continuing to heat it, it begins to harden, and after a sufficient period of time, it reaches a fully hardened state and the mold is completed.
本考案の封止用モールドケースを応用すれば、
従来第7図aの71〜74の4ステツプの作業が
第7図bに示したように75,76の2ステツプ
で電子部品及び半導体チツプの樹脂モールドが完
成され、作業工程の低減に大きい効果がある。 By applying the sealing mold case of this invention,
Conventionally, the 4 steps 71 to 74 in FIG. 7a are now completed in 2 steps 75 and 76 as shown in FIG. 7b, which greatly reduces the number of work steps. There is.
(考案の効果)
以上詳細に説明したように、本考案の封止用モ
ールドケースを使用することにより、混成集積回
路の半導体チツプ等の樹脂モールド作業工数が低
減し、上面平坦構造であるためその完成品は実装
自動化の面実装部品の対象製品の条件を備えるた
め著しい効果がある。(Effects of the invention) As explained in detail above, by using the mold case for sealing of the invention, the number of man-hours required for resin molding of semiconductor chips, etc. of hybrid integrated circuits is reduced. The finished product has a significant effect because it meets the requirements for surface mount components for mounting automation.
第1図は本考案による一実施例を示す斜視図、
第2図は本考案を応用した構造を示す斜視図、第
3図は本考案を応用した製品の構造図、第4図は
本考案を応用した製品の断面図、第5図は本考案
の第2、第3及び第4の実施例を示す構造図、第
6図は本考案の一部を説明する特性図、第7図a
は従来のフローチヤート例、bは本考案によるフ
ローチヤート、第8図は従来の構造例を示す平面
図と断面図である。
1……枠、2,22……接着層、3……上蓋、
4……モールド樹脂層、4′……モールド樹脂、
5……回路基板、6……半導体チツプ、7……ワ
イヤ、8……箱形ケース、9……電子部品、10
……外部電極、40……モールド樹脂、41……
枠、42……接着剤、71〜76……ステツプ番
号。
FIG. 1 is a perspective view showing an embodiment of the present invention;
Figure 2 is a perspective view showing a structure to which the present invention is applied, Figure 3 is a structural diagram of a product to which the present invention is applied, Figure 4 is a sectional view of a product to which the present invention is applied, and Figure 5 is a diagram of the product to which the present invention is applied. Structural diagrams showing the second, third and fourth embodiments; FIG. 6 is a characteristic diagram illustrating a part of the present invention; FIG. 7 a
8 is a conventional flowchart example, b is a flowchart according to the present invention, and FIG. 8 is a plan view and a sectional view showing a conventional structural example. 1...Frame, 2, 22...Adhesive layer, 3...Top lid,
4...Mold resin layer, 4'...Mold resin,
5... Circuit board, 6... Semiconductor chip, 7... Wire, 8... Box-shaped case, 9... Electronic component, 10
...External electrode, 40...Mold resin, 41...
Frame, 42...Adhesive, 71-76...Step number.
Claims (1)
び半導体チツプと該半導体チツプの配線用ワイヤ
とを保護するために、 前記実装された電子部品及び半導体チツプとワ
イヤとを囲む内周により形成される空間を有し、
該電子部品及び半導体チツプとワイヤの高さより
高い寸法の方形状枠と、 該枠の底面に固着した肉薄の加熱硬化形樹脂層
と、 前記枠の外周と等しいかまたはそれ以下の外周
の面積を有する上面が平坦な方形平板状の上蓋
と、 該上蓋の底面に固着し前記枠の内周より大きく
外周より小さい外周を有し前記上蓋を前記枠に載
せて前記空間内に収容された状態の電子部品及び
半導体チツプを加熱硬化によりモールドすべき加
熱硬化形モールド樹脂層と、 より構成された混成集積回路用樹脂モールドケー
ス。[Claims for Utility Model Registration] In order to protect the electronic components and semiconductor chips mounted on the substrate of the hybrid integrated circuit and the wiring wires of the semiconductor chips, has a space formed by an inner periphery surrounding the
A rectangular frame with dimensions higher than the height of the electronic components, semiconductor chips and wires, a thin thermosetting resin layer fixed to the bottom of the frame, and an outer circumferential area equal to or less than the outer circumference of the frame. a rectangular plate-shaped upper lid having a flat upper surface; and a rectangular plate-shaped upper lid having a flat upper surface; and an outer periphery fixed to the bottom surface of the upper lid and larger than the inner periphery of the frame and smaller than the outer periphery of the frame, and the upper lid is placed on the frame and housed in the space. A resin mold case for a hybrid integrated circuit comprising a thermosetting mold resin layer for molding electronic components and semiconductor chips by heat curing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989124531U JPH0530363Y2 (en) | 1989-10-26 | 1989-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989124531U JPH0530363Y2 (en) | 1989-10-26 | 1989-10-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0363946U JPH0363946U (en) | 1991-06-21 |
| JPH0530363Y2 true JPH0530363Y2 (en) | 1993-08-03 |
Family
ID=31672442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989124531U Expired - Lifetime JPH0530363Y2 (en) | 1989-10-26 | 1989-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0530363Y2 (en) |
-
1989
- 1989-10-26 JP JP1989124531U patent/JPH0530363Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0363946U (en) | 1991-06-21 |
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