JPH05304477A - 標本化回路 - Google Patents
標本化回路Info
- Publication number
- JPH05304477A JPH05304477A JP4317057A JP31705792A JPH05304477A JP H05304477 A JPH05304477 A JP H05304477A JP 4317057 A JP4317057 A JP 4317057A JP 31705792 A JP31705792 A JP 31705792A JP H05304477 A JPH05304477 A JP H05304477A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- values
- storage means
- sampling
- identity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Color Television Systems (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Tests Of Electronic Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4139340.6 | 1991-11-29 | ||
| DE4139340A DE4139340A1 (de) | 1991-11-29 | 1991-11-29 | Schaltungsanordnung zum abtasten eines signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05304477A true JPH05304477A (ja) | 1993-11-16 |
Family
ID=6445883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4317057A Pending JPH05304477A (ja) | 1991-11-29 | 1992-11-26 | 標本化回路 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5345453A (de) |
| EP (1) | EP0545493A3 (de) |
| JP (1) | JPH05304477A (de) |
| DE (1) | DE4139340A1 (de) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528165A (en) * | 1995-04-03 | 1996-06-18 | Sun Microsystems, Inc. | Logic signal validity verification apparatus |
| US6907538B1 (en) | 2001-10-16 | 2005-06-14 | Analog Devices, Inc. | Circuit and method for providing centralized synchronization for the transportation of data between devices in a different clock domains on a data bus |
| DE10355187B4 (de) * | 2003-11-26 | 2006-05-24 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Timinganalyse einer Schaltung |
| US20070073933A1 (en) * | 2005-09-13 | 2007-03-29 | International Business Machines Corporation | Asynchronous interface with vectored interface controls |
| EP2721382B1 (de) | 2011-05-18 | 2023-01-18 | Samuel Walker Inman | Unregelmässige erregung optischer sensoren |
| KR20210054545A (ko) | 2018-08-31 | 2021-05-13 | 루시드 사이언티픽, 인코포레이티드 | 동적 시스템의 측정 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3140431C2 (de) * | 1980-10-13 | 1986-09-25 | Hitachi, Ltd., Tokio/Tokyo | Demodulatorschaltung zum Demodulieren eines modulierten Digitalsignals |
| US4513387A (en) * | 1982-07-13 | 1985-04-23 | Lgz Landis & Gyr Zug Ag | Method and an apparatus for generating periodic digital time function signals |
| US4999528A (en) * | 1989-11-14 | 1991-03-12 | Keech Eugene E | Metastable-proof flip-flop |
-
1991
- 1991-11-29 DE DE4139340A patent/DE4139340A1/de not_active Withdrawn
-
1992
- 1992-11-24 US US07/980,816 patent/US5345453A/en not_active Expired - Fee Related
- 1992-11-26 JP JP4317057A patent/JPH05304477A/ja active Pending
- 1992-11-30 EP EP19920203690 patent/EP0545493A3/de not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US5345453A (en) | 1994-09-06 |
| EP0545493A2 (de) | 1993-06-09 |
| EP0545493A3 (en) | 1993-11-03 |
| DE4139340A1 (de) | 1993-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6279090B1 (en) | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device | |
| US9524759B2 (en) | Apparatuses and methods for capturing data using a divided clock | |
| US6493829B1 (en) | Semiconductor device enable to output a counter value of an internal clock generation in a test mode | |
| US6456561B2 (en) | Synchronous semiconductor memory device | |
| JPS6232511B2 (de) | ||
| US4864570A (en) | Processing pulse control circuit for use in device performing signature analysis of digital circuits | |
| KR20000023473A (ko) | 시험 시간을 감소시키기 위한 내부 클럭 곱셈 | |
| JPH05304477A (ja) | 標本化回路 | |
| JPH02283120A (ja) | 雑音除去装置 | |
| US20110234282A1 (en) | Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope | |
| US12549167B2 (en) | Sampling signals | |
| US4689791A (en) | Device for translating a test sequence to a burn-in sequence for a logic circuit and/or a digital circuit, a method for burn-in operation of a logic circuit and/or a digital circuit | |
| US7504864B2 (en) | Method for controlling the evaluation time of a state machine | |
| US6378092B1 (en) | Integrated circuit testing | |
| KR20060109281A (ko) | Lsi의 테스트 방법 | |
| JPH0776782B2 (ja) | シグネチャ圧縮回路 | |
| KR100236727B1 (ko) | 주기발생장치 | |
| US12231116B1 (en) | Digital power on reset circuit and method | |
| US10417104B2 (en) | Data processing system with built-in self-test and method therefor | |
| JPS6316276A (ja) | 半導体集積回路 | |
| JP2002196049A (ja) | Ic試験装置 | |
| WO1999059156A1 (en) | Method and apparatus for implementing a learn instruction in a content addressable memory device | |
| RU1805471C (ru) | Устройство дл контрол логических блоков | |
| US7508239B2 (en) | Pattern sequence and state transition triggers | |
| JP3475018B2 (ja) | データロード回路 |