JPH05308090A - Tab type semiconductor device - Google Patents

Tab type semiconductor device

Info

Publication number
JPH05308090A
JPH05308090A JP8017192A JP8017192A JPH05308090A JP H05308090 A JPH05308090 A JP H05308090A JP 8017192 A JP8017192 A JP 8017192A JP 8017192 A JP8017192 A JP 8017192A JP H05308090 A JPH05308090 A JP H05308090A
Authority
JP
Japan
Prior art keywords
projection
inner lead
semiconductor substrate
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8017192A
Other languages
Japanese (ja)
Other versions
JP2739797B2 (en
Inventor
Seiji Gomi
誠治 五味
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4080171A priority Critical patent/JP2739797B2/en
Publication of JPH05308090A publication Critical patent/JPH05308090A/en
Application granted granted Critical
Publication of JP2739797B2 publication Critical patent/JP2739797B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable an inner lead to be connected to the substrate for a semiconductor device without necessitating bump forming and without causing the inner lead to touch the subtrate by forming a projection in the section of the semiconductor substrate to which the inner lead is connected so as to protrude from the surface of the substrate. CONSTITUTION:A substrate 2 of a semiconductor device is fabricated so that projection 5a is formed in advance in the section of substrate to which lead-out electrode 3 is connected. Further, this projection 5a can be obtained by selectively etching the surface of the semiconductor substrate 2 before fabricating an integrated circuit on the surface of the semiconductor substrate 2. An inner lead 1 is then connected to the electrode 3 drawn out onto the thus formed projection 5a. Since the peripheral section of this lead-out electrode 3 is lower than the connecting section, the inner lead 1 does not touch the semiconductor substrate 2. Furthermore, when forming the projection 5b, the semiconductor substrate 2 may be formed by selectively growing it in advance. In this case, since the projection does not generate undercut in the periphery thereof, the projection is superior in strength to the others.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、TAB(Tape A
utomated Bonding)型半導体装置に関
する。
BACKGROUND OF THE INVENTION The present invention relates to TAB (Tape A
The present invention relates to an automated bonding type semiconductor device.

【0002】[0002]

【従来の技術】図2は従来のTAB型半導体装置の一例
におけるチップを示す断面図である。従来のTAB型半
導体装置は図2に示すように、一面に集積回路が形成さ
れるとともにこの集積回路の入出力端子である引き出し
電極3にバンプ4が形成される半導体基板2と、このバ
ンプ4に接続されるインナーリード1を有していた。
2. Description of the Related Art FIG. 2 is a sectional view showing a chip in an example of a conventional TAB semiconductor device. As shown in FIG. 2, a conventional TAB type semiconductor device has a semiconductor substrate 2 on which an integrated circuit is formed on one surface and bumps 4 are formed on lead electrodes 3 which are input / output terminals of the integrated circuit, and the bumps 4. Had an inner lead 1 connected to.

【0003】このバンプ4はインナーリード1と引き出
し電極3を接続させているが、インナーリード1と半導
体基板2を接触させないように凸状に形成されている。
また、このバンプ4の材質としては金,白金,チタンよ
り構成されたり、金,アルミニウムより構成されたりし
ている。
The bump 4 connects the inner lead 1 and the extraction electrode 3, but is formed in a convex shape so as not to contact the inner lead 1 and the semiconductor substrate 2.
The material of the bumps 4 is gold, platinum, titanium, or gold or aluminum.

【0004】さらに、バンプ4の形成方法としては直接
半導体基板2へ熱圧着や半田付により形成する方法や、
転写バンプ方式のような永久基板を利用してインナーリ
ード1側にバンプ4を形成する方法がある。
Further, as a method of forming the bump 4, a method of directly forming the bump 4 on the semiconductor substrate 2 by thermocompression bonding or soldering,
There is a method of forming bumps 4 on the inner lead 1 side using a permanent substrate such as a transfer bump method.

【0005】[0005]

【発明が解決しようとする課題】この従来のTAB型半
導体装置では、これらのバンプを形成する技術は複雑で
あるため、今日でも、製造上の品質管理や工期短縮の点
で多くの改善を必要としていた。
In this conventional TAB type semiconductor device, since the technique for forming these bumps is complicated, even today, many improvements are required in terms of manufacturing quality control and shortening of the construction period. I was trying.

【0006】本発明の目的は、製造技術上種々の問題を
引き起すバンプを形成することなく、インナーリードと
引き出し電極とを接続することの出来るTAB型半導体
装置を提供することである。
An object of the present invention is to provide a TAB type semiconductor device capable of connecting an inner lead and an extraction electrode without forming a bump which causes various problems in manufacturing technology.

【0007】[0007]

【課題を解決するための手段】本発明のTAB型半導体
装置は、インナーリードと半導体基板上の引き出し電極
が接続しているTAB型半導体装置において、前記イン
ナーリードに対応する前記半導体基板の部分に突出部が
形成されていることを特徴としている。
A TAB type semiconductor device of the present invention is a TAB type semiconductor device in which an inner lead and a lead electrode on a semiconductor substrate are connected to each other, in a portion of the semiconductor substrate corresponding to the inner lead. It is characterized in that a protrusion is formed.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0009】図1(a)及び(b)は本発明のTAB型
半導体装置の一実施例におけるチップを示す断面図であ
る。このTAB型半導体装置は、図1(a)に示すよう
に、引き出し電極3が接続される部分にあらかじめ形成
される突出部5aを設けたことてある。それ以外は従来
例と並じである。また、この突出部5aは、半導体基板
2の面に集積回路を形成する前に選択的に半導体基板2
の面をエッチングすることにより得られる。
1A and 1B are sectional views showing a chip in an embodiment of a TAB type semiconductor device of the present invention. In this TAB type semiconductor device, as shown in FIG. 1A, a protruding portion 5a formed in advance is provided in a portion to which the extraction electrode 3 is connected. Other than that is the same as the conventional example. In addition, the protruding portion 5a is selectively formed on the surface of the semiconductor substrate 2 before forming an integrated circuit.
It is obtained by etching the surface of.

【0010】このように突出部5aを形成することによ
り、突出部5a上の引き出し電極3にインナーリード1
を接続させる。この引き立し電極3の周囲はこの接続部
より低いため、インナーリード1は半導体基板2に接触
しない。
By forming the protrusion 5a in this manner, the inner lead 1 is attached to the lead electrode 3 on the protrusion 5a.
To connect. Since the circumference of the upstanding electrode 3 is lower than this connecting portion, the inner lead 1 does not contact the semiconductor substrate 2.

【0011】また、図1(b)に示すように、突出部5
bを形成する際に、半導体基板2をあらかじめ選択的に
成長させて形成させても良い。この場合は、突出部の周
囲にアンダーカットが生じないので、強度的に有利であ
る。
Further, as shown in FIG. 1B, the protrusion 5
When forming b, the semiconductor substrate 2 may be selectively grown in advance and formed. In this case, undercut does not occur around the protrusion, which is advantageous in strength.

【0012】[0012]

【発明の効果】以上説明したように本発明は、インナー
リードと接続する半導体基板の部分に表面より突出する
突出部を設けることによって、バンプ形成を行なう必要
がなく、インナーリードが半導体基板と接触することな
く接続出来るという効果がある。
As described above, according to the present invention, by providing the projecting portion projecting from the surface on the portion of the semiconductor substrate connected to the inner lead, it is not necessary to form bumps, and the inner lead contacts the semiconductor substrate. There is an effect that you can connect without doing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のTAB型半導体装置の一実施例におけ
るチップを示す断面図である。
FIG. 1 is a sectional view showing a chip in an embodiment of a TAB type semiconductor device of the present invention.

【図2】従来のTAB型半導体装置の一例におけるチッ
プを示す断面図である。
FIG. 2 is a cross-sectional view showing a chip in an example of a conventional TAB type semiconductor device.

【符号の説明】[Explanation of symbols]

1 インナーリード 2 半導体基板 3 引き出し電極 4 バンプ 5a,5b 突出部 1 inner lead 2 semiconductor substrate 3 extraction electrode 4 bumps 5a, 5b protrusion

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 インナーリードと半導体基板上の引き出
し電極が接続しているTAB型半導体装置において、前
記インナーリードに対応する前記半導体基板の部分に突
出部が形成されていることを特徴とするTAB型半導体
装置。
1. A TAB type semiconductor device in which an inner lead is connected to a lead-out electrode on a semiconductor substrate, wherein a TAB is formed at a portion of the semiconductor substrate corresponding to the inner lead. Type semiconductor device.
JP4080171A 1992-04-02 1992-04-02 TAB type semiconductor device Expired - Fee Related JP2739797B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4080171A JP2739797B2 (en) 1992-04-02 1992-04-02 TAB type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4080171A JP2739797B2 (en) 1992-04-02 1992-04-02 TAB type semiconductor device

Publications (2)

Publication Number Publication Date
JPH05308090A true JPH05308090A (en) 1993-11-19
JP2739797B2 JP2739797B2 (en) 1998-04-15

Family

ID=13710891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4080171A Expired - Fee Related JP2739797B2 (en) 1992-04-02 1992-04-02 TAB type semiconductor device

Country Status (1)

Country Link
JP (1) JP2739797B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322448A (en) * 1989-06-19 1991-01-30 Nec Corp Lead frame for tab type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322448A (en) * 1989-06-19 1991-01-30 Nec Corp Lead frame for tab type semiconductor device

Also Published As

Publication number Publication date
JP2739797B2 (en) 1998-04-15

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Effective date: 19971224

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