JPH05308100A - Wiring method of logic IC circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the signal delay and signal attenuation by shortening the wiring length to operate the IC circuit at high speed. A NOR circuit composed of DCFL logic gates is divided at the transistor level. The divided switching FETs 1, 3, 4, 6 and the current source FETs 2, 5 are
They are arranged and connected so that the wiring distance between them is the shortest in the range where a predetermined IC function can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for a high speed logic IC circuit, and more particularly to a wiring method for a logic IC circuit designed to realize a predetermined logic function by using a DCFL logic gate.

[0002]

2. Description of the Related Art Among logic IC circuits, a GaAs IC circuit is known as one suitable for high speed operation. This G
In the aAsIC circuit, DCFL (Direct Coupled
FET Logic) logic gates are widely used as one of the basic circuits for the logic.

FIG. 2A shows an example of a DCFL logic gate. This DCFL gate circuit is configured by combining a plurality of (two in the illustrated example) switching FETs 9 and 10 and one current source FET 8 that is a load element. This DCFL logic gate has N as shown in FIG.
It corresponds to the OR circuit 11.

When a plurality of DCFL logic gates are combined to realize a predetermined logic function, a configuration is generally adopted in which the combination of logic gates is arranged so as to be easily understood. That is, N
The OR circuit 11 is used as one basic unit, and the FETs constituting each basic unit are arranged in proximity to each other and the plural basic units are connected by wiring.

[0005]

However, when the logic combinations are arranged in an easily understandable manner as described above, there are the following problems. That is, for example, as shown in FIG.
In the case where the R circuits 12 and 13 are combined to form a latch circuit, the two NOR circuits 12 and 13 are separated from each other due to a large difference between the input position of the latch and the output position of the latch or the layout of the NOR circuit 12 and 13 at the time of incorporation into the substrate. It may be placed at a remote location on the substrate. FIG. 4 shows the circuit configuration in this case at a transistor level. The NOR circuit 12 is composed of the current source FET2 and the switching FETs 1 and 3, and the current source FET5 and the switching FET4 are composed of
The NOR circuits 13 are each constituted by 6. The switching FET 7 is, for example, a NOR circuit (not shown) at the next stage. The broken lines in these figures mean that they are separated in position (the same applies hereinafter).

When the NOR circuit 12 at the front stage and the NOR circuit 13 at the rear stage are separated from each other in this manner, one of the input terminals of the NOR circuit 12 at the front stage outputs the output of the NOR circuit 13 at the rear stage as shown in the figure. May be connected to terminals. In this case, in addition to the wiring L1 between the NOR gate circuits 12 and 13, a wiring L2 having a long distance for connecting one of the input terminals of the NOR circuit 12 in the previous stage to the output terminal of the NOR circuit 13 in the subsequent stage is included. Therefore, the latch circuit or I
The wiring length in the entire C circuit becomes very long.
When the total wiring length is long, the wiring delay in the latch circuit or the IC circuit becomes large, which causes a problem that the high-speed operation of the circuit is hindered.

The wiring width on the IC circuit is usually about several μm. This wiring is CR in terms of distribution constant
Since it is equivalent to a circuit having a time constant of, when the wiring length is very long as described above, the switching transistor is
The discharge in the wiring is large when it becomes N, that is, the discharge in the wiring (discharge by wiring resistance, between wirings or wiring layer and IC
Since the amount of signal attenuation due to the discharge due to the electrostatic capacitance between the substrates and the like becomes large, the signal transmission to the next stage is not performed well, and it becomes difficult to perform the desired circuit operation.

When the circuit integration further progresses and the total wiring amount increases and the wiring width becomes smaller, the switching time becomes longer due to the increase in wiring resistance, which hinders high-speed operation in the IC circuit. There is a problem that

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wiring method for a high speed logic IC circuit, which can shorten the wiring length to minimize signal delay and signal attenuation and thereby operate the logic IC circuit at high speed. And

[0010]

High-speed logic IC of the present invention
The wiring method of the circuit is to arrange and connect the switching transistor and the load element forming the DCFL logic gate so that the wiring distance between the DCFL logic gates is the shortest in the range where a predetermined logic function can be realized. ..

The load element is preferably arranged near the switching transistor of the next-stage DCFL logic gate.

[0012]

As described above, the DCFL logic gate is divided into internal element levels, and the transistors and load elements are arranged and connected so that the wiring distance between the logic gates at the internal element level is the shortest. The wiring length can be minimized. As a result, wiring delay and wiring resistance are reduced, and the logic IC circuit can be operated at high speed.

Further, by disposing the load element near the switching transistor of the next-stage DCFL logic gate,
The decrease in the wiring impedance makes the rise and fall of the signal waveform steep, which allows the speed of the entire circuit to be increased.

[0014]

EXAMPLES Examples of the present invention will be described below. FIG. 1 shows an example of rewiring the latch circuit shown in FIG. 3 by the wiring method of the present invention so that the total wiring length becomes the shortest.
This procedure will be described below. The two NOR circuits 12 and 13 forming the latch circuit are composed of FETs 1 to 3 and FETs 4 to 6, respectively, as in the case of FIG.
That is, the NOR circuit 12 is composed of the current source FET 2 and the switching FETs 1 and 3, and the NOR circuit 13 is composed of the current source FET 5 and the switching FETs 4 and 6. Here, attention is paid to the switching FET 3 that belongs to the NOR circuit 12 at the front stage and has its gate electrode connected to the output side of the NOR circuit 13 at the rear stage. Then, this switching FET 3 is separated from the switching FET 1 and is arranged in close proximity to one switching FET 4 constituting the NOR circuit 13 in the subsequent stage, and the switching FET 4 is cross-connected as shown in FIG. To get it.

By connecting the switching FETs 3 in different arrangements as described above, the long wiring L shown in FIGS.
2 can be eliminated, and the total wiring length can be shortened accordingly. Then, by arranging similar arrangements and connections, the total wiring length of the entire IC circuit can be empirically reduced by 20% or more.

Further, the other switching FET 6 constituting the NOR circuit 13 is arranged adjacent to the switching FET 7 of the next stage. Further, the current source FE of the NOR circuit 12
T2 is the switching FETs 3 and 4, and the NOR circuit 1
The current source FET 5 of No. 3 is arranged close to the switching FETs 6 and 7, respectively. By arranging the current source FETs 2 and 5 in this way, the circuit speed can be increased due to the reduction in wiring impedance.

In this embodiment, the current source FET is used as the load element of the DCFL logic gate, but a resistor may be used instead.

[0018]

As described above, according to the wiring method for the high-speed logic IC circuit of the present invention, the wiring length can be shortened to minimize the signal delay and the signal attenuation. As a result, the IC circuit can be operated at high speed. It becomes possible.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example in which transistors are arranged and connected by the method of the present invention.

FIG. 2A is an explanatory diagram of a DCFL logic gate, and FIG.
Is an explanatory diagram in which the DCFL circuit is expressed by a NOR circuit.

FIG. 3 is an explanatory diagram of a latch circuit configured by a NOR circuit.

FIG. 4 is an explanatory diagram showing an arrangement of transistors in a latch circuit.

[Explanation of symbols]

1, 3, 4, 6, 7, 9, 10 ... Switching FET,
2, 5, 8 ... Current source FETs, 11, 12, 13 ... NOR
circuit.

Claims (2)

[Claims] 1. A logic IC circuit for realizing a predetermined logic function by using a plurality of DCFL logic gates each comprising a load element and a switching transistor connected in series to the load element, wherein a switching transistor and a load forming the DCFL logic gate. A wiring method of a logic IC circuit, characterized in that elements are arranged and connected so that a wiring distance between DCFL logic gates is the shortest in a range in which the predetermined logic function can be realized. 2. The wiring method for a logic IC circuit according to claim 1, wherein the load element is arranged in the vicinity of a switching transistor of a DCFL logic gate at the next stage.