JPH05308577A - Noise reducing system for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To reduce a clock noise without deteriorating the frequency characteristic of a video signal. CONSTITUTION:The video signal outputted from a solid-state image pickup element 1 and including the clock noise, after being current/voltage-converted by a pre-amplifier 2, is inputted to a low-pass filter 3. The video signal in which the noise over a secondary higher harmonic is reduced at the low-pass filter 3 is added to a delay video signal in which the signal is delayed by the half cycle of the clock pulse via a delay circuit 4 at an adder circuit 5. Thereby, the clock noise can be offset, and the video signal in which the noise is reduced can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction system for a solid-state image pickup device, and more particularly to a noise reduction system for a solid-state image pickup device used in a high speed camera or the like for processing video signals in a wide band.

[0002]

2. Description of the Related Art Generally, a solid-state image pickup device is adapted to form a horizontal scanning clock pulse by using two clock pulses having different half-cycle phases and be driven by the horizontal scanning clock pulse or the like. The video signal read out from the solid-state image sensor is processed by the signal processing circuit having the configuration shown in FIG. That is,
In FIG. 3, 1 is a solid-state imaging device driven by two clock pulses HCK1 and HCK2 having different half-cycle phases, 2 is a preamplifier, 3 is a low-pass filter, and 6 is a sample hold circuit.

Next, the operation of the signal processing circuit of the solid-state image pickup device thus configured will be described with reference to the signal waveform diagram shown in FIG. First, the solid-state image sensor 1 is driven by a horizontal scanning clock pulse synthesized by two clock pulses HCK1 (a) and HCK2 (b), and the solid-state image sensor 1 synthesizes two video signals (c) together with a video signal (c). A signal [(c) + (d)] on which the clock noise (d) based on the clock pulse is superimposed is output. The signal [(c) + (d)] output from the solid-state imaging device 1 is current-voltage converted in the preamplifier 2 and input to the low-pass filter 3 to reduce the clock noise (d) and the sample hold circuit 6 Is input to and sample-held.

[0004]

In the conventional video signal processing circuit described above, when the frequency of the video signal is low, the low-pass filter 3 alone can sufficiently reduce the clock noise, but when the frequency of the video signal is in a wide band. The low pass filter 3 can reduce only the second harmonic of clock noise or more. Therefore, from the low-pass filter 3, a signal (f) = [(c) + (e)] in which the fundamental wave clock noise (e) having a frequency twice that of the clock pulse shown in FIG. , And is input to the sample hold circuit 6 in the subsequent stage.

As a result, the sample hold circuit 6 in the subsequent stage
However, since the signal (f) is sampled and held by the sample and hold pulse (g), there is a problem that the value to be held is changed due to a change in clock noise. Further, if a low-pass filter having a sharp characteristic is used to avoid this, there is a problem that the frequency characteristic of the video signal is deteriorated.

The present invention has been made to solve the above-mentioned problems in the conventional noise reduction system for a solid-state image pickup device, and can reduce clock noise without degrading the frequency characteristics of a video signal. An object of the present invention is to provide a noise reduction method for an image sensor.

[0007]

In order to solve the above problems, the present invention provides a solid-state image pickup device driven by using two clock pulses having different half-cycle phases.
A video signal including clock noise output from a solid-state image sensor and a delayed video signal obtained by delaying the half cycle phase of a clock pulse of the video signal are added.

Thus, by adding the video signal on which the clock noise is superimposed and the delayed video signal obtained by delaying the half cycle phase of the clock pulse to the video signal, the clock noise components cancel each other out and the clock noise component A reduced video signal is obtained.

[0009]

EXAMPLES Next, examples will be described. FIG. 1 is a block configuration diagram showing a noise reduction device for explaining an embodiment of a noise reduction method for a solid-state image pickup device according to the present invention. The same parts as those of the conventional signal processing circuit shown in FIG. It is shown with reference numerals. Reference numeral 1 is a solid-state image sensor using a CMD for converting an optical signal into an electric signal as a pixel,
Two clock pulses HCK1 and H having different half-cycle phases
It is driven by a horizontal scanning clock pulse or the like synthesized by CK2. Reference numeral 2 is a voltage follower type preamplifier that converts a current signal sent from the solid-state imaging device 1 into a voltage signal, 3 is a low-pass filter that reduces more than the second harmonic of clock noise, and 4 is a low-pass filter 3.
Is a delay circuit that delays the output signal of (1) by a half cycle of the clock pulse. An adder circuit 5 adds the output signal of the low-pass filter 3 and the delayed output signal passed through the delay circuit 4 and outputs the result to the sample hold circuit 6.

Next, the operation of the noise reducing apparatus thus constructed will be described with reference to the signal waveform diagram shown in FIG. The solid-state image sensor 1 has two clock pulses HCK1.
(A), driven by the horizontal scanning clock pulse or the like synthesized by HCK2 (b), the solid-state imaging device 1 superimposes the video signal (c) and the clock noise (d) based on the two synthesized clock pulses. Signal [(c)
+ (D)] is output. This signal [(c) + (d)]
Is subjected to current-voltage conversion in the preamplifier 2 and input to the low pass filter 3. This low pass filter 3
In the above, in the signal (f) = [which is obtained by reducing the noise equal to or higher than the second harmonic of the clock noise (d) and superposed the fundamental wave clock noise (e) having a frequency twice the clock pulse on the video signal (c). (C) + (e)] is output. That is, for example, when the clock noise frequency is 56 MHz,
Use a low-pass filter that can sufficiently reduce signals with a frequency of 2 MHz.

The output signal (f) passed through the low-pass filter 3 is input to the adder circuit 5 on the one hand and to the delay circuit 4 on the other hand. The delay time of the delay circuit 4 corresponds to a half cycle of the clock pulse, for example, the frequency of the clock pulse is 56 MHz.
In case of, it is 8.9 nsec. The delayed output signal (h) delayed in the delay circuit 4 is added to the signal (f) that has passed through the low-pass filter 3 in the adder circuit 5, and the added video signal (i) = [( f) +
(H)] is output. Video signal (i) after this addition
Is a video signal with the clock noise removed by canceling out the fundamental wave clock noise components in the signal (f) that has passed through the low-pass filter 3 and the delayed output signal (h).

The video signal (i) after this addition is
It is input to the sample-hold circuit 6 in the subsequent stage and sample-held by the sample-hold pulse (g). In addition, in the added video signal (i),
Since the pixel signals adjacent to each other are partially superposed as indicated by the circles, the sample and hold circuit 6 avoids this superposed portion to perform sampling.

[0013]

As described above on the basis of the embodiments,
According to the present invention, the video signal containing clock noise and the delayed video signal in which the half-cycle phase of the clock pulse is delayed are added, so that noise can be reduced without deteriorating the frequency characteristics of the video signal. Therefore, the sample hold operation can be performed normally.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a noise reduction device for explaining an embodiment of a noise reduction method for a solid-state image sensor according to the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the noise reduction device shown in FIG.

FIG. 3 is a block diagram showing a conventional signal processing circuit for noise reduction.

FIG. 4 is a signal waveform diagram for explaining the operation of the signal processing circuit shown in FIG.

[Explanation of symbols]

 1 Solid-state image sensor 2 Preamplifier 3 Low pass filter 4 Delay circuit 5 Adder circuit 6 Sample and hold circuit

Claims (1)

[Claims] 1. In a solid-state image sensor driven by using two clock pulses having different half-cycle phases, a video signal including clock noise output from the solid-state image sensor and a half cycle of the clock pulse for the video signal. A noise reduction method for a solid-state image pickup device, characterized in that clock noise is reduced by adding a delayed video signal having a delayed phase.