JPH05308663A - Transmission equipment for video signal - Google Patents

Abstract

(57) [Abstract] [Purpose] A high-definition video signal transmission device that is easy to manufacture and inexpensive, even if the number of effective pixels of the video signal greatly increases without requiring a circuit configuration that operates at high speed. To realize. [Configuration] This transmission device includes a plurality of encoding circuits (2, 3)
And a plurality of decoding circuits (7, 8), the transmitting side divides the input video signal into a plurality of areas, each area is encoded by a separate encoding circuit (2, 3), and then encoded. Data is multiplexed and transmitted. On the receiving side, the transmitted received data is separated into coded data for each area, and video signals for each area are decoded by separate coding circuits (7, 8) and combined into one video signal. ..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal transmission apparatus, and more particularly to a transmission apparatus having encoding and decoding functions.

[0002]

2. Description of the Related Art Conventionally, a video signal transmission device of this type is
One video signal is encoded by one encoding circuit and is decoded by one decoding circuit.

[0003]

In the conventional video signal transmission apparatus, one video signal is encoded by one encoding circuit and is decoded by one decoding circuit as described above. For example, in order to transmit a video signal having a very large number of pixels such as a high-definition video signal, it is necessary to construct a circuit that operates at a very high speed in an encoding circuit and a decoding circuit, and as a result, its production is extremely difficult. However, there are drawbacks that it is difficult and the manufacturing cost is very high.

It is an object of the present invention to provide a video signal transmission apparatus which does not become extremely difficult to manufacture even if the number of pixels of the video signal increases and the manufacturing cost is low.

[0005]

In order to achieve the above-mentioned object, the present invention provides a video signal dividing circuit for dividing a video signal into a plurality of areas and a plurality of video signal encoding circuits for dividing the divided video signals. The encoding circuit and the data multiplexing circuit that multiplexes the data encoded by each encoding circuit are provided on the transmission side, and the multiplexed encoded data is converted into encoded data for each divided area. A data separation circuit for separating, a plurality of decoding circuits for decoding the encoded data separated for each area, and a video signal for combining the decoded video signals of the plurality of areas into one video signal It is characterized in that it has a synthesizing circuit on the receiving side.

As one form of the present invention, at the time of encoding by the plurality of encoding circuits, time information such as a time record is recorded in encoded data, and the video signal synthesizing circuit stores the time information. It is characterized in that a plurality of areas are synchronized on the basis.

As another aspect of the present invention, in the data multiplexing circuit, the coded data output from each of the coding circuits is divided into blocks having a constant data length, and the data block units are arranged in the order of the coding circuits. It is characterized in that the data is alternately combined and converted into a series of data strings.

As still another aspect of the present invention, in the data multiplexing circuit, the coded data output from each of the coding circuits is divided into blocks having an arbitrary data length,
It is characterized in that the data length of the block is added to each data block as header information, and the data is alternately combined in the order of the encoding circuit in units of the data block to be converted into a series of data strings.

[0009]

According to the present invention, the video signal separation circuit on the transmission side functions to divide one input video signal into video signals of a plurality of areas having an appropriate size, and the plurality of coding circuits divide each of the divided video signals. The data multiplexing circuit functions to encode the video signal of the area, the data multiplexing circuit functions to multiplex the data coded by the respective coding circuits, and the data separation circuit on the receiving side functions to convert the multiplexed data to the area. Each of the plurality of decoding circuits functions to decode the coded data separated for each area, and the video signal synthesizing circuit functions to separate the coded data of each area. , And convert them into one video signal. This makes it possible to cope with an increase in the number of pixels of the video signal by increasing the number of encoding circuits and decoding circuits. Therefore, since it is necessary to speed up the circuit operation of the encoding circuit and the decoding circuit in order to cope with the increase in the number of pixels of the video signal, its production becomes difficult as the number of pixels increases, and the production cost becomes expensive. It is possible to solve the conventional problem of becoming.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 to 7 show an embodiment of the present invention. FIG. 1 shows a configuration example of a video signal transmission device according to an embodiment of the present invention.

The division circuit 1 on the transmission side divides the input video signal into two areas, and sends each of the divided video signals to the encoding circuit (1) 2 and the encoding circuit (2) 3. The encoding circuit (1) 2 and the encoding circuit (2) 3 independently encode the video signals sent from the division circuit 1 and send them to the multiplexing circuit 4. In the multiplexing circuit 4, 2 encoded by the encoding circuit (1) 2 and the encoding circuit (2) 3
Transmission line 5 by multiplexing one encoded data into one data
Output to.

The separation circuit 6 on the receiving side separates the multiplexed data sent from the transmission line 5 into two encoded data,
Decoding circuit (1) 7 and decoding circuit (2)
Send to 8. Decoding circuit (1) 7 and decoding circuit (2)
Decoding is independently performed at 8 and the decoded video signal is sent to the synthesizing circuit 9. The synthesizing circuit 9 synthesizes the two video signals sent from the decoding circuits 7 and 8 into a single video signal and outputs it.

First, the transmitting side will be described in detail. FIG. 2 shows an example in which a video signal is decomposed into two areas. Here, the division circuit 1 divides each of the frames 11 to 13 into two upper and lower areas 11A to 13A and 11B to 13B.

The video signals divided into the two areas are data-compressed by the encoding circuits 2 and 3. As an encoding method,
In the case of a moving image, inter-frame prediction and DC as shown in FIG.
A method combining T (discrete cosine transform) processing and variable length coding is generally used.

Next, the moving picture coding system (DCT) shown in FIG.
The coding procedure of the interframe predictive coding method) will be described.

First, in the frame memory 28, a decoded image one frame before is recorded.

Next, the difference unit 21 obtains an interframe difference signal between the current frame and the previous frame.

Next, in the DCT processing 22, this differential signal is subjected to DCT processing in block units (usually 8 × 8 pixels).

Further, in the quantization processing 23, the DCT coefficient (data after DCT) is quantized.

Subsequently, the quantized coefficient is subjected to variable length coding (entropy coding) in the variable length coding processing 24, and the coded data is output.

At the same time, the quantization coefficient is inversely quantized 25
Dequantize with to return to DCT coefficient.

Next, inverse DCT processing 26 performs inverse DCT processing on this DCT coefficient to return it to an interframe difference signal.

Next, the adder 27 adds the inter-frame difference signal to the decoded image of the previous frame to obtain the decoded image of the current frame.

The decoded image of this current frame is recorded in the frame memory 28.

Since variable length coding is used as the coding method as described above, the data length of each compressed frame becomes different for each frame as shown in FIG. In FIG. 4, the encoded data (1) is the output of the encoding circuit (1) 2 and the encoded data (2) is the output data of the encoding circuit (2) 3.

In FIG. 4, f1-1 is the first frame.
Area 1, f2-1 is the second frame / area 1, ... Also, f
Reference numeral 2-1 indicates the first frame / area 2, and f2-2 indicates the encoded data of the second frame / area 2 ,. The broken line in the figure represents the data delimiter position when the encoded data is divided into fixed lengths as shown in FIG.

Next, the video signals encoded by the two encoding circuits 2 and 3 are multiplexed by the multiplexing circuit 4 for serial transmission through one transmission path. 5 and 6 show an example of the multiplexing format.

The example shown in FIG. 5 is the encoded data (1) shown in FIG.
The coded data (2) is divided into blocks having a constant data length, and the blocks are alternately combined while adding the synchronization code SC and the area number AN to the beginning of each block. The synchronization code SC is a code for detecting a break in the data, and the area number AN indicates which coding circuit is used for coding or which decoding circuit is used for decoding.

That is, SC is a synchronization code (Sync
A unique code (a code that never appears as coded data of a video signal) is recorded so that the beginning of a data area (area where coded data is recorded) can be reliably detected. There is. Further, AN is an area number (Area Number) and indicates which area of the area where the frame is decomposed is the encoded data. For example, in the case of encoded data in area 1, AN = 1
Is recorded, and AN = 2 in the case of encoded data in area 2.
Is recorded. Encoded data is recorded in the data area following the AN, but in this case, it is recorded as fixed length data. As shown in FIG. 4, since the original encoded data is variable length data, only one part of the encoded data of one frame is recorded in one data area, or the encoded data of a plurality of frames is encoded. Data may be recorded.

In the example shown in FIG. 6, the encoded data is divided into blocks of arbitrary length, and the sync code S is added to the beginning of each block.
C, the area number AN, and the data length DL are added alternately and combined. The data length DL indicates how long the block is. In the case of this figure, the encoded data for one frame is multiplexed as one block.

That is, SC and AN are the same as those described with reference to FIG. DL is the data length (Data Length
h), the length of the data area that immediately follows (number of bytes)
Is shown. In the case of FIG. 6, 1 is set in one data area.
Encoded data of one area for a frame is recorded.

As described above, the coded data coded by the plurality of coding circuits 2 and 3 are multiplexed into a series of data strings by the multiplexing circuit 4 and sent to the transmission line 5.

Next, the receiving side will be described. Transmission line 5
A series of data strings sent from the above are separated into blocks by the separating circuit 6 and sent to the corresponding decoding circuits 7 and 8. In the case of the multiplexing format of FIG. 5, the synchronization code S
While detecting C, a block is cut out into a predetermined data length, and the data is distributed to the decoding circuits 7 and 8 corresponding to the area number AN. On the other hand, in the case of the multiplexing format of FIG. 6, the synchronization code SC is detected, the data of the length indicated by the data length DL is cut out, and the data is distributed to the decoding circuits 7 and 8 corresponding to the area number AN. To go.

The decoding circuit 7.8 performs decoding by the processing method shown in the block diagram of FIG. 7, and sends the decoded video signal to the synthesizing circuit 9. The synthesizing circuit 9 synthesizes the video signals sent from the two decoding circuits 7 and 8 to form one video signal and outputs it to a display device (not shown).

Next, the decoding procedure of the decoding method shown in FIG. 7 will be described.

First, in the frame memory 35, a decoded image one frame before is recorded.

Next, the decoded data is input to the variable length decoding process 31, variable length decoding is performed, and the quantized coefficient is returned.

In the inverse quantization process 32, the quantized coefficient is inversely quantized to be a DCT coefficient.

The inverse DCT processing 33 converts the DCT coefficient to inverse DC.
T to return to the inter-frame difference signal.

The adder 34 adds the interframe difference signal to the decoded image of the previous frame to obtain the decoded image of the current frame.

The current frame decoded image is recorded in the frame memory 35.

At the same time, the decoded image is output as a video signal.

It should be noted that the above-mentioned encoding procedure relating to FIG. 3 and the above-mentioned decoding procedure relating to FIG. 7 are exactly the same operation. This part of the encoder is called the local decoding circuit. The reason for having the decoding circuit in the encoder is to prevent a mismatch between the encoder and the decoder. That is, if the decoded image recorded in the frame memory has an error between the encoder and the decoder,
This error is accumulated as the frame progresses, leading to deterioration of the image quality of the decoded image.

[0045]

As described above, according to the present invention,
On the transmitting side, the video signal is divided into a plurality of areas, the divided video signals of the respective areas are encoded by a plurality of encoding circuits, and the data encoded by the respective encoding circuits are multiplexed and transmitted. On the receiving side, the received multiplexed coded data is divided into divided coded data for each area, and the coded data divided for each area is decoded by a plurality of decoding circuits. Since the video signals of the plurality of decoded and decoded regions are combined and converted into one video signal, even when the number of pixels of the video signal increases as in high-definition video, the encoding circuit Also, since it is possible to deal with the problem by increasing the number of decoding circuits without increasing the processing speed of the decoding circuits, it is possible to obtain an effect that the manufacturing is easy and the manufacturing cost is low.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall circuit configuration of a video signal transmission device according to an embodiment of the present invention.

2 is a diagram showing an example of a case where a video signal is decomposed into two regions in the division circuit of FIG.

3 is a block diagram showing a configuration of an encoding circuit in FIG.

4 is a diagram showing an example of encoded data generated by the encoding circuit of FIG.

5 is a diagram showing an example of a multiplexing format in the multiplexing circuit of FIG.

FIG. 6 is a diagram showing another example of the multiplexing format.

7 is a block diagram showing a configuration of a decoding circuit of FIG.

[Explanation of symbols]

 1 division circuit 2,3 encoding circuit 4 multiplexing circuit 5 transmission line 6 separation circuit 7,8 decoding circuit 9 synthesis circuit 21 subtractor 22 DCT processing 23 quantization processing 24 variable length encoding processing 25,32 dequantization Processing 26,33 Inverse DCT processing 27,34 Adder 28,35 Frame memory 31 Variable length decoding processing SC Sync code AN Area number DL Data length

Claims (4)

[Claims] 1. A video signal division circuit for dividing a video signal into a plurality of areas, a plurality of encoding circuits for encoding the divided video signals of the respective areas, and data encoded by the respective encoding circuits. A data demultiplexing circuit for demultiplexing the coded data for each region into a coded data for each region, and a data demultiplexing circuit for demultiplexing the coded data A video signal transmission device having a plurality of decoding circuits for decoding and a video signal synthesizing circuit for synthesizing video signals of a plurality of decoded regions and converting the video signals into one video signal on the receiving side. .. 2. When encoding is performed by the plurality of encoding circuits, time information such as a time record is recorded in encoded data, and the video signal synthesizing circuit stores a plurality of areas based on the time information. 2. The video signal transmission device according to claim 1, wherein 3. The data multiplexing circuit divides the coded data output from each of the coding circuits into blocks having a constant data length, and alternately combines the data in the order of the coding circuits in data block units. The video signal transmitting apparatus according to claim 1, wherein the video signal transmitting apparatus converts the video signal into a series of data strings. 4. The data multiplexing circuit divides the encoded data output from each of the encoding circuits into blocks having an arbitrary data length, and adds the data length of the block to each data block as header information. 2. The video signal transmission device according to claim 1, wherein the data are alternately combined in the order of the encoding circuit in units of the data blocks and converted into a series of data strings.