JPH0531264U - Liquid crystal matrix panel manufacturing method - Google Patents

Abstract

(57) [Summary] [Object] To reduce pinholes by stacking an insulating oxide film formed by anodic oxidation and an insulating layer formed by plasma CVD on a gate line and a gate electrode in a liquid crystal matrix panel. To aim. [Structure] An insulating oxide film formed by anodic oxidation and an insulating layer formed by plasma CVD are stacked on a gate line and a gate electrode.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a liquid crystal matrix panel using a field effect transistor (FET). Recently, a large number of gate lines (scanning lines) and drain lines (signal lines) are orthogonally insulated from each other on one substrate of a liquid crystal panel, and thin film FETs (TFTs) are arranged at the intersections of these lines as switching elements. An attempt has been made to develop a liquid crystal matrix panel that displays an image on a television or the like by opening and closing this and applying a signal to the display electrode provided at each intersection to drive the liquid crystal in this portion. The present invention relates to a liquid crystal matrix panel using a switching element for such a display panel, for example.

[0002]

[Prior Art]

 Figure 3 shows the overall structure of a matrix panel that uses FETs as switching elements.

As shown in the figure, 1 is a front glass transparent substrate, 2 is a common electrode made of an ITO film which covers the entire inner surface of the transparent substrate 1, 3 is a liquid crystal layer, 4 is a glass frit, resin or the like. The spacer also works as a sealant. Reference numeral 5 denotes a rear glass transparent substrate, on the inner surface of which a plurality of gate lines (X) and drain lines (Y) (may be source lines. The same applies hereinafter) are insulated from each other and arranged orthogonally. Reference numeral 6 is a display electrode connected to each intersection of the gate line (X) and the drain line (Y) via amorphous silicon FET.

Hereinafter, a conventional method for manufacturing a liquid crystal matrix panel will be described.

FIG. 4 shows a plan view of one FET, FIG. 5 shows a cross-sectional view of the manufacturing process around the TFT section along the line AA ′ in FIG. 4, and FIG. Shows a cross-sectional view of the gate line along the line.

FIG. 5 and FIG. 6 show a specific structure of one FET, and (X) and (Y) are the above-mentioned gate line and drain line, which are separated by the insulating layer 7. The gate line (X) and the drain line (Y) are formed on the surface of the glass substrate 5. The gate (G) of the FET is formed on the gate line (X). An amorphous silicon layer (AS) is formed above the gate (G) through an insulating layer 7, and a source (S) and a drain (D) are formed at both ends of the amorphous silicon layer (AS) so as to sandwich the gate (G). The drain (D) is also used as a part of the drain line (Y). The display electrode 6 is connected to the source (S). Usually, the gate line (X) and the display electrode 6 are made of an ITO film, and the source (S) and the drain line (Y) are made of aluminum. Further, as the insulating film 7, a vapor deposition film of silicon nitride Si ₃ N ₄ formed by the plasma CVD method is used.

In the FET having such a structure, as shown in FIG. 6C, there is a portion where the gate line (X 1) and the drain line (Y) intersect with each other through the insulating film 7. The number of intersections is the same as the number of pixels. For example, if the number of gate lines (X) and the number of drain lines (Y) are 220 and 240, respectively, the number is 52,800. Therefore, some of these intersections are short-circuited via the pinhole formed in the insulating layer 7. Even if there is only one short, this short will result in two defective lines, one gate line and one drain line, which will cause a large defect in the display.

[0008]

[Problems to be solved by the device]

 The present invention prevents short circuits due to pinholes generated at the intersections of gate lines and drain lines, and also prevents short circuits of the FETs themselves, thereby improving the reliability of these device structures, and thus displaying liquid crystal matrix panels. The purpose is to prevent defects.

[0009]

A method for manufacturing a liquid crystal matrix panel according to the present invention includes a display electrode substrate in which a large number of display electrodes are arranged in a matrix with transistors for supplying potentials to the insulating substrate and the display electrode substrate. A method of manufacturing a liquid crystal matrix panel, comprising: filling a liquid crystal between common electrodes facing each other, wherein a gate line made of aluminum and a gate electrode connected to the gate line are formed on the insulating substrate, and the gate line and the gate electrode are formed. Is anodized to form a surface insulating film on its entire surface, then the entire surface of the substrate including the surface insulating film is covered with an insulating layer formed by laminating silicon nitride, and further on the insulating film, A drain line intersecting with the gate line through the semiconductor layer, the source electrode, the surface insulating film, and the insulating film, and the drain line is connected to the drain line. Drain electrodes, and forms a display electrode connected to the source electrode.

[0010]

[Action]

 According to the method of manufacturing a liquid crystal matrix panel of the present invention, even if pinholes are formed in the insulating oxide film and the insulating layer, the probability that the positions of these pinholes coincide will be extremely low, and in practice It can be zero. Also, because an insulating oxide film is formed by anodic oxidation, even if foreign matter such as dust adheres to the surface of the gate line and gate electrode, it wraps around and forms a surface insulating film, which reduces the occurrence of pinholes due to foreign matter. .

[0011]

【Example】

1 and 2 are cross-sectional views of an embodiment of the present invention corresponding to FIGS. 5 and 6, and the same parts as those in FIGS. 5 and 6 are denoted by the same reference numerals. 8 is an insulating oxide film formed on the surface of the gate (G) and the gate line (X). When the gate line (X) and the gate (G) are formed of aluminum, the oxide is alumina. It is Al ₂ O ₃ . The insulating oxide film 8 is formed by anodizing the gate line (X) made of aluminum (FIGS. 1B and 2B). After the gate line (X) and the gate (G) are oxidized, an insulating layer 7 is formed by vapor deposition of silicon nitride so as to cover the surface, and a drain line (Y) is formed on the insulating layer 7. Be worn. In this way, the insulating oxide film 8 and the insulating layer 7 are separately formed by oxidation and plasma C VD, respectively. Therefore, the gate insulating layer on the gate electrode (G) of the FET is composed of a laminated body of the insulating oxide film 8 made of alumina, which is the surface insulating film of the gate electrode (G), and the insulating layer 7 such as silicon nitride. (Fig. 1 (d)). Further, even at the intersection of the gate line (X) and the drain line (Y), the interlayer insulating film is composed of a laminated body of the insulating oxide film 8 and the insulating layer 7 similar to the gate insulating layer of the FET. (FIG. 2 (d)). Therefore, even if a pinhole is generated in the insulating layer 7 existing at the intersection of the gate line (X) and the drain line (Y), the probability that the pinhole will be generated in the insulating oxide film 8 at this position. Is very low and can be practically zero. At the FET position, of course, as is apparent from FIG. 2D, between the gate electrode (G) and the amorphous silicon layer which is the semiconductor layer and the drain electrode (D) or the source electrode (S), Since the laminated body of the insulating oxide film 8 and the insulating layer 7 is interposed, the probability of short circuit between electrodes due to pinholes can be drastically reduced, as in the case of the above line intersection.

[0012]

[Effect of the device]

 As described above, according to the method of manufacturing a liquid crystal matrix panel of the present invention, it is possible to eliminate the short-circuit accident due to the pinhole between the transistor and the electrode at the line crossing position. Is eliminated.

Further, since the insulating oxide film is formed on the entire surface of the gate line and the gate electrode by anodic oxidation, even if foreign matter such as dust adheres to the surface of the gate line and the gate electrode, the insulating oxide film is sneak up to the insulating oxide film. As a result, the formation of pinholes due to foreign matter can be prevented.

Particularly in a liquid crystal matrix panel having transistors and the number of intersections on the order of one million, the effect of improving the yield is great.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a TFT section of a liquid crystal matrix panel of the present invention.

FIG. 2 is a sectional view of a manufacturing process along a gate line of a liquid crystal matrix panel of the present invention.

FIG. 3 is a structural diagram of a liquid crystal matrix panel.

FIG. 4 is a plan view around a pixel of a liquid crystal matrix panel.

FIG. 5 is a sectional view of a manufacturing process of a TFT portion of a conventional liquid crystal matrix panel.

FIG. 6 is a cross-sectional view of a manufacturing process along a gate line of a conventional liquid crystal matrix panel.

[Explanation of symbols]

 1 front transparent substrate 2 common electrode 3 liquid crystal layer 4 spacer 5 rear transparent substrate 6 display electrode 7 insulating layer 8 insulating oxide film X gate line Y drain line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // G09F 9/35 7926-5G H01L 21/3205

Claims (1)

[Scope of utility model registration request] 1. A liquid crystal matrix in which a plurality of display electrodes are arranged in a matrix with a plurality of display electrodes on an insulating substrate together with transistors for supplying a potential to the display electrodes, and a liquid crystal is filled between a common electrode facing the substrate. In the panel manufacturing method, a gate line made of aluminum and a gate electrode connected to the gate line are formed on the insulating substrate, and the gate line and the gate electrode are anodized to form a surface insulating film on the entire surface thereof. After that, the entire surface of the substrate including the surface insulating film is covered with an insulating layer formed by stacking silicon nitride, and a semiconductor layer, a source electrode, the surface insulating film, and the insulating film are further provided on the insulating film. A drain line intersecting with the gate line, a drain electrode connected to the drain line, and a display electrode connected to the source electrode are formed. Method of manufacturing a liquid crystal matrix panel characterized and.