JPH05313916A - Interrupt processing method in electronic computer and electronic computer - Google Patents

Abstract

(57) [Summary] [Purpose] Even if interrupt requests of any interrupt level occur continuously, after checking for the existence of an interrupt request,
Immediately, the interrupt processing program corresponding to the subsequent interrupt request can be executed. When an interrupt processing program is executed based on an interrupt request, only the interrupt level information of the contents of the CPU register saved in the RAM is restored after the execution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method (hereinafter simply referred to as an interrupt processing method) in an electronic computer and an electronic computer.

[0002]

2. Description of the Related Art Conventionally, as an electronic computer, for example, a microcomputer, a computer whose main part is shown in FIG. 4 is known.

In the figure, 1 is a chip body, 2 is a CPU for executing instructions, 3 is a RAM used for storing data, 4
Is a ROM for storing programs (main processing program, interrupt processing program), 5 is a bus, 6 is an interrupt processing unit, and 7 and 8 are resources.

Further, in the CPU 2, 9 is a register group, particularly 10 is a register collecting control flags for controlling the operation of the CPU 2, so-called processor status (PS), and 11 is an address of an instruction in a program. The register shown, the so-called program counter (P
C) and 12 are registers indicating an area called a stack in the RAM 3, so-called stack pointer (SP).

Conventionally, in such a microcomputer, interrupt processing has been performed, for example, as shown in FIG. That is, when an interrupt request is issued via the interrupt processing unit 6, the execution of the main processing program is interrupted and the CP
The contents of the U2 register group 9 are saved in the RAM 3.

Next, the interrupt processing program corresponding to the interrupt request is executed, and when the interrupt processing program is completed, the contents of the register group 9 of the CPU 2 saved in the RAM 3 are restored to the register group 9 by the interrupt restoration instruction.

Next, the presence or absence of an interrupt request is checked,
If there is an interrupt request, the contents of the register group 9 of the CPU 2 are saved in the RAM 3 again, then the corresponding interrupt processing program is executed, and if there is no interrupt request, the interrupted main processing program is restored, This is done.

In this interrupt processing method, each time the interrupt processing program corresponding to the interrupt request is completed,
Since the contents of the register group 9 of the CPU 2 saved in the RAM 3 are restored, if the interrupt requests occur successively, the contents of the register group 9 must be saved in the RAM 3 again. There was a problem that the start of the interrupt processing program was delayed.

Therefore, conventionally, an interrupt processing method as shown in FIG. 6 has been proposed. In this way,
When an interrupt request is issued via the interrupt processing unit 6, the execution of the main processing program is interrupted and the contents of the register group 9 of the CPU 2 are saved in the RAM 3.

Next, the interrupt processing program corresponding to the interrupt request is executed, and when it finishes, the presence or absence of the interrupt request is checked. If there is an interrupt request, the corresponding interrupt processing program is continuously executed. If there is no interrupt request, the contents of the register group 9 of the CPU 2 saved in the RAM 3 are restored, the interrupted main processing program is restored, and this is executed.

According to this interrupt processing method, the RAM is processed after the interrupt processing program corresponding to the interrupt request is completed.
The contents of the register group 9 saved in 3 are not restored,
The presence or absence of an interrupt request is checked, and if there is an interrupt request, the corresponding interrupt processing program is continuously executed as it is, so that the subsequent interrupt processing can be performed immediately without delay.

[0012]

However, since the interrupt level is written as the processing mode in the processor status 10 of the CPU 2, the interrupt processing method shown in FIG. 6 has a high priority, that is, a high interrupt level. When an interrupt request with a low interrupt level is generated consecutively to the interrupt request, there is a problem that the interrupt request with a low interrupt level cannot be accepted as it is.

In view of the above point, the present invention makes it possible to continuously generate interrupt requests of any interrupt level.
An object of the present invention is to provide an interrupt processing method and an electronic computer capable of executing an interrupt processing program corresponding to consecutive interrupt requests immediately after checking the presence or absence of an interrupt request.

[0014]

A first example of an interrupt processing method according to the present invention is such that, when a corresponding interrupt processing program is executed on the basis of an interrupt request, the register of the instruction execution unit saved after the execution of the interrupt processing program. Of the contents of, only the interrupt level information is restored.

The first example of the electronic computer according to the present invention is for carrying out the first example of the interrupt processing method according to the present invention. After the interrupt processing is completed, the contents of the register of the instruction execution unit saved are saved. Of these, a means for returning only the interrupt level information is provided.

A second example of the interrupt processing method according to the present invention is as follows:
When the corresponding interrupt processing program is executed based on an interrupt request and the interrupt processing is continuously performed after the execution, when the saved contents of the register of the instruction execution unit is used in the subsequent interrupt processing Is to restore the saved contents of the register of the instruction execution unit after the execution of the interrupt processing program.

A second example of the electronic computer according to the present invention is for carrying out the second example of the interrupt processing method according to the present invention. When interrupt processing is continuously performed after completion of interrupt processing, save it. When the content of the register of the instruction execution unit is used in the subsequent interrupt processing, a means is provided for restoring the saved content of the register of the instruction execution unit after the execution of the interrupt processing program is completed. To be done.

[0018]

In the first example of the interrupt processing method according to the present invention, after the completion of the execution of the interrupt processing program, all the contents of the saved registers of the instruction execution unit are not restored. Since the level information is restored, even if an interrupt request with a low interrupt level occurs successively with an interrupt request with a high interrupt level, the interrupt request with a low interrupt level can be accepted.

Further, in the interrupt processing method of the first example, when the corresponding interrupt processing program is executed on the basis of the interrupt request as described above, after the completion of the interrupt processing program, the register of the instruction execution unit saved is saved. Since all the contents are not restored, it is not necessary to save all the contents of the register of the instruction execution unit again when there are consecutive interrupt requests.

That is, according to the interrupt processing method of the first example, no matter what interrupt level interrupt request occurs continuously, immediately after the presence or absence of the interrupt request is checked, continuous interrupt requests are dealt with. It is possible to execute the interrupt processing program.

The second aspect of the interrupt processing method according to the present invention
In the example, when the corresponding interrupt processing program is executed based on the interrupt request,
If you want to use the saved register contents of the instruction execution unit for subsequent interrupt processing when performing interrupt processing consecutively, after executing the previous interrupt processing program, save the saved instruction execution unit Since the contents of the register are supposed to be restored, the interrupt level information will also be restored, and as a result, even if an interrupt request with a low interrupt level occurs consecutively with an interrupt request with a high interrupt level,
This interrupt request with a low interrupt level can be accepted.

Further, in the interrupt processing method of the second example, when the corresponding interrupt processing program is executed on the basis of the interrupt request as described above, and when the interrupt processing is continuously performed after the completion, When the contents of the saved instruction execution unit registers are used in subsequent interrupt processing, the saved contents of the instruction execution unit registers will be restored after the execution of the previous interrupt processing program. , When there are consecutive interrupt requests, especially when using the contents of the saved registers in the subsequent interrupt processing, immediately check for the interrupt request and immediately respond to the subsequent interrupt request. It is possible to execute the interrupt processing program.

That is, according to the interrupt processing method of the first example, in the case of processing consecutive interrupt requests, especially when the contents of the saved register are used in the subsequent interrupt processing, No matter what interrupt level the interrupt request is, the interrupt processing program corresponding to the subsequent interrupt request can be executed immediately after checking the presence or absence of the interrupt request.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
Examples to third examples will be described.

First Embodiment FIG. 1 is a flow chart showing a first embodiment of the present invention. FIG. 4 shows an essential part of the first embodiment of the interrupt processing method according to the present invention in FIG. An example is shown in which a microcomputer configured as described above performs an interrupt process.

In the first embodiment, when an interrupt request is issued via the interrupt processing unit 6, the execution of the main processing program is interrupted and the contents of the register group 9 of the CPU 2 are saved in the RAM 3.

Next, the interrupt processing program corresponding to the interrupt request is executed, and when it is completed, only the interrupt level information of the contents of the register group 9 of the CPU 2 saved in the RAM 3 is restored by the interrupt restoration instruction. It

Next, the presence or absence of an interrupt request is checked,
When there is an interrupt request, the corresponding interrupt processing program is executed, and when there is no interrupt request, the contents of the register group 9 of the CPU 2 saved in the RAM 3 other than the interrupt level information are restored, and the stack After the pointer 12 is updated, the interrupted main processing program is returned to and executed.

In the first embodiment, when the corresponding interrupt processing program is executed based on the interrupt request, all contents of the register group 9 of the CPU 2 saved in the RAM 3 are saved after the execution. However, since the interrupt level information is restored, even if an interrupt request with a low interrupt level occurs consecutively with an interrupt request with a high interrupt level, this interrupt request with a low interrupt level is accepted. You can

Further, in the first embodiment, when the corresponding interrupt processing program is executed on the basis of the interrupt request, the CP saved in the RAM 3 after the execution is completed.
Since all the contents of the U2 register group 9 are not restored but only the interrupt level information is restored, the contents of the register group 9 of the CPU 2 are saved again when there are consecutive interrupt requests. No steps required.

That is, according to the first embodiment, when processing consecutive interrupt requests, the register group 9 of the CPU 2 saved in the RAM 3 in the subsequent interrupt processing.
When the contents of the above are not used, no matter what the interrupt level of the subsequent interrupt request is, the interrupt processing program corresponding to the subsequent interrupt request is executed immediately after checking the existence of the interrupt request. be able to.

Second Embodiment FIG. 2 is a flow chart showing a second embodiment of the present invention. FIG. 4 shows an essential part of a second embodiment of the interrupt processing method according to the present invention in FIG. An example is shown in which a microcomputer configured as described above performs an interrupt process.

In the second embodiment, when an interrupt request is issued via the interrupt processing unit 6, the execution of the main processing program is interrupted and the contents of the register group 9 of the CPU 2 are saved in the RAM 3.

Next, the interrupt processing program corresponding to the interrupt request is executed, and when it is completed, the contents of the register group 9 of the CPU 2 saved in the RAM 3 are restored to the register group 9 by the interrupt restoration instruction. However, in this case, the contents of the stack pointer 12 are not restored.

Next, it is checked whether or not there is an interrupt request,
If there is an interrupt request, the interrupt processing program is executed. If there is no interrupt request, stack pointer 1
2 is updated, the interrupted main processing program is restored, and this is executed.

In the second embodiment, when the corresponding interrupt processing program is executed on the basis of the interrupt request, the contents of the register group 9 of the CPU 2 saved in the RAM 3 are restored after the execution. Because
The interrupt level information will also be restored, and as a result,
Even if an interrupt request with a low interrupt level occurs successively with an interrupt request with a high interrupt level, the interrupt request with a low interrupt level can be accepted.

Further, in the second embodiment, when the corresponding interrupt processing program is executed on the basis of the interrupt request, the CP saved in the RAM 3 after the execution is completed.
Since the contents of the register group 9 of U2 are to be restored, when there are consecutive interrupt requests, when the contents of the register group 9 of the CPU2 saved in the RAM3 are used in the subsequent interrupt processing, After the presence or absence of an interrupt request is checked, the interrupt processing program corresponding to the subsequent interrupt request can be executed immediately.

That is, according to the second embodiment, in the case of processing consecutive interrupt requests, especially when the contents of the register group 9 of the CPU 2 saved in the RAM 3 are used in the subsequent interrupt processing. , No matter what interrupt level the subsequent interrupt request is,
Immediately after checking the presence or absence of an interrupt request, the interrupt processing program corresponding to the subsequent interrupt request can be executed.

Third Embodiment FIG. 3 FIG. 3 is a block diagram showing a third embodiment of the present invention. The interrupt handling method of the first embodiment, the interrupt handling method of the second embodiment and FIG. 5 are shown. 1 illustrates a main part of an example of a microcomputer configured to execute a conventional interrupt processing method.

In the third embodiment, the micro R of the CPU 2 is used.
In the OM 13, an instruction RET-IQ1 for instructing the interrupt processing method of the first embodiment, an instruction RET-IQ2 for instructing the interrupt processing method of the second embodiment, and a conventional interrupt processing method RET-I shown in FIG. 5 are provided. By storing them, the interrupt processing method of the first embodiment, the interrupt processing method of the second embodiment, and the conventional interrupt processing method shown in FIG. 5 are executed.

Therefore, in this third embodiment, RO
At the end of the interrupt processing program stored in M4, an instruction RET-IQ for instructing the interrupt processing method of the first embodiment is provided.
1. An instruction RET instructing the interrupt processing method of the second embodiment
An instruction for instructing which of the instruction RET-I for instructing the IQ2 or the conventional interrupt processing method shown in FIG.

Reference numeral 14 is a bus control circuit, 15 is an instruction register, 16 is an address generating circuit, and 17 is an address generating circuit.
Is an instruction decoder, 18 is an arithmetic unit, and 19 is an internal bus of the CPU 2.

[0043]

According to the first example of the interrupt processing method according to the present invention (the interrupt processing method according to claim 1), when the corresponding interrupt processing program is executed based on the interrupt request, it is saved after the end. Only the interrupt level information is restored from the contents of the register of the instruction execution unit that is being executed, so even if interrupt requests of any interrupt level occur continuously, immediately after checking whether there is an interrupt request, , An interrupt processing program corresponding to continuous interrupt requests can be executed.

According to the first example of the electronic computer of the present invention (the electronic computer according to claim 2), the first example of the interrupt processing method of the present invention can be implemented.

According to the second example of the interrupt processing method according to the present invention (the interrupt processing method according to claim 3), when the corresponding interrupt processing program is executed based on the interrupt request, the interrupt processing program continues after the end. If the contents of the saved instruction execution unit registers are to be used for subsequent interrupt processing, the saved instruction execution unit registers after the previous interrupt processing program has finished executing. Since the contents are to be restored, when processing the consecutive interrupt requests, especially when the saved register contents are used in the subsequent interrupt processing, the subsequent interrupt request may Even if it is a level interrupt request, immediately after checking whether there is an interrupt request, execute the interrupt processing program corresponding to the subsequent interrupt request. It can be.

According to the second example of the electronic computer of the present invention (the electronic computer according to claim 4), the second example of the interrupt processing method of the present invention can be implemented.

[Brief description of drawings]

FIG. 1 is a flowchart showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a main part of a microcomputer.

FIG. 5 is a flowchart showing an example of a conventional interrupt processing method.

FIG. 6 is a flowchart showing another example of a conventional interrupt processing method.

[Explanation of symbols]

 1 chip body 2 CPU 3 RAM 4 ROM 5 bus 6 interrupt processing unit

Claims (4)

[Claims] 1. When a corresponding interrupt processing program is executed on the basis of an interrupt request, only the interrupt level information of the saved contents of the register of the instruction execution unit is restored after the execution. Interrupt handling method for electronic computer. 2. An electronic computer comprising means for restoring only the interrupt level information among the contents of the saved register of the instruction execution unit after the interrupt processing is completed. 3. When a corresponding interrupt processing program is executed on the basis of an interrupt request and the interrupt processing is continuously performed after the completion of the interrupt processing program, the saved contents of the register of the instruction executing unit are interrupted later. When used in processing, the interrupt processing method in an electronic computer is characterized in that after the execution of the interrupt processing program, the contents of the saved register of the instruction execution unit are restored. 4. When the interrupt processing is continuously performed after the interrupt processing is completed, when the saved contents of the register of the instruction execution unit is used in the subsequent interrupt processing, the execution of the interrupt processing program is completed. An electronic computer, further comprising means for restoring the saved contents of the register of the instruction execution unit.