JPH0531463U - Screen erase circuit - Google Patents

Screen erase circuit

Info

Publication number
JPH0531463U
JPH0531463U JP013356U JP1335691U JPH0531463U JP H0531463 U JPH0531463 U JP H0531463U JP 013356 U JP013356 U JP 013356U JP 1335691 U JP1335691 U JP 1335691U JP H0531463 U JPH0531463 U JP H0531463U
Authority
JP
Japan
Prior art keywords
voltage
horizontal
frequency
screen
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP013356U
Other languages
Japanese (ja)
Inventor
弘章 西村
雅樹 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP013356U priority Critical patent/JPH0531463U/en
Publication of JPH0531463U publication Critical patent/JPH0531463U/en
Pending legal-status Critical Current

Links

Landscapes

  • Details Of Television Scanning (AREA)

Abstract

(57)【要約】 【目的】マルチ周波数対応のディスプレイの任意の水平
または垂直同期周波数の切り換え時の画面の乱れを消去
する。 【構成】水平または垂直同期周波数に比例して変化する
直流電圧1を一方の入力とし、直流電圧1を抵抗4およ
びコンデンサ5からなる積分回路を経由させ、その積分
出力電圧を他方の入力としたコンパレータ6を設け、直
流電圧1の変化を一定期間のパルスとして、コンパレー
タ6の出力として取り出す。このパルスにより映像増幅
回路のブランキング回路、コントラストまたはブライト
を制御する。 【効果】任意の水平または垂直同期周波数の切り換え時
の画面の乱れを消去するので、受像管の蛍光膜の保護や
画面の乱れによる不快感を解消することができる。
(57) [Abstract] [Purpose] Eliminates screen disturbance when switching any horizontal or vertical sync frequency of a multi-frequency compatible display. [Structure] A DC voltage 1 that changes in proportion to a horizontal or vertical synchronizing frequency is used as one input, the DC voltage 1 is passed through an integrating circuit consisting of a resistor 4 and a capacitor 5, and the integrated output voltage is used as the other input. A comparator 6 is provided, and a change in the DC voltage 1 is taken out as a pulse for a fixed period and output as an output of the comparator 6. This pulse controls the blanking circuit, the contrast or the bright of the video amplifier circuit. [Effect] Since the disturbance of the screen at the time of switching the arbitrary horizontal or vertical synchronizing frequency is eliminated, it is possible to protect the fluorescent film of the picture tube and eliminate the discomfort caused by the disturbance of the screen.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、異なる水平または垂直同期周波数の信号を受信することができるマ ルチ走査形ディスプレイに係り、特に、水平または垂直同期周波数切り換え時の 画面の乱れを消去する回路に関する。 The present invention relates to a multi-scan display capable of receiving signals of different horizontal or vertical sync frequencies, and more particularly to a circuit for eliminating screen disturbance when switching horizontal or vertical sync frequencies.

【0002】[0002]

【従来の技術】[Prior Art]

従来の回路は、特開昭62−76971号公報に記載のように、水平同期周波 数の切り換え時に水平偏向を止め、映像信号をミュートすることにより縦一状の 輝線が出る現象を阻止するようにしたもので、受像管の蛍光膜を保護している。 As described in Japanese Patent Application Laid-Open No. 62-76971, a conventional circuit stops horizontal deflection at the time of switching the horizontal synchronizing frequency and mutes the video signal to prevent a phenomenon in which a vertical bright line appears. Protects the fluorescent film of the picture tube.

【0003】[0003]

【考案が解決しようとする課題】[Problems to be solved by the device]

上記従来技術は、垂直周波数切り換え時、および、任意の周波数の切り換え時 について考慮がなされていないという問題があった。 The above-mentioned conventional technique has a problem that no consideration is given to switching of the vertical frequency and switching of an arbitrary frequency.

【0004】 本発明の目的は、垂直周波数切り換え時、および、任意の周波数の切り換え時 にも、輝線等の画面の乱れを消去することにある。An object of the present invention is to eliminate screen disturbances such as bright lines during vertical frequency switching and during arbitrary frequency switching.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するために、本考案は水平または垂直同期周波数に比例して変 化する直流電圧(以下fv電圧という)を一方の入力とし、fv電圧を積分回路 に入力し、積分回路の出力電圧を他方の入力としたコンパレータを設け、このコ パレータから出力される信号で、映像増幅回路を制御し、水平または垂直同期周 波数の切り換え時の画面乱れを消去するようにした。 In order to achieve the above object, the present invention uses a DC voltage (hereinafter referred to as fv voltage) that changes in proportion to a horizontal or vertical synchronizing frequency as one input, inputs the fv voltage into an integrating circuit, and outputs the output of the integrating circuit. A comparator with a voltage as the other input was provided, and the image output circuit was controlled by the signal output from this comparator to eliminate screen disturbance when switching the horizontal or vertical sync frequency.

【0006】[0006]

【作用】[Action]

fv電圧をコンパレータの一方の入力端子に印加し、他方の入力端子には、積 分回路を経由したfv電圧を入力する。水平または垂直同期周波数の切り換え時 にfv電圧が変化し、直接、コンパレータに入力した電圧に比べ、積分回路を経 由した他方端子側の電圧は変化が遅いので、一定の期間をもったパルス状の信号 をコンパレータ出力に取り出すことができる。このパルス状の信号を映像増幅回 路のコントラスト、ブライトまたはブランキング等の回路に印加することによっ て画面の乱れを消去することができる。 The fv voltage is applied to one input terminal of the comparator, and the fv voltage that has passed through the product circuit is input to the other input terminal. The fv voltage changes when the horizontal or vertical sync frequency is switched, and the voltage on the other terminal side that has passed through the integrator circuit changes more slowly than the voltage input directly to the comparator. The signal of can be taken out at the comparator output. By applying this pulse-shaped signal to a circuit such as contrast, bright or blanking in the image amplification circuit, the disturbance on the screen can be eliminated.

【0007】[0007]

【実施例】【Example】

以下、本考案の一実施例を図1、図2および図3により説明する。 An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3.

【0008】 図1において、まず受信中の信号より水平または垂直同期周波数の高い信号に 切り換えた場合を説明する。端子1より入力された水平または垂直のfv電圧は 分圧抵抗2および3により分圧され、コンパレータとして使用するオペアンプ6 の非反転入力端子に印加される。オペアンプ6の反転入力端子には、抵抗4およ びコンデンサ5からなる積分回路を経由したfv電圧が印加される。従って、或 る水平または垂直同期周波数の信号を受信している時、非反転入力端子の電圧は 反転入力端子電圧より低いので、オペアンプ6の出力端子の電圧は、図2のAの 範囲のように、アース電位となる。ここで、受信している信号よりも水平または 垂直同期周波数の高い信号に切り換えた時、オペアンプ6の非反転入力端子に入 力しているfv電圧は高くなる。しかし、反転入力端子に印加しているfv電圧 は積分回路を経由しているので、非反転入力端子の印加電圧に比べて立上りが遅 くなる。従って、信号切り換え時に、図2のBの範囲のように、一時的にオペア ンプ6の非反転入力端子の電圧が反転入力端子の電圧より高くなるため、オペア ンプ6の出力端子の電圧はVccレベルとなる。その後、ある一定時間を経て、 図2のCの範囲のように、オペアンプ6の反転入力端子の印加電圧のほうが高く なるため、オペアンプ6の出力端子の電圧は元のアース電位となる。Referring to FIG. 1, first, a case will be described in which the signal is switched to a signal having a higher horizontal or vertical synchronizing frequency than the signal being received. The horizontal or vertical fv voltage input from the terminal 1 is divided by the voltage dividing resistors 2 and 3 and applied to the non-inverting input terminal of the operational amplifier 6 used as a comparator. The fv voltage is applied to the inverting input terminal of the operational amplifier 6 via an integrating circuit composed of the resistor 4 and the capacitor 5. Therefore, when receiving a signal of a certain horizontal or vertical sync frequency, the voltage at the non-inverting input terminal is lower than the voltage at the inverting input terminal, so the voltage at the output terminal of the operational amplifier 6 is in the range of A in FIG. Then, it becomes the earth potential. Here, when the signal is switched to a signal whose horizontal or vertical synchronizing frequency is higher than the received signal, the fv voltage input to the non-inverting input terminal of the operational amplifier 6 becomes high. However, since the fv voltage applied to the inverting input terminal passes through the integrator circuit, it rises later than the voltage applied to the non-inverting input terminal. Therefore, at the time of signal switching, the voltage at the non-inverting input terminal of the operational amplifier 6 temporarily becomes higher than the voltage at the inverting input terminal, as shown by the range B in FIG. 2, and the voltage at the output terminal of the operational amplifier 6 is Vcc. It becomes a level. Then, after a certain period of time, the voltage applied to the inverting input terminal of the operational amplifier 6 becomes higher, as in the range C of FIG. 2, so that the voltage of the output terminal of the operational amplifier 6 becomes the original ground potential.

【0009】 次に、受信中の信号よりも水平または垂直同期周波数が低い信号に切り換えた 場合を説明する。端子1より入力された水平または垂直のfv電圧は、抵抗11 を介してオペアンプ12の反転入力端子に印加される。オペアンプ12の非反転 入力端子には、抵抗8および9により分圧され、コンデンサ10からなる積分回 路を経由して印加される。従って、或る水平または垂直同期周波数の信号を受信 している時、オペアンプ12の非反転入力端子の電圧は、反転入力端子の電圧よ り低いので、オペアンプ12の出力端子の電圧は、図3のAの範囲のように、ア ース電位となる。ここで、受信している信号よりも水平または垂直同期周波数の 低い信号に切り換えた時、オペアンプ12の反転入力端子に印加しているfv電 圧は低くなる。しかし、非反転入力端子に印加しているfv電圧は積分回路を経 由しているので、反転入力端子の印加fv電圧に比べて立ち上りが遅くなる。従 って、信号切り換え時に図3のBの範囲のように、一時的にオペアンプ12の非 反転入力端子の電圧が反転入力端子の電圧より高くなるため、オペアンプ12の 出力端子の電圧はVccレベルとなる。Next, a case will be described in which the signal is switched to a signal whose horizontal or vertical synchronizing frequency is lower than that of the signal being received. The horizontal or vertical fv voltage input from the terminal 1 is applied to the inverting input terminal of the operational amplifier 12 via the resistor 11. The voltage is divided by the resistors 8 and 9 and applied to the non-inverting input terminal of the operational amplifier 12 via the integrating circuit including the capacitor 10. Therefore, when receiving a signal of a certain horizontal or vertical synchronizing frequency, the voltage at the non-inverting input terminal of the operational amplifier 12 is lower than the voltage at the inverting input terminal, so the voltage at the output terminal of the operational amplifier 12 is as shown in FIG. As in the range of A, it becomes the ground potential. Here, when the signal is switched to a signal whose horizontal or vertical synchronizing frequency is lower than the received signal, the fv voltage applied to the inverting input terminal of the operational amplifier 12 becomes low. However, since the fv voltage applied to the non-inverting input terminal goes through the integrating circuit, the rising edge becomes slower than the fv voltage applied to the inverting input terminal. Therefore, at the time of signal switching, the voltage at the non-inverting input terminal of the operational amplifier 12 temporarily becomes higher than the voltage at the inverting input terminal, as shown by the range B in FIG. 3, so the voltage at the output terminal of the operational amplifier 12 is at the Vcc level. Becomes

【0010】 オペアンプ6とオペアンプ12の出力は、それぞれ逆流防止ダイオード7およ び13を経由して加算される。加算された信号は、抵抗14および15により分 圧され、トランジスタ17のベースに印加される。抵抗16はトランジスタ17 の電流制限抵抗である。ここで、オペアンプ6または12からVccレベルの信 号が出力されると、トランジスタ17がオンし、逆流防止ダイオード18を経由 して、ビデオ信号19をアース電位にする。すなわち、水平または垂直同期周波 数が切り換わった時、一定時間の間、ビデオ信号がアース電位となり、水平また は垂直同期が引き込むまでの画像の乱れを消去することができる。The outputs of the operational amplifier 6 and the operational amplifier 12 are added via the backflow prevention diodes 7 and 13, respectively. The added signals are divided by resistors 14 and 15 and applied to the base of transistor 17. The resistor 16 is a current limiting resistor of the transistor 17. Here, when the Vcc level signal is output from the operational amplifier 6 or 12, the transistor 17 is turned on, and the video signal 19 is set to the ground potential via the backflow prevention diode 18. That is, when the horizontal or vertical synchronizing frequency is switched, the video signal becomes the ground potential for a certain period of time, and the image disturbance until the horizontal or vertical synchronizing is pulled in can be eliminated.

【0011】 上述の実施例は、オペアンプの出力を、直接、ビデオ信号に加算している方法 であるが、他にはCRTのG1端子、ブランキング、ブライトおよびコントラス ト等の映像回路で制御しても同様の結果を得ることができる。The above-described embodiment is a method in which the output of the operational amplifier is directly added to the video signal. Alternatively, it is controlled by a video circuit such as the G1 terminal of the CRT, blanking, bright and contrast. However, the same result can be obtained.

【0012】[0012]

【考案の効果】[Effect of the device]

本考案によれば、任意の水平または垂直同期周波数の切り換えで、画面の乱れ を消去することができるので、受像管の蛍光膜の保護や、切り換え時の画面の乱 れによる不快感を解消することができる。 According to the present invention, the disturbance of the screen can be eliminated by switching the horizontal or vertical sync frequency arbitrarily, so that the fluorescent film of the picture tube is protected and the discomfort caused by the disturbance of the screen at the time of switching is eliminated. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の一実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】本考案の実施例における回路の動作波形図。FIG. 2 is an operation waveform diagram of the circuit according to the embodiment of the present invention.

【図3】本考案の実施例における回路の動作波形図。FIG. 3 is an operation waveform diagram of a circuit according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1.fv電圧、 4.積分回路の抵抗、 5.積分回路のコンデンサ、 6.コンパレータ、 8.積分回路の抵抗、 10.積分回路のコンデンサ、 12.コンパレータ。 1. fv voltage, 4. 4. resistance of integrating circuit, 5. Capacitor of integrating circuit, Comparator, 8. The resistance of the integrating circuit, 10. Capacitor of integrating circuit, 12. comparator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】異なる水平または垂直同期周波数の信号を
受信することができるマルチ走査方式のディスプレイに
おいて、前記水平または垂直同期周波数に比例して変化
する直流電圧を一方の入力とし、前記水平または垂直同
期周波数に比例して変化する直流電圧を積分回路に入力
し前記積分回路の出力電圧を他方の入力としたコンパレ
ータを設け、前記コンパレータから出力される信号で、
映像増幅回路を制御することによって前記水平または垂
直同期周波数の切り換え時の画面の乱れを消去すること
を特徴とする画面消去回路。
1. A multi-scan display capable of receiving signals of different horizontal or vertical synchronizing frequencies, wherein one input is a DC voltage which changes in proportion to the horizontal or vertical synchronizing frequency, and the horizontal or vertical A direct current voltage that changes in proportion to the synchronization frequency is input to the integrating circuit, and a comparator that uses the output voltage of the integrating circuit as the other input is provided, and with the signal output from the comparator,
A screen erasing circuit for erasing a screen disturbance at the time of switching the horizontal or vertical synchronizing frequency by controlling an image amplification circuit.
JP013356U 1991-03-11 1991-03-11 Screen erase circuit Pending JPH0531463U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP013356U JPH0531463U (en) 1991-03-11 1991-03-11 Screen erase circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP013356U JPH0531463U (en) 1991-03-11 1991-03-11 Screen erase circuit

Publications (1)

Publication Number Publication Date
JPH0531463U true JPH0531463U (en) 1993-04-23

Family

ID=11830824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP013356U Pending JPH0531463U (en) 1991-03-11 1991-03-11 Screen erase circuit

Country Status (1)

Country Link
JP (1) JPH0531463U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219843A (en) * 1996-02-09 1997-08-19 Matsushita Electric Ind Co Ltd Television screen display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219843A (en) * 1996-02-09 1997-08-19 Matsushita Electric Ind Co Ltd Television screen display device

Similar Documents

Publication Publication Date Title
JPS6276886A (en) Video signal processing device with image display device
KR940003050B1 (en) Television receiver responsive to plural video signals
JPH0531463U (en) Screen erase circuit
JP2524036B2 (en) VTR software copy protection system
US4456927A (en) Video circuitry
US5510854A (en) Device for adjusting the black level of a video signal
JP2000196973A (en) Pulse correction device in display system
JPS5830282A (en) Video signal circuit
JPS628990B2 (en)
JPS5997287A (en) Signal sampling system
KR970007537B1 (en) Black level compensation circuit
JPH0342786Y2 (en)
JPH0339980Y2 (en)
JP3660062B2 (en) Analog blanking pulse generator
JP3385821B2 (en) Horizontal blanking generation circuit
JPS592425B2 (en) vertical deflection device
KR200162111Y1 (en) Synchronous separate circuit
JPH06245100A (en) Video signal processor
JP2000217044A (en) On-screen data luminance adjustment circuit
JPH04331978A (en) Clamp pulse circuit of video amplifier
JPH03236092A (en) On-screen display circuit
KR970057715A (en) Blanking part complementary color processing device for aspect ratio switching of television
JPH0127632B2 (en)
JPH04273773A (en) Direct current transmission quantity correcting device
JPH059086U (en) Image miute circuit