JPH04331978A - Clamp pulse circuit of video amplifier - Google Patents

Abstract

PURPOSE:To prevent a clamp pulse from exceeding a back porch to clamp a video display section when the synchronizing frequency of a horizontal synchronizing signal is high by controlling the width of the clamp pulse outputted to the video amplifier corresponding to the synchronizing frequency of the horizontal synchronizing signal. CONSTITUTION:The horizontal synchronizing signal when inputted to a horizontal synchronizing signal input terminal 22 is converted by an F/V converter 23 into a voltage signal, which is amplified by operational amplifiers 24 and 36 to the voltage Vb at a point B. This F/V converter operates so that an output voltage is higher and higher as the frequency of the input is higher and higher. Therefore, the Vb rises in this circuit as the frequency of the synchronizing signal inputted to a display device increases, and a larger current flows through resistors 32 and 34, so that the width of the clamp pulse becomes short.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a display device used in conjunction with a host computer and related equipment that supply horizontal synchronizing signals to a multi-scan display device. The present invention relates to a clamp pulse generation circuit for a video amplifier that varies the clamp pulse width of the video amplifier based on the synchronization frequency.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 2, a video signal input to a display device is capacitor coupled and then amplified by a video amplifier. Since the amplified video signal has lost its DC component, the DC component is regenerated by clamping the clamp pulse generated from the synchronization signal to the back porch, front porch, or the period of the synchronization signal as shown in FIG. 3(a). Generally, when the horizontal synchronization frequency is high, the back porch, front porch, and synchronization signal sections become shorter, but in conventional multi-scan display devices, the clamp pulse width was constant regardless of the horizontal synchronization frequency.

0003

[Problems to be Solved by the Invention] As described above, in the conventional technology, when the frequency of the horizontal synchronizing signal is high in a multi-scan type display device, the clamp pulse width exceeds the back porch portion and is clamped to the video section. However, there was a problem in that the correct image was not displayed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to obtain a clamp pulse having a pulse width corresponding to the synchronization frequency of an input horizontal synchronization signal, in order to solve the above-mentioned conventional problems.

[0005]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an F/V converter that inputs a horizontal synchronization signal and converts the synchronization frequency into a voltage signal, and provides a variable output according to the output voltage signal. The configuration includes a clamp pulse width variable circuit consisting of an operational amplifier and a clamp pulse generation circuit, and the clamp pulse width is varied according to the synchronization frequency of the horizontal synchronization signal output to the display device, and the clamp pulse is output to the video amplifier. The pulse width can now be optimized.

[0006]

[Operation] The variable clamp pulse width circuit configured as described above operates so that as the frequency of the horizontal synchronizing signal input to the display device increases, the clamp pulse width becomes shorter. This prevents the display from not displaying a normal screen by clamping the display section.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. In FIG. 1, an input terminal 22 to which a horizontal synchronizing signal is supplied is connected to an inverting input terminal of an operational amplifier 24 through an F/V converter 23. Also, the operational amplifier 24
The non-inverting input of is grounded. Further, the output of the operational amplifier 24 is connected to the inverting input terminal of the operational amplifier 24 through a resistor 25. The inverting input terminal of the operational amplifier 24 is also connected to a constant voltage source 27 of Va [V] through a resistor 26 . Further, the output of the operational amplifier 24 is connected to the inverting input terminal of the operational amplifier 36 through a resistor 28.

The non-inverting input terminal of the operational amplifier 36 is grounded, and the output of the operational amplifier 36 is connected to the inverting input terminal of the operational amplifier 36 through a resistor 37. Further, the output of the operational amplifier is connected to point B through a resistor 38. The R/Cext terminal of the mono multivibrator 29 is connected to point B through a resistor 32, and the R/Cext terminal of the mono multivibrator 29 is connected to a capacitor 31.
It is also connected to the Cext terminal through. The R/Cext terminal of the mono multivibrator 30 is connected to point B through a resistor 34, and the mono multivibrator 3
The R/Cext terminal of 0 is connected to Cex through the capacitor 33.
It is also connected to the t terminal. Mono multi vibrator 29
, 30 B input, CLR terminal is Vc [V] constant voltage source 3
Connected to 5.

[0009] Furthermore, the mono-multivibrator 29, 3
0 means the B input and the CLR input terminal are in a HIGH state, and at the falling edge of the A input, the Q output generates a positive pulse of arbitrary width. Furthermore, the mono multivibrator is reset at the falling edge of the CLR input terminal. Further, the input terminal 22 to which the horizontal synchronizing signal is input is connected to the A input of the mono multivibrator 29, and the Q output of the mono multivibrator 29 is connected to the A input of the mono multivibrator 30.

Therefore, when the horizontal synchronizing signal is input to the A input of the mono multivibrator 29, the mono multivibrator 29 is set at the fall of the synchronizing signal. When set, the charge accumulated in the capacitor 31 is instantly discharged, and the R of the mono multivibrator 29 is
The /Cext terminal becomes the reference voltage, and the resistor 32 is connected from point B.
Electric charge begins to be charged to the capacitor 31 through the capacitor 31, and eventually the voltage at the R/Cext terminal of the mono multivibrator 29 reaches the threshold level. During ta [s] after setting until the R/Cext terminal voltage of the mono multivibrator 29 reaches the threshold voltage, a positive pulse is generated from the Q output, and at the falling edge of the pulse, the mono multivibrator 30 is activated. Set. This ta is given by the following equation.

ta=−Cext1×Rext1×loge((V
b-Vr1)÷Vb)...(1) However, Cext1 is the Cext terminal of the mono multivibrator 29 and R/Ce.
It is the capacitance of the capacitor 31 between the xt terminals, and Rext
is the resistance value of the resistor 32 between the Rext terminal of the mono multivibrator 29 and point B, Vb is the voltage at point B, and Vr1 is the R/C of the mono multivibrator 29.
This is the threshold voltage of the ext terminal. Note that e is a natural logarithm. Furthermore, when the mono multivibrator 30 is set, the charge accumulated in the capacitor 33 is instantly discharged and the mono multivibrator 30 R/
The Cext terminal becomes the reference voltage, and the capacitor 33 starts to be charged from point B through the resistor 34, and eventually the voltage at the R/Cext terminal of the mono multivibrator 30 reaches the threshold level. A positive clamp pulse is generated from the Q output during tb [s] after setting until the R/Cext terminal voltage of the mono multivibrator 30 reaches the threshold voltage. This tb is given by the following formula.

tb=-Cext2×Rext2×loge((V
b-Vr2)÷Vb)...(2) However, Cext2 is the Cext terminal of the mono multivibrator 30 and R/Ce.
It is the capacitance of the capacitor 33 between the xt terminals, and Rext
is the resistance value of the resistor 34 between the Rext terminal of the mono multivibrator 30 and point B, Vb is the voltage at point B, and Vr2 is the R/C of the mono multivibrator 30.
This is the threshold voltage of the ext terminal. Note that e is a natural logarithm.

Therefore, in this circuit, when a horizontal synchronizing signal is input to the horizontal synchronizing signal input terminal 22, it is converted into a voltage signal by the F/V converter 23, and then sent to the operational amplifiers 24, 3.
6 and becomes the voltage Vb [V] at point B. Note that this F/V converter operates in such a way that the higher the input frequency, the higher the output voltage. That is, the voltage Vb at point B changes depending on the synchronization frequency of the horizontal synchronization signal. V
By changing b, mono multivibrator 29,
Resistors 32 and 34 between the R/Cext terminal of 30 and point B
The current flowing through changes, and ta and tb can be varied.

Therefore, in this circuit, as the frequency of the synchronizing signal input to the display device increases, V
b also becomes higher, so the current flowing through the resistors 32, 34 increases, the time ta, tb required for reaching the threshold voltage from the reference voltage becomes shorter, and the pulse width of the clamp pulse becomes shorter.

[0015]

[Effects of the Invention] As explained above, the present invention has a structure in which the pulse width of the clamp pulse input to the video amplifier is varied in accordance with the frequency of the synchronizing signal.
This has the effect of preventing the clamp pulse from going beyond the back porch and clamping the video display section when the synchronization frequency is high.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an example of the present invention.

FIG. 2 is a circuit diagram of a conventional clamp pulse circuit.

FIG. 3 is a waveform diagram of a video signal input to a video amplifier and a clamp pulse in a conventional circuit.

[Explanation of symbols]

15, 16, 29, 30 Mono multivibrator 23 F/V converter 24, 36 Operational amplifier

Claims (1)

[Claims] 1. A clamp pulse comprising an F/V converter that inputs a horizontal synchronization signal and converts the synchronization frequency into a voltage signal, and an operational amplifier that outputs the output of the F/V converter variably according to the frequency of the synchronization signal. The clamp pulse width is composed of a variable width circuit and a clamp pulse generation circuit consisting of at least one mono-multivibrator, and outputs the clamp pulse width to the video amplifier by controlling the variable clamp pulse width circuit according to the synchronization frequency of the horizontal synchronization signal. Video amplifier clamp pulse circuit characterized by variable