JPH05314662A - Information receiving circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] When priority information is set in each priority encoder of the information receiving circuit and data is input to only one side of the information receiving circuit, the word sync clock signal of that data is sent to the device. It is applied to multi-channel digital devices such as so-called PCM recorders by using one of the word sync clock signals as a synchronous clock of the device according to the priority information when data is input to both of the information receiving circuits. In this case, you can check whether the device is receiving input data, and eliminate complicated and troublesome work such as selecting which input to synchronize with multiple external inputs. Be able to prevent accidents due to work mistakes. [Configuration] A plurality of interface circuits 16 are provided, and when information is input via the plurality of interface circuits 16, a priority is given to each input, and a word sync clock signal is selected in accordance with this priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to, for example, DASH (Di
digital Audio Stationary He
The present invention relates to an information receiving circuit suitable for being applied to a multi-channel digital device such as an ad) format digital audio recorder.

[0002]

2. Description of the Related Art Conventionally, a digital audio tape recorder of, for example, DASH format has been proposed.

This tape recorder has sampling frequencies of 32 kHz, 48 kHz and 44.1 kHz.
For 6-bit professional digital audio, the combination of tape width, track density and tape speed can cover 2 to 48 channels.

In a multi-channel digital device typified by such a tape recorder, for example, a large number of devices that output audio information serving as a source are connected, and audio information supplied from these plural devices is recorded on a tape. Has been done.

When an input from the outside is taken in, it is necessary to synchronize a synchronizing signal (sync word clock) in the input information, and a circuit for performing such processing is shown in FIG. Such a thing has been conventionally proposed.

The information receiving circuit shown in FIG. 2 receives digital audio data supplied through an input terminal 1 of a multi-channel digital device (not shown), for example, AES / E.
BU (Audio Engineering Society /
(European broadcast union) Digital interface circuit 3 receives the audio data and sync word clock data of the received data by PLL circuit 2, and sync circuit 4 synchronizes the extracted sync word clock data, The audio data extracted by the signal processing circuit 5 of the digital device main body circuit (not shown) is subjected to predetermined signal processing by the clock output from the synchronizing circuit 4 and output as an audio signal via the output terminal 6.

The format of the above-mentioned input data will be described below. In this transmission format, when one cycle of the signal shown in FIG. 3A is used as the sampling frequency, channel A is in the high level "1" period of the signal shown in FIG. 3A. , Channel B is in the low level “0” period of the signal shown in FIG. 3A.

As shown in FIG. 3B, the input data are word sync clock data SYN in order from the beginning.
C, track density, sampling frequency, tape speed, reserved bits, twin recording usage, cue track usage, data track usage,
AUX data AUX indicating whether emphasis is used, audio data AUDIO DATA, flag FLAG
Composed of.

That is, in the above information receiving circuit, when receiving the input data shown in FIG. 3B, the audio data AUDIO DATA, the flags FLAG, and AUX are received.
In order to receive and process the data AUX in the signal processing circuit 5, the word sync clock data SYNC is synchronized in the synchronizing circuit 4, and the clock thus obtained is supplied to the signal processing circuit 5 of the digital device main circuit (not shown). I was doing.

There are the following two types of such digital devices for connecting many devices and receiving audio data from these many devices, for example.

One is to use a word sync clock for one of the many external input terminals, and the input terminal is the output terminal of the one of the many equipment to which the user wants to give priority. The other is a type that decides which device has priority (which device is synchronized) among many devices connected on the display or by a switch, for example. Is.

In the former case, the user connects the output terminal of the device to be prioritized to the designated input terminal, and in the latter case, while confirming the input of the data from the connected device to the digital device, The device to be prioritized is specified by the operation panel or switch.

[0013]

By the way, as described above, in a digital device capable of connecting many devices, one input terminal among a plurality of input terminals for inputting the device is synchronized. If the input terminal is specified as specified, or if many devices are connected and the input is confirmed while the input is being confirmed with the operation panel or switch, the device that is prioritized You have to check if the signal can be extracted and then choose which input has priority,
There is an inconvenience in that the user has to perform complicated and troublesome work and causes an accident due to a work mistake.

The present invention has been made in view of the above points, and when it is applied to a multi-channel digital device, it is possible to confirm whether or not the device is receiving input information and to select one of a plurality of external inputs. It is an object of the present invention to propose an information receiving circuit which eliminates complicated and troublesome work such as selection of which input is to be synchronized and the like, and prevents accidents due to work mistakes.

[0015]

The present invention has a plurality of interface means 16 as shown in FIG. 1, for example. When inputting information through the plurality of interface means 16, a priority order is given to each input. The synchronization information is selected according to this priority order.

Further, according to the present invention, for example, as shown in FIG. 1, a plurality of interface means 16 are provided, and when inputting information through the plurality of interface means 16, a priority order is given for each input, and according to this priority order. The synchronization information is automatically selected.

The present invention also includes an interface circuit 16 and the interface circuit 1 as shown in FIG.
A buffer 18 for storing the synchronization information of the information input in 6
And a reception status information output circuit 17 that outputs information indicating a reception status based on information indicating whether or not it is received from the interface circuit 16 and identification information from the outside, and priority information of the interface circuit 16 is output. The priority order information output circuit 21, which compares the priority order information from the priority order information output circuit 21 and the identification information from the outside, and controls the buffer 18 based on the comparison result.
2 and a second circuit 15 having the same configuration as the first circuit 10, and each priority information output circuit 21 of each of the first circuit 10 and the second circuit 15 Selects the synchronization information extracted from the input information of the first circuit 10 or the second circuit 15 based on the information indicating the reception status from each reception status information output circuit 17 and the predetermined priority order information. It was done.

[0018]

According to the present invention described above, when inputting information through a plurality of interface means 16, a priority is given to each input and the synchronization information is selected according to this priority, so that multi-channels are selected. When applied to a digital device of the above, it is necessary to check whether the device is receiving input information, select complicated input from multiple external inputs, etc., and It is possible to eliminate troublesome work and prevent accidents due to work mistakes and the like.

Further, according to the present invention described above, when the information is input through the plurality of interface means 16, the priority is given to each input, and the synchronization information is automatically selected according to the priority. When applied to a multi-channel digital device, it can be used to check whether the device is receiving input information,
It is possible to eliminate troublesome and troublesome work such as selection work to be synchronized with which input, and prevent accidents due to work mistakes and the like.

Further, according to the present invention described above, the interface circuit 16, the buffer 18 for storing the synchronization information of the information input to the interface circuit 16, the information indicating whether the interface circuit 16 is receiving or not, A reception status information output circuit 17 that outputs information indicating a reception status based on identification information from the outside, a priority information output circuit 21 that outputs priority information of the interface circuit 16, and a priority from the priority information output circuit. A first circuit 10 having a comparison circuit 22 that compares the order information with identification information from the outside and controls the buffer 18 based on the comparison result, and a second circuit having the same configuration as the first circuit 10. Information indicating the reception status from each reception status information output circuit 17 by each priority information output circuit 21 of the circuit 15 and a predetermined priority Since the synchronization information extracted from the input information of the first circuit 10 or the second circuit 15 is selected based on the information, when applied to a multi-channel digital device, the device receives the input information. It is possible to prevent accidents due to work mistakes, etc. by eliminating the complicated and troublesome work such as checking whether or not there are multiple external inputs and selecting which input to synchronize with. ..

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information receiving circuit of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 11 denotes an input terminal of a digital device (not shown) (for example, a DASH format digital recorder), and an external device not shown (for example, DAT, CD player, etc.) via the input terminal 11.
The audio data of the transmission format of AES / EBU (Audio Engineering Society / European Broadcast Union) is supplied to the digital audio interface circuit 16 which constitutes the information receiving circuit 10.

When digital data of the format shown in FIG. 3B, for example, is supplied to the digital audio interface circuit 10 via the input terminal 11, for example, an internal PLL circuit (not shown) causes a word sync clock in the digital data. When a signal is extracted, the extracted word sync clock signal is synchronized with an internal synchronizing circuit (not shown), the synchronized word sync clock signal is supplied to the output buffer 18, and when the word sync clock signal can be correctly extracted. , And supplies an extraction state signal indicating that fact to the selector 17.

Further, the digital audio interface circuit 16 supplies the input data after extracting the word sync clock signal to the signal processing circuit of the digital equipment main circuit (not shown).

The above word sync clock signal is a system clock corresponding to the extracted sampling frequency.

On the other hand, the identification data from the digital device main body circuit (not shown) is supplied to the comparator 22 and the selector 17 through the input terminal 12, respectively. Here, the identification data is identification data indicating the information receiving circuit (information receiving board) 10.

The selector 17 outputs the extraction status signal from the digital audio interface circuit 16 to the corresponding signal line 19 based on the identification data.

The output extraction state signal is the signal line 19
Through the priority encoder 21.
The priority encoder 21 generates identification data corresponding to the extraction state signal supplied via the signal line 19 or 20, and supplies this identification data to the comparator 22.

Here, this priority encoder 2
For example, when one extraction state signal is supplied via the signal line 19 or 20, 1 outputs identification data indicating the information receiving circuit 10 or 15 that has output the one extraction state signal. When both extraction state signals are supplied via 19 and 20, the identification data indicating the information receiving circuit 10 or 15 which outputs one extraction state signal is output in accordance with the preset priority order.

The comparator 22 compares the identification data from the priority encoder 21 with the identification data supplied from the input terminal 12, and if they match each other, supplies a control signal to the output buffer 18 and the word once stored in the output buffer 18. The sync clock signal is supplied via an output terminal 23 to a digital device main body circuit (not shown) on which the information receiving circuit 10 is mounted.

Reference numeral 15 is also an information receiving circuit, and its internal structure is similar to that of the information receiving circuit 10. This information receiving circuit 1
5 also extracts the word sync clock from the digital data supplied from the external device via the input terminal 13 by the digital audio interface circuit 16, supplies the extracted word sync clock signal to the output buffer 18, and further extracts this. Is supplied to the selector 17 and the input data after extracting the word sync clock signal is sent to the signal processing circuit of the digital equipment main circuit (not shown) in which the information receiving circuit 15 is mounted. Supply.

When identification data indicating the information receiving circuit (information receiving board) 15 is supplied from the digital device main body circuit (not shown) via the input terminal 14, the selector 17 supplies the identification data to the digital audio interface circuit. The extraction state signal from 16 is supplied to the priority encoder 21 via the corresponding signal line 20, and the identification number corresponding to the extraction state signal supplied via the signal line 19 or 20 in the priority encoder 21 is supplied to the comparator 22. Then, in this comparator 22, the priority encoder 2
The identification data from No. 1 and the identification data supplied via the input terminal 14 are compared. When they match, a control signal is supplied to the output buffer 18, and the once stored word sync clock signal is shown via the output terminal 23. Not supplied to the digital device main circuit.

Next, the operation of the above-described information receiving circuits 10 and 15 will be described as follows. That is, first,
When the digital data is supplied only to the information receiving circuit 10, the digital audio interface circuit 16 of the information receiving circuit 10 outputs the word sync clock signal to the output buffer 18, and the digital data obtained by extracting the word sync signal is not shown in the digital device. When the extraction is correctly performed, the signal processing circuit of the main body circuit is supplied with the extraction state signal to the selector 17, respectively.

Then, the extraction status signal from the digital audio interface circuit 16 is supplied to the priority encoder 21 through the signal line 19 according to the identification data supplied through the input terminal 12. Since the priority encoder 21 is not supplied with the extraction state signal from the signal line 20 and is supplied with the extraction state signal from the signal line 19, the priority encoder 21 supplies the identification data indicating the information receiving circuit 10 to the comparator 22.

Since the comparator 22 matches the identification data from the input terminal 12 with the identification data supplied from the priority encoder 21, the comparator 22 controls the output buffer 18 so that the word sync clock signal stored in the output buffer 18 is synchronized with the device synchronization clock. Is supplied to the digital device main circuit (not shown) via the output terminal 23.

Next, the digital data is transferred to the information receiving circuit 1
5, the digital audio interface circuit 16 of the information receiving circuit 15 outputs the word sync clock signal to the output buffer 18, and the digital data extracted from the word sync signal is the signal processing circuit of the digital device main circuit (not shown). In addition, when the extraction is correctly performed, the extraction state signals are supplied to the selector 17, respectively.

Then, the extraction status signal from the digital audio interface circuit 16 is supplied to the priority encoder 21 through the signal line 20 according to the identification data supplied through the input terminal 14. Since the priority encoder 21 is not supplied with the extraction state signal from the signal line 19 and is supplied with the extraction state signal from the signal line 20, the priority encoder 21 supplies the identification data indicating the information receiving circuit 15 to the comparator 22.

Since the comparator 22 matches the identification data from the input terminal 14 with the identification data supplied from the priority encoder 21, the comparator 22 controls the output buffer 18 so that the word sync clock signal stored in the output buffer 18 is synchronized with the device synchronization clock. Is supplied to the digital device main circuit (not shown) via the output terminal 23.

On the other hand, when digital data is input to both of the information receiving circuits 10 and 15, the priority encoders 21 of the information receiving circuit 10 and the information receiving circuit 15 follow the preset priority order information.
The identification data indicating one of the information receiving circuits 10 or 15 is output.

Therefore, in this case, only the buffer 18 of the information receiving circuit 10 or 15 having the higher priority outputs the data, and the word sync clock signal thereof is not shown in the figure via the output terminal 23 as the synchronous clock of the device. It is supplied to the digital device main circuit.

For example, when the information receiving circuit 10 is set to have priority and the identification data of the information receiving circuit 10 is "1" and the identification data of the information receiving circuit 15 is "2", each information receiving circuit 10 The priority encoders 21 and 15 output "1", respectively. The comparing circuit 12 of the information receiving circuit 10 is supplied with the identification data “1” from the input terminal 12, and the comparing circuit 12 of the information receiving circuit 15 is supplied with the identification data “2” from the input terminal 14. It The comparison circuit 12 of the information receiving circuit 10 allows the output of the output buffer 18 because the identification data match, and the comparison circuit 12 of the information receiving circuit 15 does not allow the output of the output buffer 18 because the identification data does not match. Therefore, the word sync clock data in the data received by the information receiving circuit 10 is prioritized.

As described above, in this example, the information reception time
Priority encoders 21 on paths 10 and 15
The priority order information is set, and one of the information receiving circuits 10 or 15 is set.
If only one person inputs data, the data
The desync clock signal is used as the device's synchronization clock
If data is input to both the receiving circuits 10 and 15.
One of the word sync clocks according to the priority information
I decided to use the signal as the device's synchronization clock.
Multi-channel digital equipment such as Yuru PCM recorder
When applied to the
Check whether or not there are multiple external inputs.
Complexity of selection work such as whether to synchronize with force,
Eliminate troublesome work and prevent accidents due to work mistakes, etc.
You can stop.

In the above example, the case where the number of information receiving circuits is two, that is, 10 and 15, has been described, but the number may be equal to or greater than the number of input channels of the digital device.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0045]

According to the present invention described above, when inputting information through a plurality of interface means, a priority order is given for each input and the synchronization information is selected in accordance with this priority order. When applied to a digital device of a channel, it is necessary to check whether the device is receiving input information or to select which of a plurality of external inputs should be synchronized, such as the complexity of work. Moreover, there is an advantage that troublesome work can be eliminated and accidents due to work mistakes can be prevented.

Further, according to the present invention described above, when inputting information via a plurality of interface means, a priority is given to each input, and the synchronization information is automatically selected according to this priority. When applied to a digital device of a channel, it is necessary to check whether the device is receiving input information or to select which of a plurality of external inputs should be synchronized, such as the complexity of work. Moreover, there is an advantage that troublesome work can be eliminated and accidents due to work mistakes can be prevented.

Further, according to the present invention described above, the interface circuit, the buffer for storing the synchronization information of the information input to the interface circuit, the information indicating whether the interface circuit receives the information, and the identification from the outside. Reception status information output circuit that outputs information indicating reception status based on information, priority information output circuit that outputs priority information of interface circuit, priority information from priority information output circuit and external identification Each priority information output circuit of a first circuit having a comparison circuit for comparing information and controlling a buffer based on the comparison result and a second circuit having the same configuration as the first circuit receives each signal. Extracted from the input information of the first circuit or the second circuit based on the information indicating the reception state from the state information output circuit and the predetermined priority order information Since the synchronization information is selected, it is possible to check whether the device is receiving input information when applying it to a multi-channel digital device, and to select which input among multiple external inputs. There is an advantage that complicated work such as selecting whether to apply synchronization and complicated work can be eliminated, and accidents due to work mistakes can be prevented.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an information receiving circuit of the present invention.

FIG. 2 is a configuration diagram showing an example of a conventional information receiving circuit.

FIG. 3 is a timing chart for explaining an example of a conventional information receiving circuit.

[Explanation of symbols]

 10, 15 Information receiving circuit 16 Digital audio interface circuit 17 Selector 18 Output buffer 21 Priority encoder 22 Comparator

[Procedure amendment]

[Submission date] July 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

As shown in FIG. 3B, the input data are word sync clock data SYN in order from the beginning.
AU such as C, sampling frequency, reserved bits, use of data track, use of emphasis, etc.
X data AUX, audio data AUDIO DAT
A flag FLAG.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

For example, when the information receiving circuit 10 is set to have priority and the identification data of the information receiving circuit 10 is "1" and the identification data of the information receiving circuit 15 is "2", each information receiving circuit 10 The priority encoders 21 and 15 output "1", respectively. Then, the comparison circuit 22 of the information receiving circuit 10, the identification data "1" from the input terminal 12 is supplied to the comparison circuit 22 of the information receiving circuit 15 is supplied with identification data "2" from the input terminal 14 It The comparison circuit 22 of the information receiving circuit 10 permits the output of the output buffer 18 because the identification data match, and the comparison circuit 22 of the information receiving circuit 15 does not permit the output of the output buffer 18 because the identification data do not match. Therefore, the word sync clock data in the data received by the information receiving circuit 10 is prioritized.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display part H04L 29/06

Claims (3)

[Claims] 1. A plurality of interface means are provided, and when inputting information through the plurality of interface means, priority is given to each input, and synchronization information is selected according to this priority. Characteristic information receiving circuit. 2. A plurality of interface means are provided, and when inputting information through the plurality of interface means, priority is given to each input, and synchronization information is automatically selected according to this priority. An information receiving circuit characterized by: 3. An interface circuit, a buffer for storing synchronization information of the information input to the interface circuit, a reception based on information indicating whether the interface circuit is receiving or not, and identification information from the outside. A reception status information output circuit that outputs information indicating a status, a priority information output circuit that outputs priority information of the interface circuit, priority information from the priority information output circuit, and identification information from the outside. A first circuit having a comparison circuit for comparing and controlling the buffer based on the comparison result; and a second circuit having the same configuration as the first circuit, the first circuit and Each priority order information output circuit of the second circuit is based on the information indicating the reception status from each reception status information output circuit and the predetermined priority order information. The information receiving circuit characterized in that the synchronization information extracted from the input information of the first circuit or the second circuit is selected.