JPH05316539A - Picture processing circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce line flicker of color difference signals. [Structure] A memory 26 stores a luminance signal, and a memory 28
Stores the dot-sequential color difference signal. The memories 26 and 28 have a storage capacity of 1 frame. Adder circuit 30 and 1/2
The division circuit 32 of 1 performs a weighted average of the signal read from the memory 28 and the current signal, and writes the weighted average in the memory 28. The memory control circuit 52 uses the memory 26,
28, a read control signal 52a one line before and a read control signal 52b one frame before are generated. The selection device 54 has a switch 56 depending on whether a moving image input or a still image input.
To control. When a moving image is input, a signal of one line before is read from the memories 26 and 28, and when a still image is input, a signal of one frame before is read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit, and more particularly to an image processing circuit for converting a PAL video signal into a luminance / color difference signal.

[0002]

2. Description of the Related Art When converting a color signal of a PAL system video signal into a color difference signal, if the BY demodulation axis is 0 °, R-
The Y demodulation axis is phase-inverted to 90 ° and 270 ° for each line, and the chrominance signal of the PAL system video signal is quadrature demodulated. Therefore, when the color signal is constant, as shown in FIG. 2A, the RY signal levels of the line #n and the line # (n + 1) are the same, and there is no problem. However, when the two axes are not orthogonal as shown in (b) or when the inversion for each line is deviated from 180 ° as shown in (c),
The level of the color difference signal varies for each line. This level variation causes color line flicker on the monitor screen and horizontal color stripes on the video print output.

Therefore, in the conventional image processing circuit of this type, the demodulated color difference signals RY and BY are averaged with the signal of the immediately preceding line of the same screen or the signal of the same line of the previous screen. This reduces the above-mentioned line flicker.

[0004]

In the conventional example, since the color difference data is added and averaged between frames, the flicker of the color difference signal can be reduced when a still image is input, but a color afterimage occurs when a moving image is input. There is a problem of doing.

It is an object of the present invention to provide an image processing circuit that solves such a problem.

[0006]

An image processing circuit according to the present invention comprises a luminance memory means for storing a luminance signal of a PAL system video signal and having a storage capacity of at least one frame.
A color difference memory unit having a storage capacity of at least one frame for storing the color difference signal of the PAL system video signal, and a color difference signal input to store the color difference signal read from the color difference memory unit in the color difference memory unit. The weighted averaging means for weighted averaging and the signal read from the color difference memory means are the same as the signal of the immediately preceding line of the color difference signal of the same kind with respect to the signal input to be stored in the color difference memory means.
It is characterized by comprising memory control means for controlling the reading of the luminance memory means and the color difference memory means so as to be one of the signals before the frame.

[0007]

In the case of moving image processing by the above means, the signal of the immediately preceding line in the same screen is read from the color difference memory means and the weighted average means performs the weighted average. This allows
It is possible to reduce the line flicker of the color difference signal without causing a color afterimage. Further, in the case of still image processing, the signal of the previous screen and the current signal are weighted and averaged. As a result, the line flicker of the color difference signal can be reduced without deteriorating the vertical resolution of the color difference signal.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the sampling rate of the luminance signal and the color difference signal is set to 2: 1 and the memories 26 and 28 are
Stores sample data as shown in FIG.

Although details will be described later, in the present embodiment, the memories 26 and 28 are made to selectively function as delay means corresponding to one line and delay means corresponding to one frame. That is, in the case of moving image input, it functions as a delay unit for one line, and in the case of still image input, it functions as a delay unit for one frame.

For this purpose, the following circuits are provided. That is, the sync separation circuit 50 separates the horizontal sync signal H and the vertical sync signal V from the Y + S data output from the A / D converter 16, and the memory control circuit 52 separates the sync separation circuit 50.
1 line delay read control signal 52a and 1 frame delay read control signal 5 according to the synchronizing signals H and V from FIG.
2b is output. The selection device 54 includes a switch for selecting or designating a moving image process or a still image process, or a device for detecting a moving image input or a still image input by a time sample between frames or fields of an input image,
The switch 56 is controlled. The switch 56 selects the read control signal 52a with 1 line delay in the case of moving image processing (or moving image input), and selects the read control signal 52b with 1 frame delay in the case of still image processing (still image input). Then, the selected read control signal is applied to the read control terminals of the memories 26 and 28.

The overall operation of FIG. 1 will be described. The Y / C separation circuit 10 separates the PAL system video signal into a luminance signal Y + S and a chrominance signal C on which a synchronization signal S is superimposed, and a decoder 12 separates the separated chrominance signal C into color difference signals RY and B-. Y
Convert to. The oscillator circuit 14 has a subcarrier frequency fsc.
Of the signal Y output from the Y / C separation circuit 10.
+ S is converted into a digital signal at 4fsc, and the A / D converters 18 and 20 respectively convert the color difference signals RY and BY output from the decoder 12 into digital signals at 4fsc.

The frequency divider circuit 22 divides the output of the oscillation circuit 14 into 1 /
The frequency is divided by 2 and a 2 fsc clock is output. Switch 2
4 is switched by the clock of 2 fsc, and A /
The outputs R-Y and B-Y of the D converters 18 and 20 are alternately selected to be dot-sequential.

By the sync separation circuit 50, the memory control circuit 52 causes the read control signal 52a with one horizontal line delay and the read control signal with one frame delay according to the horizontal sync signal H and the vertical sync signal V of the input PAL video signal. 52
Output b. The selection device 54 outputs the control signal indicating the moving image processing or the still image processing as described above, and the switch 56.
To control. The switch 56 is set to 1 for moving image processing.
The line delay read control signal 52a is selected, and in the case of still image processing, the 1 frame delay read control signal 52 is selected.
b, select the read control signal from the memory 26,
28 read control terminals.

The memory 26 sequentially stores the Y + S data output from the A / D converter 16 according to the 4 fsc clock output from the oscillation circuit 14, and the stored data is stored in the memory control circuit 52 via the switch 56. The read control signal 52a or 52b supplied from the read control signal 52a is read and read. That is, in the case of moving image processing, the storage data of one horizontal line before is read out, and in the case of still image processing, the storage data of one frame before is read out.

On the other hand, the color difference data R-Y and B-Y dot-sequentialized by the switch 24 are applied to the memory 28 via the adder 30 and the 1/2 divider 32. Memory 2
8 stores the output of the divider 32 according to the clock of 4 fsc. Similar to the memory 26, the reading of the memory 28 is controlled by the read control signal 52a or 52b supplied from the memory control circuit 52 via the switch 56. In the case of moving image processing, the storage data of one horizontal line before is stored. Is read out, and in the case of still image processing, the stored data of one frame before is read out. The read data is applied to the adder 30. The adder 30 and the divider 32 calculate the average value of the current color difference data and the color difference data of one horizontal line before (during moving image processing) or one frame before (during still image processing), and are written in the memory 28. ..

The color difference data read from the memory 28 is also separated by the switch 34 into RY data and BY data. The switch 34 is switched by a 2fsc clock.

The D / A converter 36 converts the Y + S data read from the memory 26 into an analog signal at the clock 4fsc, and the D / A converter 38 clocks the RY data separated by the switch 34. 2fsc converts into an analog signal, and the D / A converter 40 converts the BY data separated by the switch 34 into an analog signal with a clock 2fsc.

In the present embodiment, the color difference signals are weighted and averaged in one horizontal line when a moving image is input, and the weighted average is performed in one frame when a still image is input. This reduces the line flicker of the color difference signal. Further, since the weighted average is not performed between frames when a moving image is input, a color afterimage does not occur, and when the still image is input, a weighted average is not performed between lines, so that the vertical resolution of the color difference signal is not deteriorated.

In the embodiment of FIG. 1, when the switch 56 is switched in the image portion of the PAL video signal, a discontinuous portion occurs in the output video signal due to the difference in delay time. To prevent this, the switch 56 may be operated within the vertical blanking period. FIG. 4 shows a configuration block diagram of a modified embodiment in which the selection control signal from the selection device 54 is synchronized by the vertical synchronizing signal V and the switch 56 is switched within the vertical blanking period.

The output of the selector 54 is input to the data (D) input terminal of the D flip-flop 60, and the vertical synchronizing signal V separated by the sync separation circuit 50 is input to the clock (CK) input terminal of the D flip-flop 60. Enter and that Q
The output switches and controls the switch 56. The Q output of the D flip-flop 60 is a signal obtained by synchronizing the output of the selection device 54 with the vertical synchronizing signal V, whereby the switching of the switch 56 is performed within the vertical blanking period. As a result, the read phases of the memories 26 and 28 are also switched within the vertical blanking period, and the discontinuity due to the switch of the read phases does not appear on the display screen of the output signal.

[0022]

As can be easily understood from the above description, according to the present invention, line flicker can be reduced for both moving images and still images, and further, color afterimage and vertical resolution can be improved.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 shows luminance data Y and color difference data RY, B-
It is explanatory drawing of memory arrangement of Y.

FIG. 3 is a phase explanatory diagram when demodulating a color signal into a color difference signal.

FIG. 4 is a configuration block diagram of a modification of FIG.

[Explanation of symbols]

10: Y / C separation circuit 12: Decoder 14: Oscillation circuit 16, 18, 20: A / D converter 22: Frequency divider circuit 24: Switch 26, 28: Memory 30: Adder 32: Divider 34: Switch 36 , 38, 40:
D / A converter 50: Synchronization separation circuit 52: Memory control circuit 54: Selection device 56: Switch 60: D flip-flop

Claims (1)

[Claims] 1. A luminance memory means for storing a luminance signal of a PAL system video signal, and a luminance memory means having a storage capacity for at least one frame, and a color difference signal of a PAL system video signal.
A color difference memory unit having a storage capacity of at least one frame, and a color difference signal read from the color difference memory unit,
The color difference signal of the same kind as the signal input to be stored in the color difference memory means, and the weighted average means for performing weighted averaging with the color difference signal input to be stored in the color difference memory means, and the signal read from the color difference memory means. 2. An image processing circuit, comprising: memory control means for controlling the reading of the luminance memory means and the color difference memory means so as to be either the signal of the immediately preceding line or the signal of the preceding frame.