JPH053213A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To prevent a leakage current from flowing from a source electrode through an active layer to a drain electrode and reduce a side gate effect pro duced upon a plurality of MOSFETs being formed on the same substrate by bringing into coincidence a tip end of the gate electrode with a boundary of an active layer region with the aid of self-alignment. CONSTITUTION:A passivation film 2 is formed on the entire surface of a GaAs semiinsulating substrate 1, and a photo resist layer 3 of an active layer (n layer) selection doping pattern is formed with photolithography and thereafter the passivation film 2 exposed to an opening part is removed. A removed portion is ion-doped to form an active layer 4. Then, a heat resistant gate metal 5 is deposited, and the photoresist 3 and the heat-resistant gate metal 5 formed on the former are removed by a lift-off process. A contact layer for a source- drain electrode is formed on the same side as the tip end of the gate electrode 5 or inside the same to form a source electrode 6 and a drain electrode 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a GaAs MESFET.

[0002]

2. Description of the Related Art A conventional GaAs MESFET is shown in FIG.
As shown in FIGS. 3A and 3C, the tip of the gate electrode is designed and manufactured so as to extend outside the active layer region by about 0.5 to 1 μm. This is because if the tip of the gate electrode is located inside the active layer region, a leakage current that goes around the tip of the gate electrode is generated between the source and drain electrodes, so that the tip of the gate electrode may be displaced due to misalignment in photolithography. The tip of the gate electrode is exposed outside the active layer region by a length greater than the alignment accuracy so as not to be located inside the active layer region.

FIG. 3A shows a conventional GaAs MESFE.
FIG. 3B is a cross-sectional view taken along the line AA ′ shown in FIG. 3A, and FIG. 3C is a B view shown in FIG. 3A. It is sectional drawing in -B '.

Since the gate electrode is located outside the active layer region, it is possible to suppress the leakage current flowing from the source electrode to the drain electrode through the active layer, and thus the MESFE can be suppressed.
The characteristics of each T are improved.

However, a plurality of MESFEs are formed on the same substrate.
When T is formed, each MESFET can be
A side gate effect appears that T adversely affects.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks by suppressing the leakage current flowing from the source electrode to the drain electrode via the active layer and forming a plurality of MESFETs on the same substrate. The purpose is to reduce the side gate effect.

[0007]

According to the present invention, a passivation film is formed on the surface of a semiconductor device and a semiconductor device characterized in that at least one tip of a gate electrode is aligned with the boundary of an active layer region. Then, a photoresist is formed on the passivation film by photolithography as a gate electrode pattern, and after removing the passivation film on the gate electrode portion by the gate electrode pattern of the photoresist, the photoresist is removed. A semiconductor device in which an active layer is formed by implanting ions in a portion where a passivation film is removed, a gate metal is vapor-deposited on the entire surface of the substrate, and the photoresist and excess gate metal are removed by a lift-off method. The present invention provides a method for manufacturing the same.

According to the present invention, the leakage current flowing from the source electrode to the drain electrode via the active layer can be suppressed and the side gate effect when a plurality of MESFETs are formed on the same substrate can be reduced.

YI LIU et al. Compare the side gate effect between the case where the tip of the gate electrode is formed outside the boundary of the active layer region and the case where it is formed inside the boundary of the active layer region. , The former has a larger side gate effect than the latter (IEEE Electron Device Letter Vol. 11, No. 11 (1990), pages 505-5).
07).

However, in order to reduce the side gate effect, if the tip portion of the gate electrode is simply formed inside the boundary of the active layer region, the leakage current flowing from the source electrode to the drain electrode via the active layer will be described. Cannot be suppressed.

Therefore, the present inventor reduces the side gate effect without considering the misalignment of alignment in photolithography by aligning the tip of the gate electrode with the boundary of the active layer region by self-alignment. However, the leakage current flowing from the source electrode to the drain electrode via the active layer is suppressed.

[0012]

EXAMPLE An example of the present invention will be described below with reference to FIG. A passivation is applied to the entire surface of the GaAs semi-insulating substrate 1.
A SiNx film 2 having a thickness of 0.1 μm is formed by plasma CVD as an ionization film, and a photoresist layer 3 having an active layer (n layer) selective ion implantation pattern is formed thereon by photolithography, and then exposed in an opening. SiNx
The membrane 2 is removed by reactive ion etching (Fig. 1
(A)).

Next, ²⁹ Si + was ion-implanted into the active layer (n-layer) 4 with an implantation energy of 40 keV from above by 3 × 10 ¹² cm ^-2 (FIG. 1 (b)).

Then, WSix as the heat-resistant gate metal 5 was vapor-deposited from above by sputtering (FIG. 1).
(C)).

Next, the photoresist layer 3 and excess heat-resistant gate metal 5 formed thereon are removed by a lift-off method (FIG. 1 (d)).

Next, ²⁹ Si + was injected through the SiNx film 2 by through injection, with an injection energy of 240 keV and 3 × 1.
After selectively implanting 0 ¹³ cm ^-2 ions to form a contact layer (n + layer) for a source / drain electrode, a source electrode 6 and a drain electrode 7 are formed (FIG. 1E). At this time, the contact layer (n + layer) is formed at the same end as or inside the tip of the gate electrode 5.

After that, the GaAs MESFET is manufactured through the conventional steps of forming the first layer wiring, the interlayer insulating film forming step, the via hole forming step, and the second layer wiring forming step.

FIG. 2 shows the difference in side gate effect between the GaAs FET according to the present invention and the conventional GaAs FET. FIG. 2 is a diagram showing changes in drain current with respect to side gate voltage. From this figure, GaA according to the present invention
In the sFET, the drain current does not suddenly change (decrease) with respect to the side gate voltage in the measurement range, but the conventional Ga
In the As FET, a drastic decrease in drain current occurs at a side gate voltage of -5V, and GaAs according to the present invention is used.
It can be seen that the FET is effective in reducing the side gate effect.

Further, in the present invention, since the first layer wiring is entirely formed on the passivation film, the wiring metal and G
Since there is no contact with the aAs semi-insulating substrate, there is also the effect of reducing the leakage current through this portion.

[0020]

According to the present invention, the tip of the gate electrode and the boundary of the active layer region are aligned by self-alignment, so that the leakage current flowing from the source electrode to the drain electrode through the active layer is suppressed and the same. The side gate effect when forming a plurality of MESFETs on the substrate could be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to the present invention, (e) is a top view of the semiconductor device after the formation of the source / drain electrodes, and (a) to (d) are all (e) ) C
It is the figure which looked at the cross section in -C 'in order of a process.

FIG. 2 is a diagram showing a side gate effect of a semiconductor device according to the present invention and a conventional semiconductor device.

3A and 3B are views showing a conventional semiconductor device, FIG. 3A is a top view, and FIG. 3B is a sectional view taken along line AA ′ of FIG.
(C) is a sectional view taken along line BB ′ of (a).

Claims (4)

[Claims] 1. A semiconductor device, wherein at least one tip of a gate electrode is aligned with a boundary of an active layer region. 2. The semiconductor device is GaAs MESF.
A semiconductor device characterized by being ET. 3. A passivation film is formed on the surface of a substrate, a photoresist is formed on the gate electrode pattern by photolithography on the passivation film, and the gate electrode pattern of the photoresist is used to form the gate electrode pattern. After removing the passivation film from the gate electrode portion, ions are implanted into the passivation film removed portion to form an active layer, a gate metal is vapor-deposited on the entire surface of the substrate, and the photoresist and an extra gate are formed by a lift-off method. A method of manufacturing a semiconductor device, comprising removing a metal. 4. The semiconductor device is GaAs MESF.
A method of manufacturing a semiconductor device, which is ET.