JPH05325538A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make a semiconductor memory high in operation speed and also to expand an application range. CONSTITUTION:An internal address generation circuit 4 is provided for setting the value of a counter circuit 42 by a columnar address signal ADc at the time of the first change of a columnar address strobe signal CAS to an active level during the active level of a row address strobe signal RAS and incrementing or decrementing the value of the counter circuit 42 at the time of the change of the columnar address strobe signal CAS to a non-active level thereafter. The internal columnar address disnal IADc of the value of this counter circuit 42 is supplied to a columnar address decoder 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a high speed input / output function and suitable for image processing.

[0002]

2. Description of the Related Art Conventionally, as shown in FIGS. 3A and 3B as a first example, a semiconductor memory of this type has a plurality of memory cells arranged in rows and columns and a selection level. At this time, a memory cell array 1 having a plurality of word lines WL for selecting these memory cells in a row unit and a plurality of bit lines BL for transmitting data of each column of the plurality of memory cells, and a row address strobe signal RAS. Of the row address signal ADr from the outside when it changes to the active level (low level) of the row address strobe signal RAS.
And an address buffer circuit 2 which takes in and outputs a column address signal ADc from the outside when the column address strobe signal CAS, which becomes an active level a plurality of times previously set during the active level, changes to each active level. A row address decoder 3 which sets a predetermined word line of a plurality of word lines WL to a selection level according to a row address signal ADr from 2 and a predetermined bit line of a plurality of bit lines BL according to a column address signal ADc. The column address decoder 5 and the column selection switch circuit 6 of the column selection circuit, and the external supply of data to the memory cell of the memory cell array 1 in the selected state by the row address signal ADr and the column address signal ADc and from this memory cell. It has a data input / output circuit 7 that outputs the read data to the outside. And it has a configuration that.

In this semiconductor memory, after the row address signal ADr has been fetched once, the data in the same row can be continuously read by sequentially switching the column address (the same applies to writing. It is possible to increase the speed as compared with the normal read / write mode in which the row address and the column address are externally designated each time.

FIG. 4 is a timing chart showing a nibble mode of a second example of the conventional semiconductor memory.

In the nibble mode of this semiconductor memory, four addresses can be continuously accessed by an internal circuit by designating a row address and a column address once. Therefore, since the column address is not designated from the outside, the speed can be increased.

FIG. 5 is a timing chart of the static column mode of the third example of the conventional semiconductor memory.

In the static column mode of this semiconductor memory, all the memory cells in the row can be sequentially specified internally and accessed by designating a row address once, so that the speed can be further increased.

[0008]

In the conventional semiconductor memory described above, in the page mode of the first example, the memory cell at any column address of the row can be accessed by designating the row address once. Therefore, the speed is higher than that of the normal read / write mode, but there is a drawback that the speedup is restricted because the column address is specified from the outside. In the nibble mode of the second example, one row address is used. By specifying the column address and the column address, it is possible to access four addresses consecutively by the internal circuit, which speeds up the processing, but the number of consecutively accessible addresses is limited to "4", which causes a restriction in use. However, in the static column mode of the third example, the row address can be specified once to access all the addresses of the row by the internal circuit. Further speedup, for all the one line access, there is a drawback that also use constraints occurs.

An object of the present invention is to provide a semiconductor memory capable of accelerating its operation and relaxing restrictions on its use.

[0010]

A semiconductor memory according to the present invention comprises a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines which bring these memory cells into a selected state in a row unit at a selection level, And a memory cell array having a plurality of bit lines for transmitting data of each column of the plurality of memory cells, and a row address strobe for outputting a row address signal from the outside when the row address strobe signal changes to an active level. An address buffer circuit that takes in and outputs a column address signal from the outside when the column address strobe signal changes to an active level that is set to the active level a plurality of times during which the signal is at the active level, and a row from this address buffer circuit. According to the address signal, a row address deselecting a predetermined word line among the plurality of word lines as a selection level. And a counter, and sets the value of the counter by the column address signal from the address buffer circuit when the column address strobe signal changes to the first active level during the active level period of the row address strobe signal. An internal address generation circuit for incrementing (or decrementing) the value of the counter and outputting an internal column address signal of the counter value when the column address strobe signal changes to each inactive level; And a column selection circuit for selecting a predetermined bit line among the plurality of bit lines according to a signal.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A and 1B are a block diagram showing an embodiment of the present invention and a circuit diagram showing a concrete example of an internal address generator of this embodiment.

This embodiment differs from the conventional semiconductor memory shown in FIG. 3A in that it has a counter circuit 42 and the like, and a column address strobe signal CAS is provided while the row address strobe signal RAS is at an active level. When the column address strobe signal CAS changes to each inactive level, the value of the counter circuit 42 is set by the column address signal ADc from the address buffer 2 and the value of the counter circuit 42 is incremented ( Alternatively, the internal address generating circuit 4 that outputs the internal column address signal IADc of the value of the counter circuit 42 by decrementing is provided, and the internal column address signal IADc is supplied to the column address decoder 5. In this embodiment, the address buffer 2 may be a circuit which takes in the column address signal ADc only when the column address strobe signal CAS changes to the first active level when the row address strobe signal RAS is at the active level.

Further, the internal address generating circuit 4 is set by a first NOR gate G1 to which the row address strobe signal RAS and the column address strobe signal CAS are input, and the row address strobe signal set by the output of the first NOR gate G1. A flip-flop 41 that is reset by RAS, an inverter IV1 that inverts the output of the flip-flop 41, and a second that inputs the output of the inverter AV1 and the column address strobe signal CAS.
NOR gate G2 and a counter circuit 42 that internally takes in the value of the column address signal ADc when the flip-flop 41 is set and that increments (or decrements) the internal value by the output of the second NOR gate G2. It has been configured.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

In this embodiment, while the row address strobe signal RAS is at the active level (low level), the column address strobe signal CAS is externally set to the active level (low level) any number of times. A row address is specified when the row address strobe signal RAS changes to the active level, and an arbitrary number of addresses in the same row are accessed from the column address fetched when the column address strobe signal CAS changes to the first active level. Is possible (this is called serial page mode). Therefore, the range of application can be expanded with high-speed operation.

[0017]

As described above, according to the present invention, the value of the counter is set by the column address signal when the column address strobe signal changes to the first active level during the period of the active level of the row address strobe signal, and thereafter the column address signal is set. When the address strobe signal changes to each inactive level, the counter value is incremented or decremented, and the internal column address signal of this counter value is supplied to the column address decoder. Since the number of can be set arbitrarily and this address can be specified by the internal circuit, there is an effect that the operation can be speeded up and the applicable range can be expanded.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and a circuit diagram showing a specific example of an internal address generation circuit.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a first example of a conventional semiconductor memory and a timing diagram of signals in respective parts of a page mode of the semiconductor memory.

FIG. 4 is a timing chart of signals in various parts of a nibble mode of a second example of the conventional semiconductor memory.

FIG. 5 is a timing chart of signals in respective parts in a static column mode of a third example of the conventional semiconductor memory.

[Explanation of symbols]

 1 memory cell array 2 row address buffer 3 row address decoder 4 internal address generation circuit 5 column address decoder 6 column selection switch circuit 7 data input / output circuit

Claims (2)

[Claims] 1. A plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines which bring these memory cells into a selected state row by row at a selection level, and data of each column of the plurality of memory cells. A memory cell array having a plurality of bit lines for transmitting a row address signal, and a row address signal from the outside is taken in and output when the row address strobe signal changes to an active level, and the row address strobe signal is preset in the active level period. An address buffer circuit that takes in and outputs a column address signal from the outside when the column address strobe signal that becomes an active level a plurality of times changes to an active level, and among the plurality of word lines among the plurality of word lines according to a row address signal from the address buffer circuit. The row address decoder is provided with a row address decoder that uses a predetermined word line as a selection level and a counter. During the active level of the strobe signal, the value of the counter is set by the column address signal from the address buffer circuit when the column address strobe signal changes to the first active level, and each inactive of the column address strobe signal is set. An internal address generation circuit for incrementing (or decrementing) the value of the counter when changing to a level and outputting an internal column address signal of the counter value; and a plurality of bit lines among the plurality of bit lines according to the internal column address signal. A semiconductor memory having a column selection circuit for selecting a predetermined bit line. 2. An internal address generation circuit is set by a first NOR gate for inputting a row address strobe signal and a column address strobe signal, and is set by the output of the first NOR gate and reset by the row address strobe signal. A flip-flop, an inverter for inverting the output of the flip-flop, and a second for inputting the output of the inverter and the column address strobe signal.
Of the NOR gate and the address of the column address signal when the flip-flop is set.
2. The semiconductor memory according to claim 1, further comprising a counter that increments (or decrements) an internal value by the output of the OR gate.