JPH053260A - Wiring method for semiconductor integrated circuit and semiconductor integrated circuit according to the method - Google Patents

Abstract

PURPOSE:To suppress a variation in transmission time and generation of noises with a decrease in capacitance between wirings by keeping a specified long wiring or a critical path away from an adjacent wiring. CONSTITUTION:When the same first layer signal wirings 4,5,6,7 are present adjacent to a signal wiring 3 on the upper side and the lower side, the gap between the signal wiring 3 and each of 4,5,6,7 is doubled or more than that between signal wirings 6 and 8. Signal wirings which need enlargement of the gap from adjacent signal wirings are bus lines, clock lines, analog lines, long signal lines, and lines (critical paths) pointed by users. The wiring capacitance of a specified wiring can be reduced without so much increase in chip size; therefore, it is possible to raise the speed of circuit operations as well as suppress a variation in equivalent wiring capacitance, resulting in a stable action of a circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for a semiconductor integrated circuit and a semiconductor integrated circuit according to the method.

Conventionally, in the manufacture of semiconductor integrated circuits,
Wiring is performed with a constant wiring interval between the wirings.

FIG. 3 is a layout diagram showing an example of signal wiring of a conventional semiconductor integrated circuit. The semiconductor integrated circuit shown in this figure uses a two-layer wiring process. In this figure, 1 and 2 are element regions in which gates are formed, respectively, 3 to 8 are first-layer signal wirings, and 9 to 16 are second-layer signal wirings. Reference numerals 17, 17, ... Are through holes that connect the first-layer wiring and the second-layer wiring, respectively.

Capacitance exists between the signal wirings of the above layers and other adjacent signal wirings. For example, in the signal wiring 3, the signal wirings 4 to 4 of the same first layer are provided on the upper side and the lower side thereof.
7 are adjacent to each other, and a capacitance exists between each of these signal wirings 4 to 7.

FIG. 4 is a plan view showing a case where signal wirings are adjacent to each other. In the figure, reference numerals 20 to 22 denote signal wirings, respectively. The distance between the signal wiring 20 and the signal wiring 21 is d1, the distance between the signal wiring 21 and the signal wiring 22 is d2, and the wiring width of the signal wiring 21 is w1. It is set. In this case, in the conventional semiconductor manufacturing process, each wiring interval d
1, d2 and wiring width w1 are set to about 2 μm, aluminum is usually used as the wiring material, and the film thickness is set to 0.6 to 0.8 μm. Further, the interlayer film thickness of the signal wiring is set to about 0.8 μm.

Here, when the signal wiring is considered as a simple parallel plate, the electrostatic capacitance C therebetween is C = ε × ε ₀ × (wiring area) ÷ (interval), where ε is the relative permittivity of the interlayer film. ) Is given by. Note that ε ₀ is the dielectric constant of vacuum.

Now, as shown in FIG. 5, w1 = 2 μm,
Interlayer film thickness = 0.8 μm and wiring interval d1 = d2 = 2 μm
If m, the bottom capacitance C per unit length of the signal wiring 21
1 is C1 = ε × ε ₀ × (2 ÷ 0.8), and the side surface capacitance C2 between the signal wiring 20 and the signal wiring 21 is C2 = ε × ε ₀ × (0.8 / 2). Similarly, the side surface capacitance C3 between the signal wiring 21 and the signal wiring 22 is C3 = ε × ε ₀ × (0.8 ÷ 2). In this case, the ratio of the bottom surface capacity to the side surface capacity is 2.5: 0.8.

[0008]

By the way, since the delay time of a gate in a semiconductor integrated circuit depends on the driving capacity and load capacity of the gate, if the driving capacity is the same, the smaller the load capacity, the higher the speed. Further, since the load capacitance in the semiconductor integrated circuit is composed of the sum of the input capacitance of each gate and the wiring capacitance, the smaller the wiring capacitance is, the lower the load capacitance is, and the higher speed can be achieved.

However, since the wiring intervals of the respective signal wirings have been made constant in the related art, in a clock line, a bus line, an analog signal line, or the like, which lays a wiring region for a long time, these are adjacent to the wirings adjacent to each other. Is a problem, and this capacitance causes noise.

On the other hand, in the latest semiconductor manufacturing process, the wiring is becoming finer, and the wiring width and the wiring interval are 1.2 μm.
Some products have been prototyped.

As shown in FIG. 6, the film thickness of the interlayer film is 0.8 μm, which is the same as the above example, w1 = 1.2 μm, and the wiring interval d1 = d2 = 1.2 μm. Two
When calculating the bottom capacity and the side capacity per unit length of 1,
The bottom surface capacitance C1 ′ is ε × ε ₀ × 1.5, and the side surface capacitance C
2 '(C3') becomes ε × ε ₀ × 1.3. As can be seen from this result, the ratio of the side surface capacitance to the distribution wiring capacitance is very large. Therefore, when the miniaturization of the wiring progresses due to the progress of the semiconductor manufacturing process, the influence of the side surface capacitance on the wiring capacitance becomes very large, and it becomes very difficult to reduce the wiring capacitance.

Here, for reference, the signal wiring 21 of FIG.
Assuming that the inverter is connected to, the equivalent circuit is represented as shown in FIG. In this figure, 20
a, 21a and 22a are wirings 20 and 2 of FIG. 4, respectively.
1, 22 are contacts corresponding to the reference numeral C1 and the wiring 20,
21 represents the inter-wiring capacitance, and the reference symbol C2 is the wiring 2
The inter-wiring capacitance between 1 and 22 is shown.

When the wiring 20 is at the same potential as the power supply voltage and the wiring 22 is grounded (OV), the equivalent circuit is shown in FIG.
It becomes like (b). If both the wirings 20 and 22 are grounded in FIG. 4, the equivalent circuit is represented as shown in FIG. 7C. In this case, comparing the circuit of FIG. 7 (b) and the circuit of FIG. 7 (c), the load capacitances seen from the output terminal of the inverter INV have greatly different values. That is, the wiring capacitance itself varies depending on the signal level of the adjacent wiring. As a result, the signal transmission time of the internal circuit fluctuates, and in some cases the circuit itself may malfunction.

In other words, the wiring 2 adjacent to the wiring 21
The change in the signal level of the wirings 0 and 22 between the power supply voltage and the ground potential means that the potential of one electrode of the inter-wiring capacitances C1 and C2 connected to the wiring 21 changes. Therefore, the potential of the wiring 21 receives a change in the potential of the adjacent wiring (noise due to capacitive coupling of the adjacent wiring). This is because the larger the capacitance of the adjacent wiring where the potential changes, the greater the influence, and the other capacitance (bottom capacitance of the wiring itself,
The larger the input capacitance of each gate to which the wiring is connected), the less the effect. Further, in a semiconductor integrated circuit of CMOS, which has a large noise margin of an internal circuit, this is not a serious problem, but in an LSI such as an analog circuit or an ECL which is very sensitive to noise, a line between lines is Malfunction may occur due to noise due to capacitive coupling, and the capacitance between wiring increases as the wiring interval becomes smaller due to the adoption of a fine process, and the noise generated by capacitive coupling also increases, increasing the possibility of malfunction. .

As described above, when the wiring is miniaturized by the progress of the semiconductor manufacturing process, the following problems occur.

The ratio of the side capacitance to the wiring capacitance becomes large, and the wiring capacitance itself cannot be reduced.

As the side capacitance of the wiring increases, the equivalent wiring capacitance itself changes and the transmission time also changes.

There is a high risk of malfunction due to stronger capacitive coupling between wirings and larger noise generated.

The present invention has been made in view of the above-mentioned circumstances, and a wiring method of a semiconductor integrated circuit and a method for solving the problems in the above-mentioned conventional technique and achieving high speed and stable operation of the semiconductor integrated circuit. An object is to provide a semiconductor integrated circuit.

[0020]

According to the method of claim 1, a specific wiring, for example, a wiring having a long wiring length such as a bus line, a clock line, an analog signal line, or a predetermined wiring (called a critical path). To increase the distance between adjacent wiring.

In the method according to the second aspect, a specific wiring, for example, a wiring having a long wiring length such as a bus line, a clock line, an analog signal line, or a critical path is provided at a distance from an adjacent wiring. It is wider than the spacing between neighboring wirings, and its wiring width is the same as or wider than the width of the neighboring wiring and its neighboring wirings. Furthermore, the center-to-center distance between both neighboring wirings has the same value. It is determined by an integer for the wiring grid pitch of the wiring group and the adjacent wiring group on the other side.

Further, in the method according to the fourth aspect, the specific wiring is carried out in one layer of the laminated substrate constituting the semiconductor integrated circuit.

A semiconductor integrated circuit according to a fifth aspect of the invention is provided with a specific wiring manufactured by using the wiring method for a semiconductor integrated circuit according to any one of the first to fourth aspects.

[0024]

The capacitance between wirings is reduced by keeping a specific wiring having a long wiring length such as a bus line, a clock line, an analog signal line, or a critical path away from an adjacent wiring.

Therefore, since the capacitance between the wirings is reduced,
The influence of this is reduced, and the fluctuation of the transmission time and the generation of noise are suppressed.

Further, the above-mentioned specific wiring is wider than the wiring distance of the peripheral wiring in the distance from the adjacent wiring, and its wiring width is the same as or wider than the width of the adjacent wiring and the wiring in the periphery thereof. The center-to-center distance between adjacent two wirings is determined by an integer of the wiring grid pitch of the adjacent wiring group on one side and the adjacent wiring group on the other side having the same value.

Therefore, arranging the specific wiring by such a method can realize automatic wiring by CAD (Computer Aided Design) by a simple program.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of signal wiring according to an embodiment of the present invention. As shown in FIG. 1, the distance between the signal wiring 3 and the signal wirings 4 to 7 adjacent to the signal wiring 3 is different. Others are common to FIG. 3 described above.

That is, although the same first-layer signal wirings 4, 5, 6, and 7 are present adjacent to the signal wiring 3 on the upper and lower sides thereof, the signal wiring 3 and these signals The wiring distance between the wirings 4, 5, 6, and 7 is twice or more the distance between the signal wiring 6 and the signal wiring 8.

As the signal wirings such as the signal wirings 3 which need to be widened between the adjacent signal wirings, signal wirings having a long wiring length such as a bus line, a clock line and an analog signal line are targeted. In addition, a line pointed out by the user in advance (called a critical path) is also targeted. That is, generally, the distance between a specific wiring and an adjacent wiring is set to be wider than the distance between other wirings.

Since the above wiring has a virtual wiring grid in a gate array or the like which is automatically wired by CAD, it is efficient to perform the wiring on this wiring grid.

The example shown in FIG. 1 is an example in which the wiring grids on the upper and lower sides of the wiring 3 are not used and one wiring grid is vacant. In this way, if the wiring is done without using a specific wiring grid, the chip area will increase. However, since such a method is adopted only for the signal line for which the wiring capacitance is to be reduced, It does not expand the wiring pitch with respect to the wiring. Therefore, the increase in chip area can be minimized. Further, if there is a free space in another wiring area, the increase of the chip area can be minimized by moving the wiring adjacent to the wiring whose capacity is to be reduced in that area.

On the other hand, in FIG. 2, the distance between the centers of the wiring 3 and the wirings 4 and 5 is d1, the distance between the centers of the wiring 3 and the wirings 6 and 7 is d2,
The distance between the centers of the wirings 6 and 7 and the wiring 8 is d3, and d1 and d
2 is set to about 1.5 times d3 to make the wiring interval larger than other wirings. As a result, the inter-wiring capacitance of the wiring 3 in FIG. 2 can be suppressed small, and the total wiring capacity can also be suppressed small.

In the example of FIG. 2, the wiring interval is made smaller than that of the example of FIG. 1, so that the inter-wiring capacitance is somewhat increased, but the increase in the chip area can be suppressed to a small extent. Generally, a wiring grid such as a gate array is regularly arranged and C
For an LSI in which automatic wiring is performed by AD, it is preferable to use the above-described one-wiring grid space. On the other hand, the wiring grid pitch can be freely set in the manual design or the standard cell, and thus the method of FIG. 2 is suitable.

In the above embodiment, when applying the method shown in FIGS. 1 and 2, it is not possible to create some kind of program and automatically perform such wiring only for a specific wiring. It goes without saying that it is possible enough.

Here, a supplementary description will be given of a method of increasing the distance between the wirings for reducing the coupling capacitance between the wirings and a combination of wiring grids for automatic wiring by CAD.

In the wiring grid itself for automatic wiring, it is preferable that the pitch of the wirings, that is, the center-to-center distance between the wirings (one half of the sum of the wiring width and the wiring interval) follows a fixed rule. The example is an example in which one wiring grid is provided for the purpose of widening the wiring interval and maintaining the wiring pitch of the wiring grid itself constant. In this case, if the wiring widths are all the same, the wiring spacing increases by one wiring grid, that is, the wiring pitch when the wiring spacing is widened.

On the other hand, it is possible to maintain a constant wiring grid interval, open a wiring grid adjacent to a specific wiring to widen the wiring interval, and at the same time widen the wiring width of the specific wiring.

As described above, the influence of noise due to the capacitive coupling of the adjacent wiring is greater as the coupling capacitance of the adjacent wiring whose potential changes is larger, but other capacitances (bottom capacitance of the wiring itself, connection of the wiring). Even if the input capacitance of each gate is large), the effect is small. Therefore, in the embodiment of FIG. 1, at the same time as increasing the wiring interval by opening the adjacent wiring grids, all of the obtained increase in the wiring interval (one wiring grid interval) is used to reduce the coupling capacitance of the adjacent wirings. It is also possible to use it for widening a specific wiring width, instead of using it. By adopting such a method, the coupling capacitance of the adjacent wiring is reduced as compared with the conventional wiring method, and the bottom capacitance of the wiring itself is increased, so that the influence of noise due to the capacitive coupling of the adjacent wiring can be reduced. .

In this case, the total load capacitance does not reach the minimum value while maintaining the pitch of the wiring grid, but the influence of noise due to capacitive coupling of adjacent wirings should be reduced as compared with the case where the wiring grid is not opened. It is possible to reduce the resistance of the wiring itself.

Specifically, the total wiring length of a specific wiring is 20.
Considering the case of mm, when the wiring width is 1.2 μm, the resistance value is 5 mm assuming that the sheet resistance is 30 milliohm · mm.
Reach 00 ohms.

With such a resistance value, due to the existence of the time constant due to the wiring resistance and the wiring load capacitance, even if the driving impedance of the transistor for driving the wiring of the wiring is lowered, the signal delay time is reduced to a certain value or less. do not do. In this case, for example, by expanding the wiring width to 2.4 μm,
The resistance value of the wiring can be reduced by half. Even if the wiring bottom capacitance increases due to an increase in the wiring width, the signal delay can be reduced as a result by lowering the drive impedance of the transistor that drives the wiring as a signal.

Further, in the embodiment shown in FIG. 2, it is possible to apply the wiring grid in the automatic wiring in CAD. Although the wiring pitch is 1 and 1.5 in FIG. 2, this can be expressed by an integer ratio of 2 and 3 when 0.5 is taken as a unit. In this way, for a specific minimum unit, if the wiring pitch is an integer ratio,
In the application of automatic wiring, it is possible to create an appropriate program and automatically perform such wiring only for a specific wiring. It is also possible to use the method of increasing the width of the specific wiring in combination. Needless to say, when the wiring width is increased, it is not necessary to increase the wiring pitch from the center line to the both sides by the same amount.

Therefore, according to the present invention, the specific wiring is wider than the wiring spacing of the neighboring wiring in the spacing between the neighboring wiring and the specific wiring width is the same as that of the neighboring wiring or the wiring around the neighboring wiring. Wide and the wiring grid pitch determined by the adjacent wiring group on one side of the specific wiring is the same as the wiring grid pitch determined by the adjacent wiring group on the other side, and both adjacent to the specific wiring. If the distance between the centers of the wirings is arranged so as to be expressed by an integer corresponding to the integer of the wiring grid pitch, automatic wiring in CAD can be realized by a simple program creation.

Further, in the above-mentioned embodiment, the wiring of the first layer is explained, but this method can be applied to the multi-layer wiring of the second layer or three layers or more.

[0047]

As described above, according to the present invention, it is possible to reduce the wiring capacitance of a specific wiring without increasing the chip size so much, so that the operation speed of the circuit can be increased. Is obtained.

Further, by reducing the capacitance between the wirings, the capacitive coupling is weakened and the variation of the equivalent wiring capacitance is suppressed, so that the circuit can be stably operated.

Also, automatic wiring in CAD can be realized by a simple program creation.

[Brief description of drawings]

FIG. 1 is a plan view showing wiring according to the method of the present invention.

FIG. 2 is a plan view showing wiring according to the method of the present invention.

FIG. 3 is a plan view showing wiring according to a conventional method.

FIG. 4 is a plan view showing a wiring used for explaining a conventional problem.

FIG. 5 is a perspective view showing a wiring used for explaining a conventional problem.

FIG. 6 is a perspective view showing a wiring used for explaining a conventional problem.

FIG. 7 is an electrical equivalent circuit diagram in the wiring shown in FIG. 4 used for explaining a conventional problem.

[Explanation of symbols]

1, 2 cell area 3-8 First layer wiring 9-15 Second layer wiring

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a minimum distance between metal wires of 1.2 μm or less, wherein a distance between a specific wire and an adjacent wire is wider than a distance between other wires. Wiring method for integrated circuits. 2. A specific wiring is wider than a wiring distance of a peripheral wiring in a distance from the adjacent wiring, and a wiring width thereof is the same as or wider than a width of the adjacent wiring and a peripheral wiring thereof. Wiring of a semiconductor integrated circuit, characterized in that the center-to-center distance between both adjacent wirings is determined by an integer corresponding to an integer of the wiring grid pitch of the adjacent wiring group on one side and the adjacent wiring group on the other side having the same value. Method. 3. The wiring method for a semiconductor integrated circuit according to claim 1, wherein the specific wiring is a clock line, a bus line, an analog signal line, or a line designated in advance. . 4. The specific wiring is determined in relation to a wiring in one layer of a laminated substrate forming the semiconductor integrated circuit. The method for wiring a semiconductor integrated circuit according to the item. 5. A semiconductor integrated circuit comprising a specific wiring manufactured by using the wiring method for a semiconductor integrated circuit according to any one of claims 1 to 4.