JPH05326558A - Junction type field effect transistor - Google Patents

Abstract

PURPOSE:To prevent deterioration of characteristics of a junction type field effect transistor by suppressing formation of an inverted region on a gate region of the transistor due to atmospheric ions. CONSTITUTION:A P-type source region 4 and drain 5 are formed in space on an N-type epitaxial layer 3, and a P-type channel region 6, an N-type first gate region 7 and an N-type second gate region 10 having higher concentration and shallower depth than those of the first gate region are provided between the source and the drain regions. Even if negative ions in the atmosphere are collected on an insulating film 9, a P-type inverted layer is not formed on the region 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a junction field effect transistor (hereinafter abbreviated as a junction FET) which is resistant to surface inversion of a gate portion on a channel.

[0002]

2. Description of the Related Art An example of a conventional junction type FET of this type is shown in FIG. The same figure (a) is a top view and the same figure (b) is B-.
It is a B line sectional view. As shown in the figure, an N-type buried layer 2 is selectively formed on a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is formed on the P-type semiconductor substrate 1 including the N-type buried layer 2. Are formed. Further, a P-type source region 4 and a P-type drain region 5 are formed separately on the surface of the N-type epitaxial layer 3 immediately above the N-type buried layer 2.
A P-type channel region 6 and an N-type gate region 7 are formed between the P-type source region 4 and the P-type drain region 5. Further, an oxide film 9 is formed on the surface as an insulating film.

[0003]

In such a conventional junction type FET, the P type source region 4 and the P type drain region 5 are provided.
FIG. 3 shows the charge distribution in the vicinity of the N-type gate region 7 between the regions 4 and 5 when the voltage between them is increased.
In this way, when the voltage between the P-type source region 4 and the P-type drain region 5 is increased, the negative ions 11 in the atmosphere are collected on the oxide film 9 on the P-type channel region 6,
Positive charge 12 is applied to the P-type channel region 6 that performs the original current path.
Was accumulated, and the surface of the N-type gate region 7 became the P-type inversion region 13 in addition to the channel region 6, and the original characteristics of the junction FET were impaired. An object of the present invention is to provide a junction-type FET that suppresses the occurrence of such an inversion region in the gate region and prevents the deterioration of the characteristics of the junction-type FET.

[0004]

According to the present invention, a source region and a drain region of a second conductivity type are formed separately in a semiconductor layer of a first conductivity type, and a channel region of the second conductivity type is provided between these source and drain regions. A first gate region of the first conductivity type,
The second gate region of the first conductivity type has a higher concentration and is shallower than the first gate region.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which (a) is a plan view and (b) is a sectional view taken along the line AA. As shown in the figure, the P-type semiconductor substrate 1 of 1 to 3 Ω · cm has 15 to 30 Ω /
The N type buried layer 2 of □ is formed, and 1 to 5 are formed on the N type buried layer.
An N-type epitaxial layer 3 of Ω · cm is formed, and the epitaxial layer 3 has a thickness of 100 to 300Ω / on the N-type buried layer 2.
The P type source region 4 and the P type drain region 5 of □ are formed with a junction depth of 2 to 3 μm. Between the P-type drain region 5 and the P-type source region 4, a P-type channel region 6 having a depth of about 0.25 μm, an N-type first gate region 7 having a depth of about 0.1 μm, and a depth of 0.05 μm N-type second gate region 1
0 is formed.

To form these regions, the P-type channel region 6 has an energy of 1 to 100 from a thin thermal oxide film 9 of 100 to 300 Å.
Boron is ion-implanted at 00 KeV and a dose amount of 5 to 10 × 10 ¹¹ atoms / cm ² , and the N-type first gate region 7 has an energy of 50.
KeV, a dose of 1 to 5 × 10 ¹² atoms / cm ² of phosphorus is ion-implanted, and the N-type second gate region 10 has an energy of 20K.
It is formed by ion-implanting phosphorus with eV and a dose of 1 × 10 ¹⁴ atoms / cm ² . Further, contact holes for the source, drain and gate are formed in the thermal oxide film 9,
An aluminum electrode 8 is formed on each contact.

According to this structure, the P-type source region 4 and the P-type source region 4 are
Since the gate region between the type drain regions 5 is composed of the N-type first gate region 7 and the N-type second gate region 10 having a higher concentration and a shallower concentration than the first gate region, the N-type first gate region 7 and the N-type second gate region 10 are exposed to the atmosphere above the oxide film 9. Even if the negative ions are collected, the high concentration N-type second gate region 10 prevents P inversion of the gate region. Therefore, the original characteristics of the junction FET are not impaired.

[0008]

As described above, according to the present invention, the channel region between the source region and the drain region is provided with the first gate region and the second gate region having a higher concentration and a shallower concentration than the first gate region. This has the effect of preventing inversion of the gate region and preventing characteristic deterioration.

[Brief description of drawings]

FIG. 1 shows an embodiment of a junction type FET of the present invention,
(A) is a top view, (b) is a sectional view on the AA line.

2A and 2B show an example of a conventional junction FET, FIG. 2A is a plan view, and FIG. 2B is a sectional view taken along line BB.

FIG. 3 is a cross-sectional view for explaining an inverted state of a gate region in a conventional junction FET.

[Explanation of symbols]

 1 P-type semiconductor substrate 3 N-type epitaxial layer 4 P-type source region 5 P-type drain region 6 P-type channel region 7 N-type first gate region 10 N-type second gate region

Claims (1)

[Claims] 1. A first-conductivity-type semiconductor layer is formed with a second-conductivity-type source region and a drain region separated from each other, and a second-conductivity-type channel region is provided between the source / drain regions.
A junction-type field effect transistor comprising: a first gate region of a conductivity type and a second gate region of a first conductivity type having a higher concentration and a shallower concentration than the first gate region.