JPH05327480A - Synchronizing counter - Google Patents

Abstract

PURPOSE:To provide a synchronizing counter which eliminates the spike noises out of the ripple carry output and also attains a high speed operation. CONSTITUTION:A 1st flip-flop circuits 2, 4, 6 and 8 are cascaded at plural stages, and a 2nd flip-flop circuit 10 is provided to the circuit 8 of the final stage. When the output of the circuit 2 of the first stage is kept at a low level with the output of the circuits 4-8 kept at a high level respectively, each output of circuits 2-8 defined as the data input of the circuit 10. Thus the carry output is obtained from the circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous counter used for counting pulses in a general-purpose IC or ASIC.

[0002]

2. Description of the Related Art Conventionally, for example, a synchronous counter having a logic circuit shown in FIG. 7 has been used.
This synchronous counter is composed of four sets of flip-flop circuits F1, F2, F3, F4, etc., and has a clock input T, a direct connection reset input R, a load input LOAD, enable inputs EP and ET, and data inputs DA and DB. , D
Outputs QA, QB, QC, QD and carry output RCO are taken out for C and DD. The operation timing of these inputs and outputs is shown in FIG.

[0003]

By the way, in this synchronous counter, spike noise leaks to the ripple carry output RCO in addition to the regular pulse, and if this ripple carry output RCO is used for the clock of the D-flip-flop circuit, etc., It may malfunction. The limit of the operating clock is determined by the cascade output of the counter.

Therefore, an object of the present invention is to provide a synchronous counter which eliminates spike noise contained in the ripple carry output and realizes high speed operation.

[0005]

That is, the synchronous counter of the present invention comprises a first flip-flop circuit (2, 4, 6, 8) formed by cascade-connecting a plurality of stages, and the first flip-flop. A second flip-flop circuit (10, JK flip-flop circuit 11) is installed on the output side of the flip-flop circuit on the final stage side of the circuit, and the output of the first-stage side of the first flip-flop circuit is low level and the other. Of the first
When the output of the flip-flop circuit is high, the carry output is obtained from the second flip-flop circuit by making each output of the flip-flop circuit the data input of the second flip-flop circuit. And a synchronous counter.

[0006]

In this synchronous counter, a carry output is obtained when all the outputs of the first flip-flop circuit shift to the high level. That is, when the output of the first-stage side of the first flip-flop circuit is at the low level and the output of the other first flip-flop circuit is at the high level, each output of the flip-flop circuit is used as the data input of the second flip-flop circuit. By doing so, when all the outputs of the first flip-flop circuit shift to the H level at the next timing,
The data input of the flip-flop circuit is latched, and a carry output without spike noise is obtained from the second flip-flop circuit as in the normal ripple output.

[0007]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 shows an embodiment of the synchronous counter of the present invention. This synchronous counter has a plurality of first
The second flip-flop circuit 10 is installed together with four sets of flip-flop circuits 2, 4, 6 and 8 as the flip-flop circuits of
The clock signal CLK is applied to the clock input C of 0 via the buffer 12. Also, each reset input R
Is applied after the reset signal RDB is inverted by the inverter 14.

The exclusive OR 16 is provided on the data input D side of the flip-flop circuit 2, and the exclusive NOR 1 is provided on the data input D side of the flip-flop circuits 4-8.
8, 20, 22 are installed. Exclusive O
The enable signal ENP and the output Q of the flip-flop circuit 2 are added to R16, and the output Q is added to the data input D of the flip-flop circuit 2.

Exclusive NOR 18-22
NAND circuits 24, 2 are provided on one input side of each of
6, 28 are installed. The enable signal ENP and the output Q of the flip-flop circuit 2 are added to the NAND circuit 24, and the enable signal ENP is supplied to the NAND circuit 26.
And the outputs Q of the flip-flop circuits 2 and 4 are added, and the enable signal EN is applied to the NAND circuit 28.
P and the outputs Q of the flip-flop circuits 2, 4 and 6 are added.

The output of the NAND circuit 24 and the output Q of the flip-flop circuit 4 are applied to the exclusive NOR 18, and the output thereof is applied to the data input D of the flip-flop circuit 4. Further, the output of the NAND circuit 26 and the output Q of the flip-flop circuit 6 are exclusive N
It is applied to the OR 20 and its output is applied to the data input D of the flip-flop circuit 6. Further, the output of the NAND circuit 28 and the output Q of the flip-flop circuit 8 are added to the exclusive NOR 22, and the output thereof is added to the data input D of the flip-flop circuit 8.

As described above, the exclusive OR 16, the exclusive NORs 18 to 22, and the NAND circuit 24 are provided.
28 to 28, the flip-flop circuits 2 to 8 are cascaded, and the outputs of the flip-flop circuits 2 to 8 are inverted by the inverters 32, 34, 36 and 38 to output Q.
Taken out as A, QB, QC, QD, and N
It is applied to the data input D of the flip-flop circuit 10 via the OR circuit 40, and the carry output RC is taken out from the flip-flop circuit 10.

In the above configuration, the operation will be described with reference to FIG. 2. The clock signal CLK shown in A of FIG. 2, the reset signal RDB shown in B of FIG. 2 and the enable signal ENP shown in C of FIG. Then, as shown in D to G of FIG. 2, outputs QA to QD representing counter outputs are obtained,
Further, as shown by H in FIG. 2, the flip-flop circuit 1
The carry output RC is obtained through 0.

As is clear from this operation timing,
In this synchronous counter, the flip-flop circuits 2-8
Carry output R when all outputs go to high level
C is obtained. That is, when the output of the flip-flop circuit 2 is low and the outputs of the flip-flop circuits 4 to 8 are high, the outputs of the flip-flop circuits 2 to 8 are used as the data input D of the flip-flop circuit 10. When all the outputs of the flip-flop circuits 2 to 8 shift to the H level at the timing of, the data input D of the flip-flop circuit 10 enters the latch state, and spike noise, that is, a carry output without a hazard is generated as in the normal ripple output. RC can be obtained from the flip-flop circuit 10 and the operation speed can be increased.

Next, FIGS. 3 and 4 show another embodiment of the synchronous counter of the present invention. In the synchronous counter shown in FIG. 3, the NOR circuit 40 of the synchronous counter shown in FIG. 1 is changed to a 6-input one, and an enable signal ENP is added to the NOR circuit 40 via an inverter 42. It was done. With such a configuration, it is possible to realize the same operation at the same operation timing as that of the above embodiment. Even with such a synchronous counter, a carry output RC without a hazard is generated.

Further, in the synchronous counter shown in FIG. 4, a NOR circuit 41 is provided side by side with the NOR circuit 40 of the synchronous counter shown in FIG. 3, and an inverter 42 is provided in this NOR circuit 41.
Enable signal ENP via the flip-flop circuit 2 on the input side of the inverters 32-38.
8 outputs, take the NOR output,
A JK flip-flop circuit 11 is installed as a second flip-flop circuit on the output side of the OR circuits 40 and 41. Input J of this JK flip-flop circuit 11
The output of the NOR circuit 40, the input K thereof is the output of the NOR circuit 41, and the input CP thereof is the clock signal CLK, so that the output Q thereof is used as a carry output RC. Then, the carry output RC and the enable signal ENP are applied to the NAND circuit 44, and the output is inverted by the inverter 46 to obtain the output RCB. Even with such a synchronous counter, a carry output RC without a hazard is generated.

Next, FIGS. 5 and 6 show an application example using the synchronous counter of the present invention. That is, FIG. 5 shows a synchronous counter which is cascade-connected using the synchronous counter 50 shown in FIG. 1, FIG. 2 or FIG. By supplying the clock signal CLK and the reset signal RST and using the power supply voltage V _CC as the enable signal ENP,
Outputs A0 to A7 can be taken out, and hazard-free carry outputs CRO1 and CRO2 can be taken out individually through each synchronous counter 50.

Further, FIG. 6 shows a digital mono-multivibrator using a synchronous counter 50. That is, the carry output RCO obtained by the synchronous counter 50
Is inverted through an inverter 52, the inverted carry output RCO is added to a clock signal CLK to an AND circuit 54 to perform a logical product, and the output is used as a clock input CLK of the synchronous counter 50. With such a configuration, it is possible to configure a digital mono-multivibrator using a synchronous counter, and it is possible to obtain high-speed output without a hazard.

[0019]

As described above, according to the present invention,
The spike noise can be removed, the speed can be increased, and the ripple carry output can be applied as a clock to various logic circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous counter of the present invention.

FIG. 2 is a timing chart showing an operation of the synchronous counter shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the synchronous counter of the present invention.

FIG. 4 is a block diagram showing another embodiment of the synchronous counter of the present invention.

5 is a block diagram showing a cascade connection of the synchronous counters shown in FIG. 1. FIG.

FIG. 6 is a block diagram showing a digital mono-multivibrator using the synchronous counter of the present invention.

FIG. 7 is a circuit diagram showing a logic circuit of a conventional synchronous counter.

8 is a timing chart showing the operation of the synchronous counter of FIG.

[Explanation of symbols]

2, 4, 6, 8 First flip-flop circuit 10 Second flip-flop circuit 11 JK flip-flop circuit (second flip-flop circuit)

Claims (1)

[Claims] 1. A plurality of first flip-flop circuits provided side by side, and a second flip-flop circuit provided on the output side of the flip-flop circuit on the final stage side of the first flip-flop circuit, When the output of the first flip-flop circuit on the first stage side is low level and the output of the other first flip-flop circuit is high level, each output of the flip-flop circuit is used as the data input of the second flip-flop circuit. By doing so, a carry output is obtained from the second flip-flop circuit.