JPH0532941B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to demodulation of an MSK signal in which the center of demodulated data can always be identified regardless of the phase of a signal with a frequency of 1/2 of a reproduced clock. Regarding equipment.

[Technical background of the invention and its problems]

The MSK signal is a digital signal modulation method in which the phase changes by +π/2 or -π/2 during one symbol (T seconds), and the carrier phase between each symbol is continuous, so it has a constant envelope (Constant envelope). Euvelope) and is known as a method with a high concentration of signal spectrum.

As demodulation methods for MSK signals, (a) MSK signals are considered to be a type of FSK signal, so demodulation is performed using an FM detector; (b) phase is +π/2 or -π during one symbol. /2
A simple method is a delayed detection method in which the preceding symbol is delayed by one symbol time T by taking advantage of this change, then shifted by 90 degrees and multiplied. Although the above two methods simplify the demodulation device, they have the disadvantage that the bit error rate for the same C/N is worse than the synchronous detection method in which the demodulation device regenerates the carrier wave and performs synchronous detection.

The method for regenerating the carrier wave on the demodulator side is as follows:
As shown in Figure 1, QPSK (Quadrature Phase
Shift Keying) Similar to the demodulator, a method of multiplying the input signal by 4 and removing the influence of the modulation signal is considered.

That is, the input signal 1 is input to the clock regeneration circuit 2, which reproduces the 1/THz clock and inputs it to the 1/4 divider circuit 3, where the frequency is divided to 1/4 and output 3a with no phase shift is generated. is sent to the integral discrimination circuit 4, and an output 3b whose phase has been shifted by 90 degrees is sent to the integral discrimination circuit 5.

In addition, the input signal 1 is input to the 4 in the carrier regeneration circuit 6.
The signal is input to a multiplier 6a and multiplication circuits 7 and 8.
The input signal 1 input to the quadruple multiplier 6a is multiplied by four in frequency and sent to the multiplication circuit 6b.

The multiplication circuit 6b multiplies the output signal of the oscillator 6d and inputs the multiplied signal to the low-pass filter 6c.The low-pass filter 6c passes the low-frequency region components to drive the oscillator 6d, and the output of the oscillator 6d is divided by 1/ The frequency is divided into 1/4 by the 4 frequency divider circuit 6e. The output 6 _e1 of the frequency dividing circuit 6e is sent as it is to the multiplication circuit 7, and is also outputted to the multiplication circuit 8 after its phase is shifted by 90° through a 90° phase shifter 9.

Multiplication circuit 7 is input signal 1 and 1/4 frequency division circuit 6e
The multiplication circuit 8 multiplies the input signal 1 by the output of the 90° phase shifter 9 and outputs the result to the integral identification circuit 5.

The integral identification circuit 4 identifies the integral state from the output 3a of the 1/4 frequency dividing circuit 3 and the output of the multiplication circuit 7, and outputs demodulated data. Similarly, the integral identifying circuit 5 identifies the integral state from the output of the multiplication circuit 8 and the output 3b of the 1/4 frequency dividing circuit 3, and outputs demodulated data.

The MSK demodulation method shown in FIG. 1 has the disadvantage that the symbol timing of the two-axis synchronous detection output and the identification clock timing are not synchronized because the recovered carrier and recovered clock are generated independently.

That is, as shown in the signal generation process of FIG. 3, the MSK signal is the input signal 1 of synchronization T in FIG. 3a.
In contrast, the data timings of the I and Q axes shown in FIGS. 3b and 3c, respectively, are shifted by Tsec.
Which of the I and Q axis data on the transmitting side is the demodulation axis 1,
What appears in 2 is the regenerated carrier wave (Fig. 3 d, 3
It cannot be determined because it is determined by the phase in Figure e).

Therefore, the demodulation method shown in FIG. 1 has the disadvantage that the timing relationship between the demodulated data and the identification clock cannot be limited to 1:1.

As a method for eliminating this drawback, a method can be considered in which the clock component is extracted from the synchronous detection output, as shown in FIG.

In the case of FIG. 2, the input signal 1 is the output of the 1/4 frequency dividing circuit 6e of the carrier regeneration circuit 6 similar to that in FIG.
The signal is sent to the multiplication circuit 8 through the multiplication circuit 8. Multiplication circuit 7 is 1/
The output of the 4-frequency divider circuit 6e is multiplied by the input signal 1, and the result is sent to the integral discrimination circuit 4.

The multiplication circuit 8 multiplies the input signal 1 and the output of the 90° phase shifter 9 and sends the result to the integral discrimination circuit 5.

Also, the output of the multiplication circuit 7 is the clock regeneration circuit 1.
0 is input to the amplitude discrimination circuit 10a, where the amplitude is discriminated and outputted to the multiplication circuit 10b. The multiplier circuit 10b multiplies the output of the oscillator 10d by a signal frequency-divided by the 1/2 frequency divider circuit 10e, and drives the oscillator 10d through the low-pass filter 10c.
The output of this oscillator 10d is sent to a 1/4 frequency divider circuit 11, where the frequency is divided into 1/4.

The output of the 1/4 frequency divider circuit 11 is sent as is to the integral discrimination circuit 4 without phase shifting, and
The 90° phase-shifted output is sent to the integral discrimination circuit 5. The integral discrimination circuit 4 is the output of the multiplication circuit 7 and 1/4
The integral identification circuit 5 identifies the integration state based on the output of the frequency dividing circuit 11, and the output of the multiplication circuit 8 and the output of the 1/4 frequency dividing circuit 11, respectively.

In this case, if the recovered carrier wave causes a cycle slip due to the influence of noise, the demodulated data timing will change.
Due to the Tsec shift, the clock regeneration circuit 10 becomes out of synchronization, during which burst errors occur.

Therefore, as a demodulator for MSK signals, there are two methods: (a) a method in which the phase of the regenerated clock is controlled by the phase of the regenerated carrier; (b) a method in which the phase of the regenerated carrier is controlled by the phase of the regenerated clock. .

A typical example of the former is shown in FIG. This demodulation method is known as an application of the demodulation method devised by Sunde as a demodulation method for FSK signals with a modulation index of 1.

In this Figure 4, the input signal is input to the multiplier circuit 1.
2. Input to multipliers 13 and 14, double the frequency of the input signal in multiplier circuit 12, and send to (2πfc + 1/2T) Hz phase synchronization circuit 15 and (2πfc - 1/2T) Hz phase synchronization circuit 16, respectively. It is input and phase-synchronized with the frequencies of (2πfc + 1/2T) Hz and (2πfc - 1/2T) Hz, and sent to frequency divider circuits 17 and 18, where the frequency is divided into 1/2, and then added to adders 19 and 18, respectively. 20 and multiplier 21
Output to.

The frequency divider circuit 17 outputs signals of the same phase, and the frequency divider circuit 18 outputs signals of mutually opposite phases. As a result, the adder 19 adds the outputs of the frequency dividing circuits 17 and 18 and outputs the result to the multiplier 13, and the adder 20 subtracts the output of the frequency dividing circuit 18 from the output of the frequency dividing circuit 17 and outputs the result to the multiplier 14. Output.

Multiplier 13 multiplies the output of adder 19 and the input signal to integrate, sample and dump circuit 2
The multiplier 14 multiplies the output of the adder 20 by the input signal and outputs the result to the integration, sampling and dumping circuit 23.

On the other hand, the multiplier 21 adds the outputs of both the frequency dividing circuits 17 and 18, inputs the result to the low-pass filter 24, extracts the low frequency component there, and then sends the clock to the integration, sampling and dumping circuit 23 through the OR element 25. At the same time, using the inverted signal of the low-pass filter 24 as a clock,
Output to integration, sampling and dump circuit 22.

Integration, sampling and dump circuit 22,2
3 are multipliers 13 and 14 based on the clock, respectively.
The output is integrated, sampled, and dumped, and sent to differential amplification and decoding circuits 26 and 27, where it is decoded, and then a serial demodulated signal is obtained from a parallel-to-serial conversion circuit 28.

This carrier-dependent MSK demodulation method requires two phase-locked loops at high frequencies, as well as doubling and dividing-by-2 circuits at the high-frequency stage, which has the disadvantage that the device becomes complicated and expensive.

[Purpose of the invention]

The present invention has been made to eliminate the drawbacks of the above-mentioned conventional methods, and an object of the present invention is to provide an MSK signal demodulation device with a simple configuration and high performance.

[Summary of the invention]

The MSK signal demodulation device of the present invention extracts the modulation component of the MSK signal, regenerates the recovered clock signal, extracts the low-frequency components of the outputs of two orthogonal synchronous detectors using a low-pass filter, and then converts the modulation components of the MSK signal into an exclusive logic A signal component that is a function of the phase difference between the frequency of the input signal and the recovered carrier wave is generated by calculating the sum and exclusive ORing the output with a signal of 1/2 period of the recovered clock signal, and this phase error A regenerated carrier wave is generated by controlling the phase of the oscillation output of the voltage controlled oscillator using a control voltage that is a function of At the same time, the outputs of the two multipliers are identified by clock signals with different polarities at half the frequency of the reproduced clock signal.
It is designed to demodulate the digital data of each orthogonal axis of the MSK signal.

[Embodiments of the invention]

Embodiments of the MSK signal demodulation device of the present invention will be described below with reference to the drawings. FIG. 5 shows an MSK modulator that extracts the modulation component of the MSK signal input to the MSK signal demodulation device of the present invention.Before explaining the demodulation device of the present invention, the MSK modulator will be briefly explained. .

In FIG. 5, when an input signal is input to a serial/parallel converter 31, serial data is converted into parallel data and sent to differential encoders 32 and 33. Differential encoders 32 and 33 encode parallel data to generate orthogonal I-axis and Q-axis digital data I.
(t) and Q(t) are output to multipliers 34 and 35.

Further, the clock signal is input to the phase synchronized oscillator 36, and the clock signal sinπt/2T synchronized with this clock signal is generated from the phase synchronized oscillator 36 and sent to the multiplier 34.
7, where the clock signal cosπt/2T is shifted in phase by 90° and sent to a multiplier 35.

The multiplier 34 multiplies the output I(t) of the differential encoder 32 by the clock signal sinπt/2T, and outputs the result I (t)·sinπt/2T to the multiplier 38. Similarly, the multiplier 35 multiplies the output Q(t) of the differential encoder 33 by the clock signal cosπt/2T, and outputs the result Q(t)·cosπt/2T to the multiplier 39.

A carrier wave (hereinafter referred to as carrier) sinω ₀ t with an angular frequency ω ₀ is sent to the multiplier 38 from a carrier oscillator 40 , and a 90° phase shifter 41 is also sent to the multiplier 38 .
carrier cosω ₀ t by shifting the phase by 90° through
is generated and this carrier cosω ₀ t is added to the multiplier 39.
Output to.

The multiplier 39 multiplies the carrier sinω ₀ t by the output I(t) of the multiplier 34, sinπt/2T, calculates I(t)・sin πt/2T・sinω ₀ t, and sends it to the adder 42. Output.

Similarly, the multiplier 39 multiplies the carrier cosω ₀ t by the output Q(t)・cosπt/2T of the multiplier 35, calculates I(t)・cosπt/2T・cosω ₀ t, and adds it. Add to bowl 4 2.

An adder 42 adds the outputs of both multipliers 38 and 39, and a bandpass filter 43 generates a modulated signal I(t)·sin of the MSK signal in a predetermined frequency band.
Outputs πt/2T・sinω ₀ t+Q(t)cosπt/2T・cosω ₀ t.

This modulated signal I(t)・sinπt/2T・sinω ₀ t+Q(t)・cosπt/2T・cosω ₀ t is input to the demodulator of the first embodiment of the present invention shown in FIG. 6 as an input of an MSK signal. This becomes the signal S(t).

This input signal S(t) is expressed as the following equation (1) similar to the above.

S(t)=I(t)・sinω ₀ t・sinπt／2T+Q(t)・cosω ₀ t
-cosπt/2T...(1) In this equation (1), ω ₀ is the carrier angular frequency (rad/sec), and T is the data length (sec). In FIG.
The signal is input to a bandpass filter 52a of the clock signal generation circuit.

The output of the bandpass filter 52a of the carrier phase locked loop 52 is subjected to envelope detection by an envelope detector 52b to extract the modulation component of the MSK signal.
The output thereof is sent to a synchronous detector 52c. The synchronous detector 52c receives an output from a voltage controlled oscillator 52e (hereinafter referred to as VCO) through a low-pass filter 52d, and the output of the low-pass filter 52d causes the synchronous detector 52c to detect the envelope. The output of the detector 52b is synchronously detected and the output is applied to the VCO 52e.

The oscillation frequency of the VCO 52e is controlled by the output of the synchronous detector 52c.
The output of VCO52e is passed through the 1/2 frequency divider circuit 53.
A timing determiner 57 is passed through a 90° phase shifter 54, a timing determiner 56 (consisting of a D-flip-flop), and a polarity inverter 55.
(Constructed by D-flip-flop)
It is now being sent to

In addition, the output of the 1/2 frequency divider 53 is the 1/2 frequency divider 5
8, the signal is sent to a 90° phase shifter 59 and a multiplier 60.

The output of the 90° phase shifter 54 is sent to a multiplier 61, and the output of the 90° phase shifter 59 is sent to a multiplier 62.
The multiplier 61 is connected to the output of the 90° phase shifter 54 and the multiplier 63
The signal is multiplied by the output of , and the result is output to the VCO 65 through a low-pass filter 64.

The VCO 65 controls the oscillation frequency by the output voltage of the low-pass filter 64 and outputs it to the synchronous detector 50 as well as to the synchronous detector 51 through the 90° phase shifter 66.

The synchronous detector 50 performs synchronous detection of the input signal S(t) using the output of the VCO 65, outputs the output to a low-pass filter 67, and outputs the output of the low-pass filter 67 to multipliers 60 and 63. There is.

Further, the synchronous detector 51 synchronously detects the input signal S(t) using the output of the 90° phase shifter 66 and outputs the output to the low-pass filter 68.
The output of this low-pass filter 68 is transmitted to a multiplier 62,
63.

The multiplier 60 is connected to the output of the low-pass filter 67 and 1/
The multiplier 62 multiplies the output of the frequency divider 68 by the output of the 90° phase shifter 59 and outputs the result to the timing judge 57. is performed and output to the timing determiner 56.

The timing determiner 57 determines the output timing of the multiplier 66 based on the output of the polarity inverter 55, and outputs a demodulated signal of I-axis digital data orthogonal to the MSK signal. Similarly, the timing determiner 51 uses a 1/2 frequency divider circuit 53.
Based on the output of the multiplier 62, the timing of the output of the multiplier 62 is determined and a demodulated signal of Q-axis digital data orthogonal to the MSK signal is output.

Next, the present invention configured as described above will be described.
The operation of the MSK signal demodulator will be explained.
In the input signal S(t) shown in equation (1), I(t), Q(t)
is a coefficient determined by the state of the data signal on the transmitting side and takes a value of "+1" or "-1". This I(t),
FIG. 7 shows the timing relationship between Q(t), sinπt/2T, and cosπt/2T.

As can be seen from Fig. 7, I(t) (Fig. 7 a) has symbol change points at 0, 2T, 4T, ... 2NT (N is an integer), and as shown in Fig. 7 b. , Q(t) has symbol change points at T, 3T, . . . (2N+1)T (N is an integer).

The input signal S(t) is distributed to three outputs by a distributor (not shown). One of its outputs is supplied to a narrowband bandpass filter 52a. The narrowband bandpass filter 52a has a passband width equal to the input signal S(t).
It is a band filter narrower than the transmission bandwidth of . Therefore, an envelope change corresponding to the modulation component occurs in the output of the bandpass filter 52a. The envelope detector 52b is a circuit that detects the changing component, and its output is supplied to the synchronous detector 52c.

The synchronous detector 52c, VCO 52e, and low-pass filter 52d form a phase-locked loop 52, which generates a recovered clock signal f(t) (FIG. 7e) synchronized with the modulation clock component of the input signal S(t). From equation (1), the reproduced clock signal f(t) can be expressed as follows.

f(t)=sin2πt/T (2) This phase-locked loop 52 operates as a clock signal regeneration circuit. Regenerated clock signal f(t) is 1/2
The signal is supplied to the frequency dividing circuit 53. In the case of digital signals, the 1/2 frequency divider circuit 53 can be easily constructed with a flip-flop circuit.

The output signal g(t) (FIG. 7f, FIG. 7g) of this 1/2 frequency divider circuit 53 is divided into two signals as shown in the following equations (3) and (4) depending on the initial operating state of the circuit. (i.e., with an uncertainty of 180°).

g(t)=+sinπt/T or −sinπt/T...(3) Also, by passing the output g(t) of this 1/2 frequency divider 53 through a 90° phase shifter 54, the output h( t) becomes as shown in equation (4).

h(t)=+cosπt/T or −cosπt/T (4) Therefore, the circuit operating state will be explained for the following two states.

(A) When g(t)=+sinπt/T (h(t)=+cosπt/T), the departure R ₁ (t) of the VCO 65 is defined as follows.

R ₁ (t)=sin(ω ₀ t+) (5) In this equation (5), is the phase difference between the carrier of the input signal S(t) and the output R ₁ (t) of the VCO 65.

At this time, the output a ₁ (t) of the synchronous detectors 50 and 51,
a ₂ (t) is given by the following formula.

a ₁ (t)=S(t)×sin(ω ₀ t+)……(6) a ₂ (t)=S(t)×cos(ω ₀ t+)……(7) This synchronous detector 50, 51 output signal a ₁ (t),
a ₂ (t) is applied to low-pass filters 67 and 68, respectively. The low-pass filters 67 and 68 remove high-frequency carriers and their harmonic components, and their outputs b ₁ (t) and b ₂ (t) are expressed by the following equations, respectively.

b ₁ (t)=2/1 {I(t)・sinπt／2T・cos＋Q(t)・co
sπt/2T・sin}……(8) b ₂ (t)=2/1{−I(t)・sinπt/2T・cos+Q(t)・
cosπt/2T・sin}...(9) Output signal of these low-pass filters 67 and 68
b ₁ (t) and b ₂ (t) are each applied to a multiplier 63 and multiplied. The multiplier 63 can be an analog type multiplier or can be realized by an exclusive OR circuit by converting the output signals b ₁ (t) and b ₂ (t) into digital signals. The output c(t) of this multiplier 63 is given by the following equation from equations (8) and (9) above.

c(t)=b ₁ (t)×b ₂ (t)=1/8Msin(πt/T+) ...(10) However, in this equation (10), M is a newly introduced coefficient, and the following Defined by equations (11) and (12).

M=I(t)×Q(t)=+1, (I(t)=Q(t))
...(11) M=I(t)×Q(t)=-1, (I(t)≠Q(t))
...(12) The output signal c(t) of the multiplier 63 is the output signal c(t) of the multiplier 61.
and the output signal g(t) of the 1/2 frequency divider circuit 53
is multiplied by the output signal h(t) whose phase is shifted by 90 degrees by the 90 degrees phase shifter 54. Like the multiplier 63, the multiplier 61 may be of either an analog type or a digital type. The output signal d(t) of this multiplier 61 is expressed in (3) above.
From equation (10), d(t)=c(t)×h(t)=1/16Msin (2πt/T+2M)
It is expressed as +16sin2...(13). The output signal d(t) of this multiplier 61
is sent to a low pass filter 64. The low-pass filter 64 removes the clock frequency component, and its output signal e(t) is given by equation (13) as follows.

e(t)=1/16sin2...(14) The output signal e(t) of the low-pass filter 64 is
Since it is applied to the VCO 65 and is supplied as a control voltage for the VCO 65, as a result, the part (52) surrounded by the dashed line in FIG. 6 operates as a carrier phase locked loop.

The stable point of this carrier phase locked loop 52 is e
(t)=0, which is the point where the differential coefficient e'(t) of e(t) becomes positive. Therefore, from equation (14), sin2=0, that is, =Nπ (N=0, 1, 2...)
...(15).

That is, this carrier phase synchronized rape 52 has only two stable points (0, π), whereas the four-phase PSK has four stable points. This is because the carrier phase locked loop 52 is controlled by the reproduced clock signal.

By substituting equations (8) and (9) into equation (15), the output signals b ₁ (t) and b ₂ (t) of the low-pass filters 67 and 68 can be expressed as follows.

b ₁ (t)=±1/2I(t)sinπt/2T, b ₂ (t)=±1/2Q(
t)cosπt/2T...(16) On the other hand, the output signal j(t) of the 1/2 frequency divider circuit 58 is (3)
From the formula, i(t)=±sinπt/2T...(17). Therefore, the output signal k(t) of the 90° phase shifter 59 is k(t)=±cosπt/2T (18). Therefore, the output signals of multipliers 60 and 62 l ₁ (18)
(Figure 6(h)), l ₂ (18) (Figure 6i) is equation (16), equation (18),
From the following equations (19) and (20), l ₁ (t)=±1/2I(t)sin ² πt/2T=±1/4I(t)(1
−cosπt/T)……(19) l ₂ (t)=±1/2Q(t) cos ² πt/2T=±1/4Q(t)(1
+cosπt/T...(20).

Output signals l ₁ (t), l ₂ (t) of the multipliers 60 and 62
As shown in Figure 7, the timing relationship of the output signal l ₁ (t) is at t=T, 3T...(2N-1)T is the center of the data, while the output signal l ₂ (t) is at t =
0.2T...2NT is the center of the data.

(B) When g(t)=-sinπt/T (h(t)=-cosπt/T) In this case, up to the output signal c(t) of the multiplier 63
Same as case (A). The output signal d(t) of the multiplier 61 is expressed as follows.

d(t)=1/8Msin(πt/2+)×{−sinπt/2}
=-1/16Msin(2πt/T+M)-1/16sin2...
(21) Therefore, the output signal e(t) of the low-pass filter 64 is given as follows.

e(t)=-1/16sin2...(22) Therefore, from equation (22), the stable point of the carrier phase-locked loop 62 in case (B) is =(+1/2)π(N=0, 1, 2...) ...(23)

That is, in case (B), the stable points of the carrier phase locked loop are two points (π/2, 3/2π), which are different from those in case (A).

Substituting equation (23) into equations (8) and (9), b ₁ (t)=±Q(t)・cosπt／2T……(24) b ₂ (t)=±I(t)・sinπt/2T...(25)

On the other hand, the signal j(t) of the 1/2 frequency divider circuit 58 and the output signal k(t) obtained by shifting the phase of this output signal j(t) by 90° by the 90° phase shifter 59 are each expressed by the following equation (26 )formula,
It is expressed as equation (27).

j(t)=±cosπt/2T...(26) k(t)=±sinπt/2T...(27) These output signals j(t) and k(t) are each input to multiplier 6.
0,62 by the output signals b ₁ (t), b ₂ (t) of the low-pass filters 67, 68, and the output signal l ₁ (t)
(Fig. 7 l) and l ₂ (t) (Fig. 7 m) are output to the timing determiners 57 and 56, respectively. These output signals l ₁ (t) and l ₂ (t) are as follows (28 ) formula, (29)
It is expressed by the formula.

l ₁ (t)=±1/4Q(t)(1+cosπt/T) ……(28) l ₂ (t)=±1/4I(t)(1−cosπt/T) ……(29) This ( As can be seen from equations 28) and (29),
In the case of (B), the output signal l ₁ (t) of the multipliers 60 and 62,
l ₂ (t) is exactly the opposite of (A). However, the identification timing signal -g(t) obtained from the polarity inverter 55 (Fig. 7k) and the identification timing signal +g(t) obtained from the 1/2 frequency divider circuit 53 (Fig. 7i) are exactly ( Since it is the opposite of case A), the data timing and identification pulse timing of each axis are the same combination, and the center of the data is identified.

As explained above, the embodiment shown in FIG. 6 can always identify the center of demodulated data regardless of the phase of the 1/2 cycle signal of the reproduced clock.

Note that it is not an important question which of the demodulation axes 1 and 2 the I-axis data and the Q-axis data on the transmitting side are demodulated. In other words, similar to the offset QPSK signal demodulator, since there is a temporal order relationship between I-axis data and Q-axis data, when parallel-serial exchange is performed, the data of the two axes are sequentially switched and sent out in synchronization with T seconds. Just do it.

Also, as mentioned above, the demodulated data has (±) polarity ambiguity, which is explained by (a) and (b) below.
It can be solved using one of the following methods.

(a) A method in which the I and Q axes are differentially encoded on the transmitting side and differentially decoded after demodulation on the receiving side (differential encoding method); (b) A method in which a specific pattern is inserted in advance into the transmitted code. The receiving side then determines the polarity of the demodulated data from the shape of the demodulated specific pattern (coherent method). The method described above is the same method as used in the offset QPSK signal demodulator. This is because the MSK signal is offset as is clear from the signal generation process described above.
The format of the signal after demodulating the MSK signal and identifying the timing is the same as that of offset QPSK, since it is obtained by balanced modulation of each axis of the QPSK signal with sinπt/2T and cosπt/2T, respectively. It is clear from the point of view.

Next, the second part of the MSK signal demodulation device of the present invention
An example will be described. FIG. 8 is a block diagram showing this second embodiment. In FIG. 8, the same parts as those in FIG. I will focus on this.

As shown in FIG. 8, the means for reproducing a clock signal from demodulated data is also different from the above embodiment. That is, in the carrier phase locked loop 52, the exclusive logic circuit 70 has amplitude discriminators 70, 71
The synchronous detector 52 calculates the exclusive OR of the outputs of
c, and the synchronous detector 52
c, the output of VCO52e is low pass filter 52
It is designed to be input through d.

Amplitude discriminators 70 and 71 are multipliers 60 and 71, respectively.
The amplitude of the output of 62 is identified and outputted to the exclusive OR circuit 52f and timing determiners 57 and 56.

6 in that the output of the 1/2 frequency divider 58 is applied to the multiplier 61 through the 90° phase shifter 54.

In the case of FIG. 8, there is no need for an envelope detector of a narrow band filter in the high frequency stage, and there is an advantage that the clock regeneration circuit can be constructed entirely of digital circuits.

In addition, in the case of Figure 6, the sequence is that carrier synchronization is established after clock synchronization is established, so the clock regeneration circuit is not affected by the carrier synchronization circuit and is an extremely stable circuit, but in the case of Figure 8, the demodulated data To regenerate the clock signal from
Clock recovery circuits are affected by carrier synchronization conditions.

However, if the transmission clock signal is extremely stable compared to the carrier, the VCO of the clock regeneration circuit can be highly stabilized. Therefore, the loop band of the clock synchronized loop can be made sufficiently narrower than that of the carrier synchronized loop, so even if the carrier is out of synchronization, clock synchronization can be maintained for a sufficient period of time for the carrier to resynchronize. .

Therefore, a modified example can be realized as a demodulator for MSK signals whose clock stability is sufficiently higher than that of a carrier.

〔Effect of the invention〕

As described above, according to the MSK signal demodulation device of the present invention, the modulation component of the MSK signal is extracted to reproduce the recovered clock signal, and the low frequency components of the outputs of two orthogonal synchronous detectors are filtered through the low frequency filter. The frequency of the input signal is determined as a function of the phase error between the reproduced carrier waves by performing an exclusive OR with the output and a signal with a frequency of 1/2 of the reproduced clock signal. A component that is a function of the phase error is used as a control voltage to control the phase of the oscillation departure of the voltage controlled oscillator, thereby generating a regenerated carrier wave, and outputs from two orthogonal synchronous detectors to a regenerated clock. The MSK signal is orthogonal by multiplying it by two signals that are 1/4 the frequency of the signal and orthogonal, and by identifying the outputs of the two multipliers with a clock signal that has a different polarity and has a frequency that is 1/2 the frequency of the reproduced clock signal. Since the digital data of each axis is demodulated, there is an advantage that the center of the demodulated data can always be identified with a simple configuration regardless of the phase of the signal having a frequency of 1/2 of the reproduced clock.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams of conventional MSK signal demodulation methods, respectively, and FIG. 3 is a time chart for explaining the operation of the demodulation method shown in FIG.
Fig. 4 is a block diagram of a conventional carrier-dependent MSK demodulation system, and Fig. 5 shows how to create an MSK modulation signal applied to the MSK signal demodulation device of the present invention.
The block diagram of the MSK modulator, Figure 6, is this invention.
A block diagram of an embodiment of an MSK signal demodulator,
FIG. 7 is a time chart for explaining the operation of the MSK signal demodulation device of FIG. 6, and FIG. 8 is a block diagram of another embodiment of the MSK signal demodulation device of the present invention. 50, 51, 52c...Synchronous detector, 52...
Carrier phase locked loop, 52e, 65...VCO,
52f...exclusive OR circuit, 53, 58...1/
2 frequency divider circuit, 54, 59, 60...90° phase shifter, 5
5... Polarity inverter, 56, 57... Timing determiner, 60-63... Multiplier, 70, 71... Amplitude discriminator.

Claims (1)

[Claims] 1. A circuit that extracts the modulation component of the MSK signal and reproduces the recovered clock signal, and a circuit that extracts the low-frequency components of the outputs of two orthogonal synchronous detectors using a low-pass filter and then performs an exclusive OR operation. Means for generating a signal component that is a function of the phase error between the frequency of the input signal and the recovered carrier wave by exclusive ORing the exclusive OR output with a signal having a frequency that is 1/2 of the recovered clock signal. a carrier synchronization circuit that obtains a recovered carrier wave by controlling the oscillation output phase of the voltage controlled oscillator using a component that is a function of the phase error as a control voltage; A circuit for multiplying by two orthogonal signals having a frequency of 1/4 of the signal, and a clock signal having a frequency of 1/2 of the reproduced clock signal and different polarities to identify the outputs of the two multipliers. An MSK signal demodulation device comprising means for demodulating digital data of each orthogonal axis of the MSK signal.