JPH0533250U - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To give confidentiality to the data in the storage unit and to facilitate inspection of the storage unit. A selection circuit control circuit 4 for controlling the connection between a first data bus 3b connected to the outside and a second data bus 3b connected to the storage unit 1 according to the number of times the select signal CS becomes an active level. And a bus connection control circuit 5.
The storage unit 1 according to the output signal (NJ) of the selection circuit control circuit 4
A signal control circuit 9 for controlling a write control signal (internal write signal IW) and a read control signal (internal read header signal IR) is provided. First and second data buses 3a, 3b
The data of is compared and the result is output. A latch circuit 7 and an output circuit 8 are provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a rewritable memory and capable of externally controlling writing and reading of data.

[0002]

[Prior Art]

 Conventionally, this kind of semiconductor integrated circuit is activated when the select signal CS becomes the active level and becomes the address specified by the address signals A0 to A15 when the write control signal WR is the active level, as shown in FIG. A memory unit 1 for writing data and reading data from an address specified by the address signals A0 to A15 when the read control signal RD is at an active level, and an address bus 2 for transmitting the address signals A0 to A15 to the memory unit 1. The data bus 3 transmits external data to the storage unit 1 and transmits data from the storage unit 1 to the outside.

Next, the operation of this semiconductor integrated circuit will be described. FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the semiconductor integrated circuit.

First, a case where data is externally written in the storage unit 1 will be described. Address signals A0 to A15 to be written are transmitted to the storage unit 1 via the address bus 2, data D0 to D7 to be written are transmitted to the storage unit 1 via the data bus 3, and at the same time an external active level signal is generated. By inputting the (low level) write control signal WR, data is written in the storage unit 1 (write cycle in FIG. 4).

Next, a case where data in the storage unit 1 is read from the outside will be described. The address signals A0 to A15 to be read are transmitted to the storage unit 1 via the address bus 2 and the read control signal RD is externally input to the storage unit 1 to transfer the data D0 to D7 to the data bus 3. It is possible to read out to the outside through (the read cycle of FIG. 4).

[0006]

[Problems to be solved by the device]

 In the conventional semiconductor integrated circuit described above, it is possible to always write data to the storage unit 1 from the outside and read data from the storage unit 1, so that the confidentiality of the data in the storage unit 1 cannot be maintained. There are drawbacks.

Further, if the reading is simply disabled, the storage unit 1 cannot be inspected.

An object of the present invention is to provide a semiconductor integrated circuit that has confidentiality with respect to data in a storage unit and can easily inspect the storage unit.

[0009]

[Means for Solving the Problems]

 The semiconductor integrated circuit of the present invention is activated when the select signal becomes the active level and writes data to the address specified by the address signal when the internal write signal is at the active level and specifies the address signal when the internal read signal is at the active level. Connected to a memory unit for reading data from the stored address, a first data bus connected to this memory unit for transmitting data to and from this memory unit, and a data input / output terminal. A second data bus for transmitting data from the outside to the storage unit and data from the storage unit and the number of times the select signal becomes the active level are determined, and when this number is the first preset number Is a first level, and a number-of-times determination circuit that outputs a number-of-times determination signal that is a second level when the number of times is the second number; Is a bus connection control circuit that connects the first data bus and the second data bus and disconnects the second data bus at the second level; the data of the first data bus and the data of the second data bus. And a comparison judgment signal output circuit for latching the comparison judgment signal at a predetermined timing and outputting the result to the outside, and the number of times judgment signal When the write control signal is the active level when the first level, the internal write signal is the active level, and when the number determination signal is the second level, the internal read signal is the inactive level when the write control signal is the inactive level. A signal control circuit for setting a signal to an active level.

[0010]

【Example】

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this embodiment, the address signals A0 to A15 which are activated when the select signal CS becomes the active level (low level) and which are input via the address bus 2 when the internal write signal IW is the active level (low level). A storage unit 1 for writing data to the address specified by and reading the data from the address specified by the address signals A0 to A15 when the internal read signal IR is at an active level (low level); The first data bus 3a for transmitting data to and from the storage unit 1 and the data input / output terminal are connected to the external data to the storage unit 1 and the data from the storage unit 1. The number of times that the second data bus 3b to be transmitted and the select signal CS become the active level is determined, and when this number is the preset first number (first time), the high level is set. , The selection number determination circuit 4 which outputs the number determination signal NJ which becomes the low level at the second number (second time), and the first data bus 3a and the second number when the number determination signal NJ is at the high level. The bus connection control circuit 5 that connects the data bus 3b and disconnects it when the level is low is compared with the data of the first data bus 3a and the data of the second data bus 3b to determine whether or not they match. And the comparison circuit 6 which outputs the comparison determination signal CJ, and the latch circuit 7 and the output circuit 8 of the comparison determination signal output circuit which latch the comparison determination signal CJ at a predetermined timing and output it to the outside (CJO). If the write control signal WR is at an active level (low level) when the determination signal NJ is at a high level, the internal write signal IW is set at an active level (low level) and the write control signal is inactive when the number determination signal NJ is at a high level. level If low level) the internal read signal IR active level (has a configuration and a signal control circuit 9, a low level). The selection number determination circuit 4 is a T-type flip-flop, the latch circuit 7 is a 3-state buffer B1 and a D-type flip-flop DFF1, the output circuit 8 is a D flip-flop DFF2, and the signal control circuit 9 is a 3-state buffer. B2 and B3 respectively.

Next, the operation of this embodiment will be described. FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

In the initial state, the selection circuit determination circuit 4 and the output circuit 8 are reset by the reset signal RST, and the frequency determination signal NJ and the output comparison determination signal CJO are low level.

The number determination signal NJ goes high due to the first active level of the select signal CS, so that the 3-state buffer B2 is activated and the bus connection control circuit 5 connects the data buses 3a and 3b. Further, the 3-state buffers B1 and B3 are inactivated. In this state, since data is written in the storage unit 1, data ED0 to ED7 from the outside are written to the addresses designated by the address signals A0 to A15 through the data buses 3b and 3a. ..

Next, since the number determination signal NJ becomes low level by the second active level of the select signal CS, the 3-state buffer B2 becomes inactive, and the bus connection control circuit disconnects the data buses 3a and 3b. Also, the 3-state buffers B1 and B3 are activated. In this state, data is read from the storage unit 1 and this data is compared with externally input data. Externally input data ED0 to ED7 are input to the comparison circuit 6 via the data bus 3b and compared.

As a result, the comparison determination signal CJ becomes low level when it is determined that the externally input data ED0 to ED7 and the read data ID0 to ID7 match, and becomes high level when it is determined that they do not match.

The comparison determination signal CJ is latched with the write control signal WR at the rising edge and is output (CJO) to the outside through the output circuit 8.

In this way, it is possible to inspect whether the storage unit 1 operates normally.

In this embodiment, when the number of times that the select signal CS becomes the active level is the first time, it is the state of writing data from the outside to the storage unit 1 and when it is the second time, the state of reading the data from the storage unit 1. Becomes However, even when data is being read from the storage unit 1, the read data is not output to the outside but used internally or subjected to comparison inspection. Even if the active state of the select signal CS is set to the first state and the data buses 3a and 3b are connected to each other and the level of the write control signal WR is controlled to make the read state, the data buses 3a and 3b are connected to each other. At this time, since the 3-state buffer B3 is inactive, the internal read signal IR does not go to the active level, and the memory 1 cannot be put into the read state. Therefore, the data in the storage unit 1 can be kept secret.

Further, as long as the storage unit 1 is not destroyed, data rewriting and reinspection can be easily performed.

[0022]

[Effect of the device]

 As described above, according to the present invention, the connection between the first data bus connected to the outside and the second data bus connected to the storage unit is controlled by the number of times the select signal becomes the active level, and the storage is performed. By controlling the write control signal (internal write signal) and the read control signal (internal read) to the part, comparing the data of the first and second data buses, and outputting the result, Since the data in the storage unit cannot be read while the second data buses are connected, the confidentiality of the data in the storage unit can be maintained, and the data read from the storage unit and external Since the data can be compared and the comparison result can be known, there is an effect that the storage unit can be easily inspected.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the semiconductor integrated circuit shown in FIG.

[Explanation of symbols]

 1 storage unit 2 address bus 3, 3a, 3b data bus 4 selection circuit determination circuit 5 bus connection control circuit 6 comparison circuit 7 latch circuit 8 output circuit 9 signal control circuit

Claims (1)

[Scope of utility model registration request] 1. When the select signal becomes active level, it is activated, and when the internal write signal is active level, data is written to the address specified by the address signal. When the internal read signal is active level, the address specified by the address signal is written. A storage unit for reading out data, a first data bus connected to the storage unit for transmitting data to and from the storage unit, and a data input / output terminal for external connection to the storage unit And a second data bus for transmitting data from the storage unit and the data from the storage unit, and the number of times the select signal becomes the active level is determined, and when this number is the preset first number, the first level , A selection number determination circuit that outputs a number determination signal that becomes a second level when the number of times is the second number, and the first data when the number determination signal is at the first level. The bus connection control circuit that connects the bus and the second data bus and disconnects the bus at the second level and the data of the first data bus and the data of the second data bus are compared to determine whether they match. A comparison circuit that determines whether or not the comparison judgment signal is output, a comparison judgment signal output circuit that latches the comparison judgment signal at a predetermined timing and outputs the signal to the outside, and a write operation when the number judgment signal is at the first level A signal control circuit that sets the internal write signal to the active level when the control signal is at the active level and sets the internal read signal to the active level when the write control signal is at the inactive level when the number-of-times determination signal is at the second level And a semiconductor integrated circuit.