JPH05334181A - Control signal generator - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a control signal generator capable of easily controlling a generated signal by rewriting an address setting value or a timing setting value. [Configuration] Rewritable setting address information is stored in the setting register 8, and the CPU uses the bus line 70.
This address value is specified through to access. However, since the set address information itself is not stored immediately after the power is input, the CPU reads the ROM 93.
I can't access the program and cannot load the program itself. Therefore, the CPU tries to access the ROM 93 based on the address value fixed and stored in the first initial address generation circuit in terms of hardware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generator, and more particularly to a control signal generator which controls a generated signal by rewriting a set value.

[0002]

2. Description of the Related Art As a control signal generator, for example, FIG.
There are control circuits 72, 74 ... Shown in FIG. This control circuit 7
Reference numerals 2, 74, etc. control commands for writing and reading data given from the CPU 2 to the memories 73, 75, .... Details of the functions and operations of the respective units will be described below with reference to FIG.

A plurality of memories for storing data from the CPU 2 are provided. In the example of FIG. 12, the memories 73 and 75
... are provided, and control circuits 72 and 74 are provided corresponding to the respective memories.
... is provided. And each control circuit,
In order to distinguish the memories, (001) ₂ , (010) ₂ ...
U2 specifies the memory by specifying this upper address and processes the data. Here, () ₂ is a display showing binary data. The individual upper address of each memory is specified by rearranging the circuit configuration in the control circuit.

Now, assume that data is written in the memory 73. In this case, the CPU 2 directly outputs the data to be written to the memory via the bus line 71. The CPU 2 also outputs address data through the bus line 70 at the same time. As the address data, for example, (00110100) ₂ is output. In this
The previous three digits (001) ₂ indicate the individual upper address of the control circuit 72, and this (001) ₂ is fetched by the control circuit 72. Then, the control circuit 72 knows that its own individual upper address is designated, and recognizes that data should be written in the memory 73. Although the higher-order address (001) ₂ is given to all other control circuits (for example, the control circuit 74), the individual higher-order address ((010) _{2 in the} control circuit 74) does not match in the other control circuits. Therefore, the writing process is not performed.

Upper address (001) ₂ from CPU ₂
The control circuit 72 that has taken in outputs the CS signal to the chip select CS input of the memory 73. In addition, the control circuit 7
An R / W signal is given to CPU 2 from CPU 2. This R /
The W signal is a signal for instructing either writing or reading processing, and is given as an L signal in the case of writing processing and as an H signal in the case of reading processing. Since the writing process is performed now, the L signal is given. Then, the control circuit 72 outputs a write permission signal to the W input of the memory 73 based on the R / W signal. In addition, when reading data, R /
The H signal is given as the W signal, and the control circuit 72 outputs the read permission signal to the R input.

As described above, the CS signal and the write enable signal are output from the control circuit 72, and the memory 73 writes the data given through the bus line 71 at the time of receiving these signals. Of the above address data (00110100) ₂ , the last five digits (1010
0) ₂ indicates a lower address. This lower address indicates a write address in the memory 73, and the memory 73 takes in the lower address and writes and stores the data in the storage area of (10100) ₂ . When the data processing is completed, the control circuit 72 sends the CP via the OR circuit G3.
Output a response signal to U2. The CPU 2 recognizes the end of the data processing based on this response signal.

By the way, new data is sequentially output onto the bus line 71, and is sequentially written in each memory based on the instruction of the address data as described above. Therefore, immediately after the output of new data, the data is in an unstable state in relation to the previous data content. If such unstable data were written in the memory, incorrect data would be stored.
That is, if the control circuit 72 outputs the CS signal and the write enable signal immediately after the CPU 2 outputs the data via the bus line 71, there is a risk of malfunction.

Therefore, the control circuit, after outputting the CS signal,
The write enable signal is output to the memory with a delay of a certain time. When the control circuit generates such a time difference, it becomes possible to wait for the data on the bus line 71 to stabilize before performing the writing process. In addition, CP
The same applies when there is a data read command from U2.
In order to read stable data, the control circuit outputs a read enable signal to the R input of the memory with a delay for a certain time.

As a method of delaying the write permission signal and the read permission signal from the control circuit for a fixed time, a delay circuit or a logic circuit is used. The delay time can be adjusted by changing the circuit configuration such as the delay circuit built in the control circuit.

[0010]

The conventional control signal generator has the following problems. As described above, the control circuit waits for stabilization of the data contents before processing, so the control circuit
After transmitting the S signal, a write enable signal or the like is output to the memory with a delay of a certain time. Then, a delay circuit or a logic circuit is used to generate such a time difference.

Here, this delay time, that is, the time until the data content stabilizes, varies depending on the control target (for example, memory), and it is necessary to set the delay time according to these control targets. However, in the conventional control circuit in which the time difference is generated by the configuration of the delay circuit or the logic circuit, when changing the delay time, the circuit configuration must be rearranged. That is, it is not possible to flexibly deal with various delay times.

The individual higher-order address given to each control circuit is also specified by rearranging the circuit configuration in the control circuit. Therefore, the individual upper address cannot be changed easily.

As described above, the conventional control circuit is poor in versatility, and there is a problem that the circuit rearrangement work is required when changing the delay time or the individual upper address, for example. Therefore, it is an object of the present invention to provide a control signal generator that can easily control a generated signal by rewriting an address setting value or a timing setting value.

[0014]

According to another aspect of the present invention, there is provided a control signal generator which receives an address signal and an operation signal and outputs an address selection signal and a timing signal. Set value storage means for storing, a timing set value storage means for storing rewritable timing set values, an initial address value storage means for storing a hardware fixed initial address value, an address signal, and an address set value. Alternatively, an address match signal output means for outputting an address match signal based on an initial address value, an operation signal, an address match signal, and a timing control means for outputting an address selection signal and a timing signal based on a timing set value are provided. Is characterized by.

According to another aspect of the control signal generator of the present invention, the address match signal output means does not output the address match signal based on the initial address value when the initial mode signal is not applied. Generator.

A control signal generator according to a third aspect of the present invention comprises a mode switching register address value storage means for storing a mode switching register address value capable of rewriting the mode switching register for outputting the mode switching signal. The control signal generating device is characterized in that the address of is determined by the address value of the mode switching register.

[0017]

In the control signal generator of the first aspect, the address setting value or the timing setting value can be rewritten. Therefore, these set values can be arbitrarily changed.

Further, the address match signal output means outputs an address match signal based on the address signal and the address set value or the initial address value. Therefore, even when the address setting value is not stored in the address setting value storage means, the address match signal can be output based on the initial address value.

In the control signal generator of claim 2,
When the initial mode signal is not given, the address match signal output means does not output the address match signal based on the initial address value. Therefore, if the initial mode signal is not given, the output of the address match signal based on the initial address value can be prohibited, and the same value as the address given to the other storage means can be used as the initial address value.

In the control signal generator of claim 3,
The address of the mode switching register is determined by the mode switching register address value. Therefore, the address of the mode switching register can be freely changed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic structure and operation of the control signal generator will be described. FIG. 4 is a block diagram of the control signal generator 10 in the present embodiment, which is provided in place of the control circuits 72, 74 ... Shown in FIG.

That is, each control signal generator 10 is provided with an individual upper address, and the address data transmitted through the bus line 70 is fetched to determine whether or not its own individual upper address is designated. Further, the control signal generator 10 outputs the CS signal to the memory when its own individual upper address is designated. Further, after the CS signal is output, a write signal or a read signal is output after a certain delay, and the process is performed after the data on the bus line 71 is stabilized.

First, the operation in the case where the control signal generator 10 fetches the address data and determines whether its own individual upper address is designated will be described with reference to FIG.
As shown in the figure, a setting register 8 is provided in the control signal generator 10, and the setting register 8 stores setting address information and setting control information. FIG. 6 shows the detailed contents of the setting address information and the setting control information.
Listed. For example, it is assumed that an individual upper address (0010000) ₂ and a mask bit (00011111) ₂ are stored as the set address information. The mask bits (00011111) ₂ is shown to eliminate the 5 digits after from the individual upper address (00100000) _2. As a result, the individual upper address of the control signal generator 10 (001) ₂ Is recognized.

The control signal generator 10 is further provided with a comparator H1. The comparator H1 fetches the set address information and the address data (see FIG. 12) transmitted from the CPU 2 through the bus line 70,
Compare these. When the two match, the address match signal is output to the timing control circuit 6.

Now, suppose that the CPU 2 is temporarily operated through the bus line 70.
It is assumed that address data (00110100) ₂ is transmitted from The last 3 digits (00
1) ₂ indicates the upper address. The comparator H1 takes in the address data (00110100) 2 and at the same time reads the set address information from the setting register 8.
In this case, since the set address information is recognized as the individual upper address (001) ₂ as described above, the control signal generator 10 knows that its own individual upper address is designated, and the address match signal Is output.

Next, the operation of the timing control circuit 6 which receives the address match signal will be described in detail. For example, in this case, it is assumed that the CPU 2 has given a data write command. Specifically, the R / W signal from the CPU 2 is given as the L signal instructing the writing (see FIGS. 4 and 12). This L signal as an R / W signal is
It is directly taken into the timing control circuit 6. In addition,
FIG. 7 shows a timing chart of various signal outputs.

A detailed circuit configuration of the timing control circuit 6 is shown in FIG. First, the address match signal from the comparator H1 (FIG. 4) is given to the AND circuit D1, and the valid signal (1
11111111) ₂ is input, the CS signal is output to the memory (see the timing chart of FIG. 7 and FIGS. 4 and 12). This valid signal is stored in the setting register 8, and when each data becomes stable after the program is started at the time of power input ((000000)
It is rewritten from (00) ₂ to (11111111) ₂ .

While the CS signal is output to the memory, the timers 52, 53 in the timing control circuit 6,
54 is set to start. Further, the address match signal is sent to the flip-flop F through the inverting circuit K1.
It is applied to the R inputs of 1, F2 and F3 to reset each flip-flop.

On the other hand, from the CPU 2, R /
The W signal is given to the timing control circuit 6 as the L signal (see the timing chart of FIG. 7). This L signal becomes an H signal by the inverting circuit K2 and is given to the AND circuit D3. Further, a writable signal is taken into the AND circuit D3 from the setting control information stored in the setting register 8 (FIG. 4).

The writable signal in this case is (11111111) ₂ as shown in FIG. 6, and as a result, the AND circuit D3 recognizes that writing is permitted and outputs a signal. This writable signal itself can also be freely rewritten and controlled. If the writable signal is set to (00000000) ₂ , the output of the write enable signal from the timing control circuit 6 can be prohibited, and the memory can be exclusively used for reading data. Similarly, the readable signal is set to (0000
If it is set to 0000) ₂ , reading can be prohibited.

The output signal from the AND circuit D3 is
It is taken into the AND circuit D5. And AND circuit D
Since 5 outputs a write enable signal to the memory,
It is in a state of waiting for a signal to be given from the flip-flop F2. The output signal from the AND circuit D3 is also fetched into the AND circuit D6 via the OR circuit G1.
The AND circuit D6 also waits for the signal from the flip-flop F3 and outputs a response signal.

On the other hand, the comparator H3 fetches the timer from the timer 53 and the write signal set value and compares them. This write signal setting value is stored in the setting register 8 as setting control information. The write signal setting value in this case is (00
110000) ₂ is stored, which corresponds to 30 μSEC. In other words, the comparator H3 receives 30 μSEC after the timer 53 is started by the address match signal.
When the time has elapsed, the signal is output to the S input of the flip-flop F2 (see the timing chart of FIG. 7).

With the signal input to the S input of the flip-flop F2, the flip-flop F2 supplies a signal to the AND circuit D5. In this way, the AND circuit D5 outputs the write enable signal to the W input of the memory, and the memory performs the writing process of the data sent via the bus line 71 (see FIGS. 4 and 12).

The comparator H4 also takes in the timer from the timer 54 and the response signal set value and compares them. This response signal set value is also stored in the setting register 8 and is set to (01010010) ₂ . This set value corresponds to 40 μSEC. That is,
When the comparator H4 passes 40 μSEC (10 μSEC after the write enable signal is output), the flip-flop F
A signal is output toward the S input of No. 3 (see the timing chart of FIG. 7).

With the signal input to the S input of the flip-flop F3, the flip-flop F3 supplies a signal to the AND circuit D6. Thus, from the AND circuit D6, the CPU
2, a response signal is output toward CPU 2, and the CPU 2 recognizes that the data writing process is completed and starts the next processing operation (see FIGS. 4 and 12).

The setting register 8 also stores a read signal setting value (00011000) ₂ as setting control information. This set value corresponds to 10μSEC,
A read permission signal is output from the AND circuit D4 when 10 μSEC has elapsed.

The above is the signal generating operation of the control signal generator 10. Here, each data stored in the setting register 8 can be freely rewritten under the control of the CPU 2. By rewriting these data, for example, the individual upper address can be easily changed, and the versatility of the device can be improved. Further, the read signal set value, the write signal set value, the response signal set value, etc. can be freely rewritten (see FIG. 6). That is, the output time of the read permission signal, the write permission signal, and the response signal output from the timing control circuit 6 can be arbitrarily changed correspondingly. Furthermore, it is easy to change the readable signal and the writable signal (see FIG. 6).

Details of the data rewriting operation in the setting register 8 will be described below with reference to FIG. First, when rewriting the data in the setting register 8, the CPU 2 outputs address data through the bus line 70.
Now, suppose that address data (00001001) ₂ is output. In this address data, the previous 5 digits indicate the upper setting address, and the upper setting address (00
001) ₂ is taken into the comparator H5.

On the other hand, the individual higher-order set address value circuit 35 stores the individual higher-order set address value (00001) ₂ given to the setting register 8. As aforementioned,
Since a plurality of control signal generators each having a built-in setting register are provided corresponding to each memory (see control circuits 72, 74 ... In FIG. 12), an individual upper setting address for specifying each setting register is provided. A value is given and stored.

The comparator H5 This individual upper set address value (00001) ₂ uptake, compared with the upper set address (00001) ₂ given through the bus line 70. In this case, since the two match, the comparator H5 outputs a setting register matching signal to the setting register 8.
Upon receiving this setting register match signal, the setting register 8
Knowing that self has been designated, recognizes that the stored data should be rewritten.

Further, the setting register 8 has a bus line 7
The lower setting address is given through 0. This lower setting address specifies which data in each data (FIG. 6) in the setting register 8 is rewritten, that is, the storage area in the setting register 8 is specified. Specifically, the 3-digit (001) ₂ after the address data (00001001) ₂ indicates the lower setting address. For example, if the storage area corresponding to (001) ₂ is the storage location of the response signal setting value, it is recognized that the response signal setting value should be rewritten.

The newly written response signal set value data is given from the CPU 2 through the bus line 71. In FIG. 12, the data on the bus line 71 is not taken in by the control circuit, but in this example, the bus line 71 is connected to the setting register of each control signal generator (not shown). For example, (01010111) ₂ is given from the bus line 71, and this new data is stored as the response signal setting value.

As described above, the data in the setting register 8 can be easily rewritten based on the instruction from the CPU 2. In addition, individual upper address, write signal setting value,
The same operation is performed for read signal setting values,
The setting value is changed.

Next, FIG. 9 shows another configuration relating to data rewriting in the setting register 8. In this configuration,
The set address coincidence signal output from the comparator H5 is temporarily taken into the AND circuit D7. Then, the signal is output to the setting register 8 only after the state control signal from the CPU 2 is given to the comparator H5.

As described above, even if, for example, the address data (00001001) ₂ is output through the bus line 70, as long as the status control signal is not applied, the setting register 8
The rewriting of the data inside is not executed. That is, if the data rewriting in the setting register 8 is prohibited during the normal operation, the address (00001)
001) ₂ can be given as an individual address of another memory. In this way, it becomes possible to efficiently assign an address value to each storage area.

Another configuration corresponding to FIG. 4 is shown in FIG.
This is another configuration example of output control of the address match signal. As shown in the figure, the address match signal is once taken in by the AND circuit D8. And this AND circuit D8
A set address coincidence signal is applied to the input terminal via the inverting circuit K3. That is, while the set address match signal is output and the data in the setting register 8 is being rewritten, the output of the address match signal is prohibited. In this way, it is possible to prevent the address coincidence signal from being erroneously output during data rewriting, and it is possible to reliably prevent malfunction.

Next, FIG. 11 shows a circuit having another structure. As described above, the CPU 2 controls a plurality of control signal generators and memories (see FIG. 12), and each control signal generator has a setting register and a timing control circuit. In the circuit configuration shown in FIG. 11, the timing control circuit is extracted from this and the timing control circuit 6 is shared through the multiplexer 30. The details will be described below.

The address data given through the bus line 70 is taken into each of the comparators H6, H7 and H8,
It is compared with the individual upper address of each setting register 81, 82, 83. Then, an address match signal is output from the comparator that matches the address data. The address match signal is first fetched by the multiplexer 30. The multiplexer 30 selects a setting register based on the address match signal, fetches predetermined setting control information from the setting register, and supplies it to the timing control circuit 6.

The address coincidence signal output from the comparator is applied to the timing control circuit 6 via the OR circuit G2. The timing control circuit 6 is also supplied with the R / W signal from the CPU 2. In this way, the timing control circuit 6 outputs various signals (CS signal, R signal, W signal, etc.) to the memory. By sharing the timing control circuit as described above, it is possible to reduce the cost of the product.

Next, an embodiment of the control signal generator according to the present invention will be described with reference to FIG. This FIG. 1 is an embodiment for FIG. 4, and in the control signal generator 10, a first initial address generating circuit 3 which is an initial address value storage means, a comparator H9, and an OR as an address coincidence signal output means. A circuit G4 is provided. The control signal generator 10 shown in FIG. 1 is provided for controlling the data of the ROM 93. The function and operation of each part will be described below.

In the setting register in the control signal generator,
As described above, various data such as setting address information and setting control information are stored. Then, processing control for the memory is performed based on these setting data.
Immediately after the power supply to the computer, the setting register in each control signal generator is in a state in which predetermined data is not written. Therefore, when the power is input, the CPU first reads and executes the stored initial program sequentially from the head address of the ROM 93, and writes and stores predetermined data in each setting register according to this program.

However, as shown in FIG.
The setting register 8 is also provided in the control signal generator 10 itself, and the setting address information and the like are not stored in the setting register 8 immediately after the power is input. Therefore, C
Even if the PU outputs the address data, the ROM 93
Cannot be specified, and the initial program itself stored in the ROM 93 cannot be loaded.

In order to eliminate such an inconvenience, in this embodiment, the first initial address generating circuit 3 and the comparator H are used.
9 is provided. In the first initial address generating circuit 3, for example, (000) ₂ is set in hardware as an initial address indicating the ROM 93. Since it is set by hardware, the (000) ₂ signal is reliably output even immediately after power is input. Then, the initial address (000) ₂ output from the first initial address generation circuit 3 is fetched by the comparator H9.

On the other hand, the CPU immediately after the power is input, the ROM 93
Address data (000) ₂ is output through the bus line 70 in order to access. Then, this address data (000) ₂ is also taken into the comparator H9. In this way, the comparator H9 recognizes that its own memory, that is, the ROM 93 is designated by the coincidence of both signals, and outputs the address coincidence signal. The address match signal is given to the timing control circuit 6 through the OR circuit G4.

As described above, the CPU accesses the ROM 93, fetches the initial program in the ROM 93,
Write the setting data to the setting register in each control signal generator. Then, based on the data in each setting register, another memory is accessed, and thereafter, a predetermined process is executed. As shown in FIG. 1, the OR circuit G
The address match signal from the comparator H1 is also supplied to the comparator 4, and the address match signal is output to the timing control circuit 6 even during normal operation.

FIG. 2 shows another embodiment. This is
An AND circuit D9 is further provided to the control signal generator shown in FIG. The AND circuit D9 includes the comparator H described above.
A mode switching signal output from the CPU is given together with the address match signal output from the CPU 9. That is, unless the mode switching signal from the CPU is given as the H level (initial mode signal), the address coincidence signal is not output to the timing control circuit 6.

Immediately after the power is input, the CPU first sets the comparator H
This mode switching signal is output to the H level as the H level. Therefore, as described with reference to FIG. 1, the address data (0
00) ₂ is given, the comparator H9 outputs an address coincidence signal. Then, based on this, the CPU
Access M93 to load the initial program.

In this way, after loading the initial program, the CPU sets the mode switching signal to the L level. That is, after that, even if the address data (000) ₂ is given through the bus line 70, the AND circuit D
No address match signal is output from 9. After that, the address designation from the CPU to the ROM 93 is
This is performed based on the setting address information stored in the setting register 8.

By setting the mode switching signal to the L level, the address data (000) 2 can be given as an individual address of another memory. That is, it becomes possible to efficiently assign the value of the address to each storage area.

FIG. 3 shows a circuit configuration for controlling the mode switching signal. Mode switching register 77
Mode switching information is stored in the memory, and a mode switching signal is output from this to the AND circuit D9 (FIG. 2). As described above, since it is necessary to output the mode switching signal as H level immediately after the power is input, the mode switching register 77 automatically outputs "1" when the power is input. There is. At the same time, this "1" is stored as mode switching information.

When the mode switching signal "1" is given to the AND circuit D9, the CPU is made to operate in the ROM 93.
, And execute the initial program to write predetermined data to each setting register. At this time, the CPU also writes the setting address information and the setting control information in the mode address setting register 79. The mode address setting register 79 stores the individual address given to the mode switching register 77.

Data writing to the mode address setting register 79 is performed as follows. The individual address of the mode address setting register 79 itself is stored in hardware in the second initial address generation circuit 17, and this individual address, for example, (010) ₂ is output to the comparator H11. On the other hand, since the CPU designates the mode address setting register 79, the address data (010) _{2 is transferred} to the comparator H through the bus line 70.
Give to 11. The comparator H11 outputs a signal to the AND circuit D11 when the two signals match.

The AND circuit D11 receives the mode switching signal output from the mode switching register 77. At this point in time, the mode switching signal is at the H level "1", so the AND circuit D11
Upon receiving the signal from the comparator H11, the signal is output to the mode address setting register 79. In this way, the mode address setting register 79 recognizes that data should be written to itself as an initial operation, and fetches and stores the data given from the CPU, for example, (100) ₂ through the bus line 71. As described above, the data (100) ₂ written here is the mode switching register 77.
It is an individual address assigned to.

As described above, the CPU finishes the processing such as data writing to each setting register, that is, the execution processing of the initial program. And because it goes into normal processing,
As described with reference to FIG. 2, the mode switching signal is set to the L level “0”. The operation for setting the mode switching signal to "0" will be described below.

In this case, the CPU uses the individual address stored in the third initial address generating circuit 27 to access the mode switching register 77. In the third initial address generation circuit 27, an individual address, for example, (011) ₂ is stored by hardware. C
PU gives this (011) ₂ to the comparator H12 through the bus line 70, and the comparator H12 outputs a signal to the AND circuit D12 based on the coincidence of both signals.

Here, the AND circuit D12 receives the mode switching signal output from the mode switching register 77. At this point, the mode switching signal is still at the H level "1", so the AND circuit D12
Receives the signal from the comparator H12 and receives the OR circuit G
5. Output a signal to the mode switching register 77 through the timing control circuit 89. In this way, the mode switching register 77 is designated, and the mode switching signal is switched from the H level "1" to the L level "0".

As described above, the mode switching signal is switched to "0" and given to the AND circuit D9 in FIG. Then, the normal processing operation is started thereafter.
However, it may be necessary to rewrite the data in the setting register during normal operation. In this case, the mode switching signal output from the mode switching register 77 has to be set to "1" again just as when the power is input.

At this time, using the individual address (100) ₂ stored in the mode address setting register 79,
Access the mode switching register 77. Specifically, the CPU supplies the address data (100) ₂ to the comparator H10 through the bus line 70. Then, the comparator H10 takes in (100) ₂ stored in the mode address setting register 79, and outputs the coincidence signal to the AND circuit D.
Output to 10.

Here, the mode switching signal from the mode switching register 77 is applied to the AND circuit D10 through the inverting circuit K4. At this time, the mode switching signal is "0", which is inverted by the inverting circuit K4 and taken into the AND circuit D10 as H level "1". Therefore, the AND circuit D1
A signal is output from 0 and is input to the mode switching register 77 through the OR circuit G5 and the timing control circuit 89.

As described above, the CPU accesses the mode switching register 77 and switches the mode switching signal from the L level "0" to the H level "1".

[0071]

In the control signal generator of the first aspect, the address setting value or the timing setting value can be rewritten. That is, these set values can be arbitrarily changed.

Therefore, the versatility of the control signal generator can be improved by changing the set value.

Further, the address match signal output means outputs an address match signal based on the address signal and the address set value or the initial address value. That is, even when the address setting value is not stored in the address setting value storage means, the address match signal can be output based on the initial address value.

Therefore, for example, even after the power is input and before the address setting value is written, the access can be performed based on the hardware-fixed initial address value.

In the control signal generator of claim 2,
When the initial mode signal is not given, the address match signal output means does not output the address match signal based on the initial address value. That is, if the initial mode signal is not given, the output of the address match signal based on the initial address value can be prohibited, and the same value as the address given to the other storage means can be used as the initial address value.

Therefore, the address setting value can be efficiently given to other storage means.

In the control signal generator of claim 3,
The address of the mode switching register is determined by the mode switching register address value. That is, the address of the mode switching register can be freely changed.

Therefore, the degree of freedom of the address value can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a control signal generator according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the control signal generator according to the present invention.

3 is a circuit diagram for controlling a mode switching signal in FIG.

FIG. 4 is a circuit diagram showing a basic configuration of a control signal generator.

5 is a detailed circuit diagram of the timing control circuit of FIG.

6 is a diagram showing the contents of stored data in a setting register of FIG.

FIG. 7 is a timing chart of various output signals.

FIG. 8 is a circuit diagram showing another control signal generator.

9 is another embodiment of the circuit shown in FIG. 8. FIG.

FIG. 10 is another embodiment of the circuit shown in FIG.

FIG. 11 is a circuit diagram when a timing control circuit is shared.

FIG. 12 is a circuit diagram showing an outline of conventional data control.

[Explanation of symbols]

 3 ... First initial address generation circuit 6 ... Timing control circuit 8 ... Setting register 10 ... Control signal generator 17 ... Second generation of initial address Circuit 27 ...- Third initial address generation circuit 77-Mode switching register 79-Mode address setting register D9-Comparator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shingo Yamada 10 Ouron Co., Ltd., Hanazono Dodo-cho, Ukyo-ku, Kyoto City, Kyoto Prefecture

Claims (3)

[Claims] 1. A control signal generator which outputs an address selection signal and a timing signal in response to an address signal and an operation signal, an address set value storage means for storing a rewritable address set value, and a rewritable timing setting. A timing setting value storage means for storing a value, an initial address value storage means for storing a hardware-fixed initial address value, an address signal, and an address for outputting an address match signal based on the address setting value or the initial address value. A control signal generation device comprising: a coincidence signal output means, an operation signal, an address coincidence signal, and timing control means for outputting an address selection signal and a timing signal based on a timing set value. 2. The control signal generator according to claim 1, wherein when the initial mode signal is not given, the address match signal output means does not output the address match signal based on the initial address value. Control signal generator. 3. The control signal generator according to claim 2, further comprising a mode switching register address value storage means for storing a mode switching register rewritable mode switching register address value for outputting the mode switching signal. A control signal generator, wherein the address of the switching register is determined by the mode switching register address value.