JPH05335366A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05335366A
JPH05335366A JP4163656A JP16365692A JPH05335366A JP H05335366 A JPH05335366 A JP H05335366A JP 4163656 A JP4163656 A JP 4163656A JP 16365692 A JP16365692 A JP 16365692A JP H05335366 A JPH05335366 A JP H05335366A
Authority
JP
Japan
Prior art keywords
lead frame
insulator
chip
semiconductor device
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4163656A
Other languages
Japanese (ja)
Other versions
JP2795069B2 (en
Inventor
Kazuaki Maehara
和明 前原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4163656A priority Critical patent/JP2795069B2/en
Publication of JPH05335366A publication Critical patent/JPH05335366A/en
Application granted granted Critical
Publication of JP2795069B2 publication Critical patent/JP2795069B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 半導体装置の樹脂封止工程において、ボンデ
ィングワイヤが樹脂により変形されて、隣接のワイヤ同
士が接触するのを防ぐ。 【構成】 銅板１上に、絶縁体２を介してリードフレー
ム３を、また導電性接着剤４を介してチップ５を固着す
る。チップ５上のパッドとリードフレーム３とをボンデ
ィングワイヤ６で接続する際に、絶縁体２上を中継点と
して用いる。 (57) [Abstract] [Purpose] To prevent a bonding wire from being deformed by resin and contacting adjacent wires in a resin sealing process of a semiconductor device. [Structure] On a copper plate 1, a lead frame 3 is fixed via an insulator 2, and a chip 5 is fixed via a conductive adhesive 4. When connecting the pad on the chip 5 and the lead frame 3 with the bonding wire 6, the insulator 2 is used as a relay point.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に樹脂封止された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.

【０００２】[0002]

【従来の技術】多層リードフレームを用いた半導体装置
では、チップおよびリードフレームが銅板上に固着され
ることが多い。即ち、図３に示されるように、銅板１上
に絶縁体２を介してリードフレーム３が固着され、銅板
１の中央には導電性接着剤４を介してチップ５が搭載さ
れる。そして、チップ５−リードフレーム間をボンディ
ングワイヤ６により接続した後、全体をモールド樹脂７
により封止している。2. Description of the Related Art In a semiconductor device using a multilayer lead frame, a chip and a lead frame are often fixed on a copper plate. That is, as shown in FIG. 3, the lead frame 3 is fixed on the copper plate 1 via the insulator 2, and the chip 5 is mounted on the center of the copper plate 1 via the conductive adhesive 4. Then, after the chip 5 and the lead frame are connected by the bonding wire 6, the whole is molded resin 7.
It is sealed by.

【０００３】[0003]

【発明が解決しようとする課題】上述した従来の半導体
装置では、チップとリードフレーム間が直接ボンディン
グワイヤにより接続されているため、ボンディングワイ
ヤが長い場合には、樹脂封止の際にボンディングワイヤ
が変形してしまい、隣り合うボンディングワイヤ同士が
接触してしまうという問題点があった。In the conventional semiconductor device described above, since the chip and the lead frame are directly connected to each other by the bonding wire, if the bonding wire is long, the bonding wire is not sealed at the time of resin sealing. There is a problem in that the bonding wires are deformed and adjacent bonding wires come into contact with each other.

【０００４】[0004]

【課題を解決するための手段】本発明の半導体装置は、
金属板の中央にチップが搭載され、その周辺に絶縁体を
介してリードフレームが固着され、全体がモールド樹脂
により封止されたものであって、チップ−リードフレー
ム間を接続するボンディングワイヤは、チップ−リード
フレーム間の途中で絶縁体上にもボンディングされてい
る。The semiconductor device of the present invention comprises:
A chip is mounted in the center of a metal plate, a lead frame is fixed to the periphery through an insulator, and the whole is sealed with a mold resin. The bonding wire connecting the chip and the lead frame is Bonding is also performed on the insulator midway between the chip and the lead frame.

【０００５】[0005]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は、本発明の第１の実施例を示す断面
図である。この半導体装置は、次のようにして組み立て
られる。銅板１に、予めリードフレーム３が固着されて
いる絶縁体２を接着剤を用いて接着する。この絶縁体２
の内側部分には突起が形成されており、この突起上には
メタライズ層が形成されている。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. This semiconductor device is assembled as follows. The insulator 2 to which the lead frame 3 is fixed in advance is adhered to the copper plate 1 using an adhesive. This insulator 2
A protrusion is formed on the inner side of the substrate, and a metallized layer is formed on the protrusion.

【０００６】次に、銅板１上に導電性接着剤４を用いて
チップ５をマウントする。次いで、ボンディングワイヤ
６を用いてチップ上のパッド−絶縁体２上のメタライズ
層−リードフレーム３の順にボンディングを行い、最後
にモールド樹脂７にて封止を行う。Next, the chip 5 is mounted on the copper plate 1 by using the conductive adhesive 4. Next, the bonding wire 6 is used to perform bonding in the order of the pad on the chip-the metallized layer on the insulator 2-the lead frame 3, and finally sealing with the molding resin 7.

【０００７】このように構成された半導体装置では、ボ
ンディングワイヤが中継点を経由しているためフライイ
ングワイヤ長が短くなり、変形されにくくなる。そのた
め、モールド工程でのワイヤ変形による短絡事故が激減
し歩留りが向上する。In the semiconductor device configured as described above, since the bonding wire passes through the relay point, the length of the flying wire is shortened and it is less likely to be deformed. Therefore, the short circuit accident due to the wire deformation in the molding process is drastically reduced, and the yield is improved.

【０００８】本実施例では、絶縁体２に突起を設けて絶
縁体のボンディング面と、チップやリードフレームのボ
ンディング面との高低差を少なくしている。この構成に
よりフライイングワイヤ長をより短くすることができ、
また、ボンディング工程も容易化される。リードフレー
ムが多層リードフレームであるとき、リードフレームの
面に合わせて絶縁体の突起の表面にも凹凸を作ることが
できる。In this embodiment, the insulator 2 is provided with a protrusion to reduce the height difference between the insulator bonding surface and the chip or lead frame bonding surface. With this configuration, the flying wire length can be shortened,
Also, the bonding process is facilitated. When the lead frame is a multi-layer lead frame, it is possible to make unevenness on the surface of the protrusion of the insulator in accordance with the surface of the lead frame.

【０００９】図２は、本発明の第２の実施例を示す断面
図である。本実施例は、絶縁体２上で２回ワイヤボンデ
ィングを行っている点が先の実施例と相違しているが、
その他の点では同様である。FIG. 2 is a sectional view showing a second embodiment of the present invention. This embodiment is different from the previous embodiment in that wire bonding is performed twice on the insulator 2.
The other points are the same.

【００１０】[0010]

【発明の効果】以上説明したように、本発明の半導体装
置は、チップ−リードフレーム間のワイヤボンディング
を、リードフレームが固着された絶縁体を中継点として
行うものであるので、本発明によれば、ボンディングワ
イヤのフライイングワイヤ長を短くすることができる。
従って、本発明によれば、樹脂封止の際のボンディング
ワイヤの変形を抑制することができ、隣接するボンディ
ングワイヤ同士が接触するという事故を防止することが
できる。As described above, in the semiconductor device of the present invention, the wire bonding between the chip and the lead frame is performed by using the insulator to which the lead frame is fixed as a relay point. For example, the flying wire length of the bonding wire can be shortened.
Therefore, according to the present invention, the deformation of the bonding wire at the time of resin sealing can be suppressed, and the accident that adjacent bonding wires contact each other can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図２】 本発明の第２の実施例の断面図。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図３】 従来例の断面図。FIG. 3 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

１ 銅板 ２ 絶縁体 ３ リードフレーム ４ 導電性接着剤 ５ チップ ６ ボンディングワイヤ ７ モールド樹脂 1 Copper Plate 2 Insulator 3 Lead Frame 4 Conductive Adhesive 5 Chip 6 Bonding Wire 7 Mold Resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 絶縁体上にリードフレームが固定され、
半導体素子上のパッドと前記リードフレーム間がボンデ
ィングワイヤにより接続され、全体がモールド樹脂によ
り封止されている半導体装置において、前記ボンディン
グワイヤが、前記リードフレーム−前記半導体素子間に
おいて、前記絶縁体上にもボンディングされていること
を特徴とする半導体装置。1. A lead frame is fixed on an insulator,
In a semiconductor device in which a pad on a semiconductor element and the lead frame are connected by a bonding wire and the whole is sealed with a molding resin, the bonding wire is on the insulator between the lead frame and the semiconductor element. A semiconductor device which is also bonded to.
JP4163656A 1992-05-29 1992-05-29 Semiconductor device Expired - Fee Related JP2795069B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4163656A JP2795069B2 (en) 1992-05-29 1992-05-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4163656A JP2795069B2 (en) 1992-05-29 1992-05-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05335366A true JPH05335366A (en) 1993-12-17
JP2795069B2 JP2795069B2 (en) 1998-09-10

Family

ID=15778088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4163656A Expired - Fee Related JP2795069B2 (en) 1992-05-29 1992-05-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2795069B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839556A (en) * 1983-02-25 1989-06-13 Rca Licensing Corporation Cathode-ray tube having an improved shadow mask contour
US7199477B1 (en) * 2000-09-29 2007-04-03 Altera Corporation Multi-tiered lead package for an integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113931U (en) * 1984-06-29 1986-01-27 関西日本電気株式会社 semiconductor equipment
JPH0399455A (en) * 1989-09-05 1991-04-24 Advanced Micro Devices Inc Package of integrated circuit capsuled by high performance plastics

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113931U (en) * 1984-06-29 1986-01-27 関西日本電気株式会社 semiconductor equipment
JPH0399455A (en) * 1989-09-05 1991-04-24 Advanced Micro Devices Inc Package of integrated circuit capsuled by high performance plastics

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839556A (en) * 1983-02-25 1989-06-13 Rca Licensing Corporation Cathode-ray tube having an improved shadow mask contour
US7199477B1 (en) * 2000-09-29 2007-04-03 Altera Corporation Multi-tiered lead package for an integrated circuit

Also Published As

Publication number Publication date
JP2795069B2 (en) 1998-09-10

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