JPH05335437A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05335437A
JPH05335437A JP4143847A JP14384792A JPH05335437A JP H05335437 A JPH05335437 A JP H05335437A JP 4143847 A JP4143847 A JP 4143847A JP 14384792 A JP14384792 A JP 14384792A JP H05335437 A JPH05335437 A JP H05335437A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
solder
mounting
face electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4143847A
Other languages
Japanese (ja)
Inventor
Osamu Onishi
修 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4143847A priority Critical patent/JPH05335437A/en
Publication of JPH05335437A publication Critical patent/JPH05335437A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】実装時のはんだ不良を防止する半導体装置を得
る。 【構成】金メッキやはんだメッキにより、はんだ付性を
良くした端面電極2の中央部から上に、はんだレジスト
4を形成する。
(57) [Abstract] [Purpose] To obtain a semiconductor device that prevents solder defects during mounting. [Structure] A solder resist 4 is formed on the end surface electrode 2 having a good solderability by gold plating or solder plating, from the central portion to the upper portion.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
端面電極を有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an end face electrode.

【0002】[0002]

【従来の技術】端面電極を有する半導体装置は、図3
(a),(b)に示すようにスルーホールを半分に切断
した形状の端面電極2と凹状の素子搭載部12を有する
パッケージ基板1に、1個あるいは複数個の半導体素子
8を接着剤10によりダイボンディングし、この半導体
素子8と配線9をボンディングワイヤ11により接続
し、半導体素子8とボンディングワイヤ11を、エポキ
シ樹脂等の樹脂3で封止した構造となっている。
2. Description of the Related Art A semiconductor device having an end face electrode is shown in FIG.
As shown in (a) and (b), one or a plurality of semiconductor elements 8 are attached to a package substrate 1 having an end surface electrode 2 having a shape obtained by cutting a through hole in half and a concave element mounting portion 12 with an adhesive 10. The semiconductor element 8 and the wiring 9 are connected by a bonding wire 11, and the semiconductor element 8 and the bonding wire 11 are sealed with a resin 3 such as an epoxy resin.

【0003】図4(a)は、この従来の半導体装置の端
面電極の近傍の斜視図である。端面電極2の表面全体に
はAuメッキあるいは、はんだメッキ等が施こされ、は
んだ付性が良好になるように仕上げられている。
FIG. 4A is a perspective view showing the vicinity of an end face electrode of this conventional semiconductor device. Au plating, solder plating, or the like is applied to the entire surface of the end face electrode 2 to finish the solderability.

【0004】[0004]

【発明が解決しようとする課題】上述した半導体装置を
実装基板に搭載する場合、あるかじめ印刷法により、実
装基板上の搭載電極に一定量のはんだを塗布しておき、
半導体装置を端面電極と実装基板上の搭載電極が合うよ
うに搭載する。その後、遠赤外等によるはんだリフロー
法で、端面電極と搭載電極をはんだ付することにより、
実装基板への半導体装置の搭載を完成させている。
When the above-described semiconductor device is mounted on a mounting board, a certain amount of solder is applied to the mounting electrodes on the mounting board by a certain printing method.
The semiconductor device is mounted so that the end surface electrodes and the mounting electrodes on the mounting substrate match. After that, by soldering the end face electrode and the mounting electrode by a solder reflow method using far infrared rays,
The mounting of the semiconductor device on the mounting board has been completed.

【0005】しかし従来の端面電極2の場合、端面電極
の表面全体が、Auメッキ等ではんだ付性が極めて良い
状態に仕上げられているため、図4(b)に示すよう
に、はんだリフロー時に搭載電極6上に印刷されたはん
だ5が必要以上に吸い上げられるため、搭載電極6と端
面電極2を接続するために必要な量のはんだが搭載電極
6上に残らないようという不具合が生じ、半導体装置の
実装の信頼性が低下するという問題がある。
However, in the case of the conventional end face electrode 2, since the entire surface of the end face electrode is finished to have a very good solderability by Au plating or the like, at the time of solder reflow, as shown in FIG. 4 (b). Since the solder 5 printed on the mounting electrode 6 is sucked up more than necessary, there occurs a problem that the amount of solder necessary for connecting the mounting electrode 6 and the end surface electrode 2 does not remain on the mounting electrode 6, and the semiconductor There is a problem that the mounting reliability of the device is reduced.

【0006】[0006]

【課題を解決するための手段】本発明による半導体装置
は、メッキが施された端面電極を側面に有するパッケー
ジ基板と、このパッケージ基板上に固定された半導体素
子と、この半導体素子を封止する樹脂とを有する半導体
装置において、前記端面電極の中央部にはんだ付性を阻
害する領域を設けたものである。
A semiconductor device according to the present invention includes a package substrate having a plated end surface electrode on its side surface, a semiconductor element fixed on the package substrate, and the semiconductor element sealed. In a semiconductor device having a resin, a region that hinders solderability is provided in the central portion of the end face electrode.

【0007】[0007]

【実施例】次に本発明いついて、図面を参照して説明す
る。
The present invention will now be described with reference to the drawings.

【0008】図1(a),(b)は、本発明の第1実施
例を説明するための端面電極近傍の斜視図である。
FIGS. 1 (a) and 1 (b) are perspective views showing the vicinity of an end face electrode for explaining a first embodiment of the present invention.

【0009】半導体装置は図3(a),(b)に示した
ように、端面電極2と配線9と半導体素子搭載部12を
備えたパッケージ基板1と、このパッケージ基板1上に
接着剤10により固定された半導体素子8と、この半導
体素子8とパッケージ基板1上に設けられた配線9とを
接続するボンディングワイヤ11と、これら半導体素子
8等を封止するエポキシ等の樹脂3とから主に構成され
ている。
As shown in FIGS. 3A and 3B, the semiconductor device includes a package substrate 1 having an end face electrode 2, wiring 9 and a semiconductor element mounting portion 12, and an adhesive 10 on the package substrate 1. The semiconductor element 8 fixed by the above, the bonding wire 11 for connecting the semiconductor element 8 and the wiring 9 provided on the package substrate 1, and the resin 3 such as epoxy for sealing the semiconductor element 8 and the like. Is configured.

【0010】そして端面電極2は、あらかじめ、Auメ
ッキあるいははんだメッキ等によりはんだ付性が良好な
状態に仕上られているが、特にその中央部から上部には
はんだレジスト4が塗布されている。
The end surface electrode 2 is previously finished in a good solderability state by Au plating, solder plating, or the like, and a solder resist 4 is applied especially from the central portion to the upper portion.

【0011】このように構成された第1実施例の半導体
装置を実装する場合、図1(b)に示したように、搭載
電極6と半導体装置の端面電極2とを遠赤外線はんだリ
フロー法により、はんだ接続を行なうが、はんだレジス
ト4により端面電極2の上方向へのはんだ5の吸い上げ
が防止される。このため、搭載電極6と端面電極2との
接続を得るためのはんだ量は十分なものとなるため、実
装の信頼性は向上する。
When the semiconductor device of the first embodiment having the above-described structure is mounted, as shown in FIG. 1B, the mounting electrode 6 and the end face electrode 2 of the semiconductor device are formed by the far infrared solder reflow method. , Solder connection is made, but the solder resist 4 prevents the solder 5 from being sucked upward in the end face electrode 2. For this reason, the amount of solder for obtaining the connection between the mounting electrode 6 and the end surface electrode 2 is sufficient, so that the reliability of mounting is improved.

【0012】図2(a),(b)は本発明の第2実施例
の半導体装置の端面電極近傍の斜視図である。
FIGS. 2A and 2B are perspective views showing the vicinity of the end face electrodes of the semiconductor device according to the second embodiment of the present invention.

【0013】パッケージ基板1に設けられた端面電極2
Aにはあらかじめはんだ付性をよくするためにAuある
いははんだメッキが施されるが、この第2の実施例の端
面電極2Aの中央部は、これらのメッキが施されていな
い未メッキ部7を有している。この未メッキ部7は、端
面電極2Aにメッキを施す前に、端面電極2Aの一部に
はんだレジストあるいはフォトレジストを塗布してお
き、メッキを施した後このはんだレジストあるいはフォ
トレジストを除去して形成する。
End face electrodes 2 provided on the package substrate 1
Au is pre-plated with Au or solder in order to improve solderability, but the central portion of the end face electrode 2A of the second embodiment has an unplated portion 7 not plated with these. Have In this unplated portion 7, before the end face electrode 2A is plated, a solder resist or a photoresist is applied to a part of the end face electrode 2A, and after the plating is performed, the solder resist or the photoresist is removed. Form.

【0014】このように構成された第2実施例の半導体
装置を実装する場合、図2(b)に示したように搭載電
極6と半導体装置の端面電極2Aとを遠赤外線リフロー
法により、はんだ付接続を行なうが、未メッキ部7がは
んだ付性に劣るため、第1実施例と同様に、端面電極2
Aの上方向へのはんだ5の吸い上げが防止されるため、
搭載電極6と端面電極2Aとの接続は十分なはんだ量で
行なわれる。
When mounting the semiconductor device of the second embodiment having such a structure, the mounting electrode 6 and the end face electrode 2A of the semiconductor device are soldered by the far infrared ray reflow method as shown in FIG. 2B. However, since the unplated portion 7 is inferior in solderability, the end face electrode 2 is formed similarly to the first embodiment.
Since the solder 5 is prevented from being sucked up in the upper direction,
The mounting electrode 6 and the end surface electrode 2A are connected with a sufficient amount of solder.

【0015】[0015]

【発明の効果】以上説明したように本発明は、端面電極
の中央部にはんだ付性の劣る領域を形成することによ
り、実装時端面電極への余分なはんだの吸い上げを防止
できるため、搭載電極と端面電極との接続に必要なはん
だ量を確保できる。このため実装の信頼性を向上させる
ことができるという効果がある。
As described above, according to the present invention, since a region having poor solderability is formed in the central portion of the end face electrode, it is possible to prevent excess solder from being sucked up to the end face electrode during mounting. It is possible to secure the amount of solder required for the connection between the electrode and the end face electrode. Therefore, there is an effect that the reliability of mounting can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の端面電極近傍の斜視図。FIG. 1 is a perspective view of the vicinity of an end face electrode according to a first embodiment of the present invention.

【図2】本発明の第2実施例の端面電極近傍の斜視図。FIG. 2 is a perspective view of the vicinity of an end face electrode according to a second embodiment of the present invention.

【図3】本発明の対象となる半導体装置の斜視図および
断面図。
3A and 3B are a perspective view and a cross-sectional view of a semiconductor device which is an object of the present invention.

【図4】従来の半導体装置の端面電極近傍の斜視図。FIG. 4 is a perspective view of an end face electrode and its vicinity of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 パッケージ基板 2,2A 端面電極 3 樹脂 4 はんだレジスト 5 はんだ 6 搭載電極 7 未メッキ部 8 半導体素子 9 配線 10 接着剤 11 ボンディングワイヤ 12 素子搭載部 1 Package Substrate 2, 2A End Face Electrode 3 Resin 4 Solder Resist 5 Solder 6 Mounting Electrode 7 Unplated Part 8 Semiconductor Element 9 Wiring 10 Adhesive 11 Bonding Wire 12 Element Mounting Part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 メッキが施された端面電極を側面に有す
るパッケージ基板と、このパッケージ基板上に固定され
た半導体素子と、この半導体素子を封止する樹脂とを有
する半導体装置において、前記端面電極の中央部にはん
だ付性を阻害する領域を設けたことを特徴とする半導体
装置。
1. A semiconductor device comprising a package substrate having a plated end surface electrode on a side surface thereof, a semiconductor element fixed on the package substrate, and a resin sealing the semiconductor element, wherein the end surface electrode is provided. A semiconductor device having a region for impairing solderability in a central portion of the semiconductor device.
JP4143847A 1992-06-04 1992-06-04 Semiconductor device Pending JPH05335437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4143847A JPH05335437A (en) 1992-06-04 1992-06-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4143847A JPH05335437A (en) 1992-06-04 1992-06-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05335437A true JPH05335437A (en) 1993-12-17

Family

ID=15348342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4143847A Pending JPH05335437A (en) 1992-06-04 1992-06-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05335437A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952717A (en) * 1994-12-29 1999-09-14 Sony Corporation Semiconductor device and method for producing the same
US5962917A (en) * 1997-03-31 1999-10-05 Nec Corporation Semiconductor device package having end-face halved through-holes and inside-area through-holes
JP2000133845A (en) * 1998-10-23 2000-05-12 Rohm Co Ltd Semiconductor light emitting device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01102946A (en) * 1987-10-15 1989-04-20 Mitsubishi Electric Corp Mounting of electronic component by reflow soldering
JPH03185754A (en) * 1989-12-14 1991-08-13 Nec Corp Semiconductor device
JPH04142765A (en) * 1990-10-04 1992-05-15 Nec Corp Lsi package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01102946A (en) * 1987-10-15 1989-04-20 Mitsubishi Electric Corp Mounting of electronic component by reflow soldering
JPH03185754A (en) * 1989-12-14 1991-08-13 Nec Corp Semiconductor device
JPH04142765A (en) * 1990-10-04 1992-05-15 Nec Corp Lsi package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952717A (en) * 1994-12-29 1999-09-14 Sony Corporation Semiconductor device and method for producing the same
US5962917A (en) * 1997-03-31 1999-10-05 Nec Corporation Semiconductor device package having end-face halved through-holes and inside-area through-holes
JP2000133845A (en) * 1998-10-23 2000-05-12 Rohm Co Ltd Semiconductor light emitting device

Similar Documents

Publication Publication Date Title
JP2520575B2 (en) Resilient lead for electrically and mechanically connecting an integrated circuit chip package to a surface of a substrate and method of manufacturing the same
JPH09232499A (en) Semiconductor device
JPH05335437A (en) Semiconductor device
JPH0547836A (en) Semiconductor device mounting structure
KR200153438Y1 (en) Chip scale package with tap tape
JPH05160316A (en) Semiconductor element
JPH05144821A (en) Semiconductor device
JPS63250163A (en) Semiconductor integrated circuit device
JP2536724B2 (en) Mounting structure of leadframe type magnetoresistive sensor
JPH11176849A (en) Method for manufacturing semiconductor device
JPH03257854A (en) Semiconductor device
JP2774566B2 (en) Semiconductor device lead frame
JP2991174B2 (en) Lead frame for semiconductor device and method of manufacturing the semiconductor device
JPH0451056B2 (en)
JPH06334059A (en) Semiconductor mounting board and production thereof
JPH08130267A (en) Resin-sealed semiconductor package, resin-sealed semiconductor device using the same, and manufacturing method thereof
JPH05166811A (en) Solder bump formation method
JPH0513011Y2 (en)
JPH0214558A (en) Semiconductor integrated circuit device
JP3221304B2 (en) Semiconductor device and method of manufacturing the same
KR950006837Y1 (en) Out lead surface exposed semiconductor package
JPH0864745A (en) Semiconductor device
JPH04162466A (en) Lead frame for semiconductor device
JPH0555436A (en) Lead frame for semiconductor device
JPH09213856A (en) Semiconductor device

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19980217