JPH0534005Y2 - - Google Patents

Description

[Detailed description of the invention] <Field of industrial application> The invention is installed in a follow-up circuit configured to maintain a constant relationship between its input signal and its output signal. The present invention relates to an improvement in a defect detection circuit that monitors the operation of a device.

<Prior Art> In controlling processes and the like, a follow-up circuit is used to monitor whether or not an input signal and an output signal maintain a constant relationship.

A typical follow-up circuit calculates the deviation between the input signal and the output signal of this follow-up circuit using an arithmetic unit, compares the output of this arithmetic unit with a zero level using a comparator, and determines the polarity of the output. The output of the integrator is controlled to be increased or decreased depending on the determination result, and the output signal of the integrator is made to match the input signal.

Furthermore, such a follow-up circuit is provided with a defect detection circuit in order to monitor its operation. This defect detection circuit is configured to detect the input/output deviation of the arithmetic unit in the follow-up circuit, cancel the timer reset signal when the deviation exceeds a set value, and output an alarm after a certain period of time.

<Problem to be solved by the invention> However, since the defect detection circuit of the conventional follow-up circuit described above is constructed using an analog method, it is a complicated circuit and has the problem of being cumbersome to install in recent digital equipment. It was hot.

The present invention aims to solve such problems, and aims to realize a defect detection circuit of a follow-up circuit using a digital system and a simple configuration.

<Means for Solving the Problems> The present invention, which has solved the above problems, includes an arithmetic unit that calculates the deviation between an input signal and an output signal, and compares the deviation with a zero level, and when the deviation is positive, “1”
A comparator that outputs a level and outputs a "0" level when it is negative, and a comparator that outputs an output increasing direction signal when the output of this comparator is a "1" level, and the output of the comparator outputs a "0" level. A polarity discrimination circuit outputs an output decrease direction signal, and an integrator that receives the output increase direction signal of the polarity discrimination circuit to increase its output and receives the output decrease direction signal to decrease its output. The output of this integrator is installed in a follow-up circuit that follows the input signal as an output circuit, and in a defect detection circuit of the follow-up circuit that detects a malfunction in the operation of the follow-up circuit, a rise of the output of the comparator causes A monomulti that generates a pulse with a constant time width, an oscillator that outputs an output signal of a constant frequency, a gate that performs an opening/closing operation and passes the output of the oscillator when it is open, and a constant frequency output signal given from this gate. a counter that counts the output signal and is set by a pulse of a certain time width output from the monomulti, and when an overflow occurs, supplies the overflow signal to the gate as a closing signal; This is a defect detection circuit for a follow-up circuit characterized in that it is used as a defect detection signal for the follow-up circuit.

<Operation> The defect detection circuit of the follow-up circuit of the present invention operates as follows.

When the follow-up circuit is in a normal state, the counter counts the output signal of a constant frequency from the oscillator, and is reset by a pulse of a constant time width from the monomulti. When the follow-up circuit enters an abnormal state and the deviation between its input signal and output signal remains at the "0" level or "1" level, the counter overflows and this overflow signal is used as a defect detection signal of the follow-up circuit.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

First, referring to this figure, a portion of a general tracking circuit will be explained.

That is, 1 is the deviation ε between the input signal E _i and the output signal E _O
2 is a comparator that compares the output of the comparator with a zero level; 3 determines the polarity of the output of the comparator 2 and generates a signal to switch the integration method of the integrator according to the polarity. The polarity determining circuit 4 is an integrator that receives the output of the polarity determining circuit 3. This integrator 4 constitutes a signal hold circuit for input signals, and its output E _O is input to the arithmetic unit 1 .

These arithmetic unit 1, comparator 2, polarity discrimination circuit 3
and an integrator 4 constitute a follow-up circuit, and the output of the integrator 4 with respect to the input signal E _i is taken as the output signal E _O of this follow-up circuit.

Now, the defect detection circuit of the present invention added to such a follow-up circuit is constituted by the following circuit elements.

That is, the defect detection circuit includes an oscillator 5 that generates a pulse, an AND gate 6 that receives the output of the oscillator 5, a counter 7 that receives the output of the AND gate 6, and a constant value that receives the output of the comparator 2 in the follow-up circuit. It is composed of a monomulti 8 that outputs pulses with a certain width. Furthermore, the output of counter 7 is an alarm signal.
It is output as ALARM and also input to AND gate 6. Further, the output pulse E _R of the monomulti 8 functions as a reset signal for the counter 7.

Now, the operation of the follow-up circuit configured as described above and the defect detection circuit added to the follow-up circuit will be explained using the time chart shown in FIG. 2.

First, the operation of the follow-up circuit will be explained.

The comparator 2 receives the deviation output ε from the arithmetic unit 1, compares this output ε with a zero level, and outputs a signal E _C as shown in FIG. The comparator 2 outputs a "1" level when the deviation output ε is positive, and outputs a "0" level when it is negative. Further, the comparator 2 may be provided with a hysteresis characteristic in order to operate stably even when the deviation output ε is around "0". When a hysteresis characteristic is provided, the output of comparator 2 will always be at either the "1" level or the "0" level even when the deviation output ε takes a value near "0", resulting in stable operation. can be done. The width of this hysteresis can be set to any value as necessary.

The polarity determination circuit 3 switches the polarity of the signal given to the integrator 4 according to the output of the comparator 2. When the output E _C of the comparator 2 is at the “1 _” level, it indicates that the output E _O is smaller than the input E _i . ) is output. Also, the output of comparator 2
When E _C is at the “0” level, it indicates that the output E _O is larger than the input E _i , so the output of the integrator 4 is
E _O is the output decreasing direction signal (DOWN
signal).

The integrator 4 receives such UP and DOWN signals and outputs an integrated waveform as shown in FIG. 2 E _O , and its output E _O is controlled so as to match the input signal E _i . Incidentally, the integrator 4 is not limited to an analog integrator, and may be of a digital type. When using an analog integrator, the UP signal becomes a negative reference voltage, and the DOWN signal becomes a positive reference voltage. On the other hand, when using a digital integrator, both the UP and DOWN signals become pulse signals. Further, when using a digital type integrator, it is necessary to use digital types for both the arithmetic unit 1 and the comparator 2.

Next, the operation of the follow-up circuit defect detection circuit of the present invention installed in such a follow-up circuit will be explained.

The monomulti 8 generates a pulse E _R of a constant time width as shown in FIG. 2 E _R in response to the rise of the output E _C of the comparator 2. This pulse E _R acts as a reset signal for the counter 7, and this pulse
Each time E _R rises, the contents of counter 7 are cleared to "0".

When the follow-up circuit is operating normally, the pulse _ER , which is the reset signal, is repeatedly output at certain intervals, so the counter 7 will not overflow.

On the other hand, if an abnormality occurs in the follow-up circuit, the output E _C of the comparator 2 will maintain either the "0" level or the "1" level, and the monomulti 8 will output a pulse E _R that is a reset signal. It will no longer be done.
In the case of FIG. 2, the output E _C of the comparator 2 remains at the "1" level, and as a result, the counter 7 continues counting the output pulses from the oscillator 5 and eventually overflows. When the counter 7 overflows, the AND gate 6 closes and remains in this state thereafter. It is assumed that the overflow signal is output as a negative logic (“0” level).

The overflow signal of this counter 7 is used as an alarm signal ALARM. Alarm signal ALARM
This state is maintained until the follow-up circuit returns to the normal operating state and the monomulti 8 outputs the pulse E _R. Figure 2 ALARM is an alarm signal
FIG. 3 is a diagram showing the output state of ALARM. This alarm signal ALARM is used to turn on the alarm lamp. Alternatively, an alarm operation such as sounding an alarm buzzer can be performed.

The time set in counter 7, i.e. monomulti 8
During the time T from when the alarm signal ALARM stops operating until the alarm signal ALARM is output, the follow-up circuit uses the input signal E _i
Set it longer than the time required to track the maximum change in . As a result, the alarm signal ALARM will not be output while the follow-up circuit is operating normally.

Note that the output signal E _O of the integrator 4 is always in the increasing or decreasing direction, and even when the deviation output ε becomes "0", the comparator 2 that compares the deviation output ε and the integrator 4 output, As a result, a "1" level or a "0" level is output with the hysteresis width, and the output E _O of the integrator 4 increases or decreases depending on the output signal of the polarity determining circuit 3.

In the above explanation, the monomulti 8 was used to pulse the output E _C of the comparator 2 and generate the reset signal _ER , but a differentiating circuit may be used instead of the mono multi 8 to pulse the output E C.

<Effects of the invention> As explained in detail above, according to the defect detection circuit of the follow-up circuit of the present invention, failure detection of the follow-up circuit can be performed in a digital manner, and the defect detection circuit can be realized with a simple configuration. can do.

[Brief explanation of drawings]

FIG. 1 is an electrical configuration diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing operating waveforms of various parts in the embodiment of the present invention shown in FIG. 1... Arithmetic unit, 2... Comparator, 3... Polarity discrimination circuit, 4... Integrator, 5... Oscillator, 6... AND gate, 7... Counter, 8... Mono multi.

Claims (1)

[Scope of utility model registration request] A computing unit that calculates the deviation between the input signal and the output signal, and a comparison device that compares the deviation with a zero level and outputs a “1” level when the deviation is positive and outputs a “0” level when it is negative. a polarity determining circuit that outputs an output increasing direction signal when the output of the comparator is at the "1" level and outputting an output decreasing direction signal when the output of the comparator is at the "0"level; an integrator that receives the output increasing direction signal of the discrimination circuit to increase its output and receives the output decreasing direction signal of the discrimination circuit and decreases its output, and an output signal in which the output of the integrator follows the input signal. In the defect detection circuit of the follow-up circuit that is installed in the follow-up circuit and detects a malfunction of the follow-up circuit, a monomultiply that generates a pulse of a certain time width by the rising edge of the output of the comparator, and an output of a constant frequency are used. an oscillator that outputs a signal; a gate that performs an opening/closing operation and allows the output of the oscillator to pass through when it is open;
a counter that counts the output signal of a constant frequency given from the gate, is reset by a pulse of a constant time width output from the monomulti, and when an overflow occurs, gives this overflow signal to the gate as a close signal; A failure detection circuit for a follow-up circuit, characterized in that the outputted overflow signal is used as a failure detection signal for the follow-up circuit.