JPH05342012A - Compiling method and compiler - Google Patents

Abstract

(57) [Abstract] [Purpose] A program is compiled independently of a digital signal processor and language. [Structure] In the language L _n front-end unit 1 _n , the preprocessing corresponding to the language L _n is performed on the source code of the program described in the language L _n (n = 1, 2, ..., N). Is performed and an intermediate code common to the languages L _{1 to} L _N is output. In the common module section 2, the intermediate code is subjected to processing independent of the languages L _{1 to} L _N and DSP _{1 to} DSP _M , and the back end section 3 _m (m = 1, 2) for the digital signal processor DSP _m .・ ・ ・ ・ ・ ・
In M), post-processing is performed on the output of the common module unit 2, and the digital signal processor DSP _m
The object code corresponding to is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiling method and a compiler suitable for compiling a DSP (digital signal processor) program used for digital signal processing such as voice processing and image processing.

[0002]

2. Description of the Related Art In recent years, in audio processing and image processing, in many cases, a signal (audio signal or image signal) is sampled, that is, the signal is digitized and, for example, DFT.
(Discrete Fourier transform), FFT (fast Fourier transform),
Alternatively, a signal on the time axis is converted into a signal (spectrum) on the frequency axis by DCT (discrete cosine transform) or the like, and parameter extraction and compression encoding processing are performed.

In such digital signal processing represented by the mutual conversion (DFT (inverse DFT), FFT (inverse FFT), DCT (inverse DCT), etc.) processing between the time axis and the frequency axis of the digital signal. The number of product-sum operations is extremely large, and when this processing is realized by, for example, a general-purpose CPU, it is difficult to perform real-time processing.

Therefore, a DSP (digital) having an architecture suitable for so-called pipeline processing and parallel processing and capable of performing a product-sum operation in, for example, several tens to several hundreds of nanoseconds, which is, so to speak, good at a product-sum operation process. Signal processors) have been developed, and in recent years, many digital signal processing devices (for example, image processing devices and audio processing devices) using this DSP have been realized.

[0005]

By the way, this DSP
In order to execute digital signal processing, first, it is necessary to write a digital signal processing program in the language for the DSP, compile the source code thereof with a compiler, and convert it into object code.

However, the language for describing the digital signal processing program is often different depending on the DSP, and even the same DSP may provide a plurality of languages for describing the program. For example, when a program of M DSPs can be written in N kinds of languages, M × N compilers corresponding to each DSP and each language must be prepared, which is inconvenient.

Note that the case where the language is different depending on the DSP means that the type of language is different depending on the DSP, and that the system is different depending on the DSP even if it is the same language (for example, the same C language in computer language). However, it depends on the manufacturer of the compiler).

Further, the compiler is composed of a plurality of logical operation units (phases) obtained by dividing the process of compiling a program. The above-mentioned DSPs and compilers corresponding to respective languages have DSPs and There are quite a few language-independent phases that can be shared with each other, and it was useless to provide this phase for each compiler.

The present invention has been made in view of such a situation, and makes it possible to compile a program without depending on the DSP and the language.

[0010]

A compiling method according to claim 1, wherein a source code of a program of a digital signal processor is converted into an intermediate code, and the intermediate code is converted into an object code corresponding to the digital signal processor. In the above, the intermediate code is common to a plurality of languages for writing a program of the digital signal processor or an object code corresponding to each of the plurality of digital signal processors.

[0011] The compiler according to claim 2, a digital signal processor DSP ₁ to the front end portion 1 (front language L ₁ end portion 1 ₁ of the pre-processing means for converting the source code of a program of DSP _M into an intermediate code To a language L _N front end unit 1 _N ), a common module unit 2 as a common processing unit for analyzing and optimizing an intermediate code output from the front end unit 1, and a digital output from the common module unit 2. Back-end unit 3 (DS) as a post-processing unit for converting into object code corresponding to the signal processors DSP _{1 to} DSP _M
P ₁ back end unit 3 _{1 to} DSP _M back end unit 3 _M ) and a front end unit 1 (language L ₁ front end unit 1 _{1 to} language L _N front end unit 1 _N )
Is a digital signal processor DSP _{1 to} DSP _M
Output intermediate code common to a plurality of languages L _{1 to} L _N for describing the program of the back end unit 3 (DSP).
Back end unit 3 ₁ to the back-end portion 3 _M for DSP _M) for _1, and converting the intermediate code into an object code corresponding to the plurality of digital signal processors DSP ₁ to DSP _M.

According to a third aspect of the present invention, the common module section 2 provides the common module section 2 with DSP _{1 to} DS for intermediate code.
It is characterized in that an optimization process that does not depend on any of P _M is performed.

According to a fourth aspect of the compiler, the back end unit 3 (the DSP ₁ back end unit 3 _{1 to the} DSP _M back end unit 3 _M ) divides the intermediate code into units that can be executed in parallel. It is characterized by being assigned to DSP _{1 to} DSP _M.

[0014] The compiler according to claim 5, the back end unit 3 (DSP ₁ for the back-end portion 3 ₁ to the back-end portion 3 _M for DSP _M), characterized in that to perform register allocation.

[0015]

In the compiling method according to claim 1,
The source code of the program of the digital signal processor is converted into an intermediate code common to a plurality of languages for writing the program of the digital signal processor, or an object code corresponding to each of the digital signal processors, and the intermediate code is digitally converted. Convert to the object code corresponding to the signal processor. Therefore, the program can be compiled independent of the DSP (digital signal processor) and the language.

In the compiler according to claim 2,
The source code of the program of DSP _{1 to} DSP _M is converted into an intermediate code common to the languages L _{1 to} L _N , and the intermediate code is analyzed and optimized. Then, the optimized intermediate code is converted into object codes respectively corresponding to DSP _{1 to} DSP _M. Therefore, the program can be compiled independent of the DSP (digital signal processor) and the language.

In the compiler according to claim 3,
In the common module section 2, for the intermediate code, DSP ₁
Since the optimization processing independent of any of DSP to DSP _M is performed, useless processing due to overlapping phases is prevented.

According to a fourth aspect of the compiler, the back-end unit 3 (the DSP ₁ back-end unit 3 _{1 to the} DSP _M back-end unit 3 _M ) divides the intermediate code into units that can be executed in parallel. Since it is assigned to DSP _{1 to} DSP _M , it is possible to effectively use the function of a DSP (digital signal processor) capable of parallel processing.

According to a fifth aspect of the compiler, the back end unit 3 (the DSP ₁ back end unit 3 _{1 to the} DSP _M back end unit 3 _M ) performs register allocation, so that a DSP (digital signal processor) is provided. The registers of can be used efficiently.

[0020]

1 is a block diagram showing the configuration of an embodiment of a compiler according to the present invention. Front end 1 is M
Digital signal processors DSP _{1 to} DSP _M
(Hereinafter, DSP _{1 to} DSP _M ) A source code of a program described in any one of the program description languages L _{1 to} L _N is converted into an intermediate code described in an intermediate language common to the languages L _{1 to} L _N. It is composed of a language L ₁ front end unit 1 _{1 to a} language L _N front end unit 1 _N to be converted. Each language L _n for the front-end unit 1 _{n (n} = 1,
2, · · ·, N) is constructed as a phase (the processing unit of compilation) shown in FIG. 2, lexical analyzer 11 _n, the parsing unit 12 _n, and the semantic analysis unit 13 _n, the language L _n
Perform processing depending on.

[0021] That is, the language L lexical analyzer 11 _n of the front end portion 1 _n for _n is the source code for a program written in a language L _n, a minimum unit that can be handled logically string (token) To separate. The syntax analysis unit 12 _n structurally analyzes the syntax composed of the lexical output from the lexical analysis unit 11 _n, and checks whether the syntax structure of the language L _n is allowed (syntax check). The semantic analysis unit 13 _n performs a semantic analysis on a syntax composed of lexical words, checks a semantic error in the syntax, and if there is no error, converts the source code into an intermediate code common to all the languages L _{1 to} L _N. ..

The common module section 2 is composed of a phase dependence analysis section 21 and an optimization section 22 shown in FIG. 3, and outputs from the language L ₁ front end section 1 _{1 to the} language L _N front end section 1 _N. The intermediate code to be processed is processed independent of the languages L _{1 to} L _N and DSP _{1 to} DSP _M.

That is, the dependency analysis unit 2 of the common module unit 2
Reference numeral 1 analyzes the data reference or definition dependency (data dependency) in the intermediate code output from the front end unit 1 and converts this dependency (data dependency) into a data structure called a so-called data flow graph. To do. The optimizing unit 22 refers to the data flow graph created by the dependency analyzing unit 21 as necessary, and with respect to the intermediate code output from the front end unit 1, for example, convolution of constants, identification of common subexpressions, etc. , L _{1 to} L _N and DSP _{1 to} DSP _M independent optimization processing.

The back end unit 3 is the common module unit 2
DSP that generates object code corresponding to DSP _{1 to} DSP _M from the intermediate code optimized by
₁ back-end section 3 _{1 to} DSP _M back-end section 3 _M
Composed of. Back end unit for each DSP _m 3 _m (m =
1, 2, ..., M) is composed of a scheduling unit 31 _m , a code generation / register allocation unit 32 _m , and an optimization unit 33 _m as the phase shown in FIG.
Perform processing depending on P _m .

That is, when the architecture of the DSP _m is such that the architecture of the DSP _m can perform parallel processing, the scheduling unit 31 _m can execute the intermediate code optimized by the common module unit 2 in units (tasks) that can be executed in parallel. ) And configure DSP _m , for example, ALU, multiplier, adder, or shifter. Code generation / register allocation unit 32 _m, from the intermediate code output from common module unit 2 (optimizing unit 22), generates an object code corresponding to the DSP _m, DSP _m
Performs register allocation for efficiently allocating variables to the registers of. The optimization unit 33 _m refers to the data flow graph created by the dependency analysis unit 21 of the common module unit 2 as necessary, and the object code corresponding to the DSP _m created by the code creation / register allocation unit 32 _m. Is subjected to optimization processing depending on DSP _m .

When a program for DSP _m written in the language L _n is compiled in the compiler configured as described above, first, the language L _{n of the} front end unit 1 is written.
The program is read into the front end unit 1 _n for use. Then, in the language L _n for the front end portion 1 _n of the lexical analyzer 11 _n (Fig. 2), the source code of a program written in a language L _n, e.g. clue words (for example, C
Language, FORTRAN, such as do, while, if, and for), identifiers (eg, variables in a program), constants, and operators (eg, +, −,
*, And / or the like) is separated into a character string (lexical) of the smallest unit that can be logically handled.

That is, in the lexical analysis unit 11 _n , for example, the FORTRAN statement of IF (5.EQ.MAX) GOTO 100 is the eight lexical phrases of IF, (, 5..EQ., MAX,), GOTO, and 100. Is separated into

The lexical separated by lexical analyzer 11 _n is input to the parsing unit 12 _n, the syntax analyzing unit 12 _n, the syntax comprising the lexical is structural analysis, allowed the syntactic structure of the language L _n The presence or absence is checked (syntax check). That is, for example, when the lexical characters A, +, and B are input, the syntax analysis unit 12 _n structurally analyzes the syntax A + B composed of the lexical characters A, +, and B as having a syntactic structure named as an expression, and the syntax A + B. Is checked (syntax check) as to whether or not is allowed as an expression described in the language L _n . If the syntax analysis unit 12 _{n determines} that an arbitrary syntax cannot be used in the syntax check, the compilation (the subsequent processing) is stopped.

The syntax that has passed the syntax check by the syntax analysis unit 12 _n is semantically analyzed by the semantic analysis unit 13 _n to check the semantic error of the syntax. That is, in the semantic analysis unit 13 _n , for example, a syntax A + B including three tokens of an integer type variable A, an operator +, and a real number type variable B.
Is analyzed as an addition expression of integer type and real number type, and it is checked whether addition of integer and real number is wrong. Language L
_If the specification of _n does not allow addition of an integer and a real number, the semantic analysis unit 13 _n disables the syntax A + B, and compilation (subsequent processing) is stopped.

The semantic analysis unit 13 _n has checked the semantic meaning of the syntax. If the syntax is correct, the source code is converted into an intermediate code common to all the languages L _{1 to} L _N , and the common module is used. It is output to the dependency analysis unit 21 (FIG. 3) of the unit 2.

In the dependency analysis unit 21, the semantic analysis unit 13
_In the intermediate code output from _n , the data reference or definition dependency (data dependency) is analyzed, and this dependency (data dependency) is converted into a data structure called a so-called data flow graph.

That is, for example, three equations A = B + C (1) B = A + E (2) B = F + G (3) are executed in the order of the equations (1), (2) and (3). Assuming that a program is described, the dependency analysis unit 21: A defined in Expression (1) is referenced in Expression (2) (flow dependence). B referenced in equation (1) is defined in equation (2) (reverse dependency). B referenced in equation (1) is defined in equation (3) (reverse dependency). B defined in equation (2) is redefined in equation (3) (output dependent). The dependency analysis is performed as described above, and the dependency relation (data dependency) of the reference or definition of this data is converted into a data structure called a so-called data flow graph.

After the data flow graph is created by the dependency analysis unit 21, the data flow graph is referred to by the optimization unit 22 as needed, and the intermediate code output from the semantic analysis unit 13 _n is For example, optimization processing that does not depend on DSP _{1 to} DSP _M , such as constant folding and common subexpression identification, is performed.

That is, for example, if the syntax I = 4 A = I * B is described in the language L _n in the program, the optimization unit 22 optimizes the above syntax as A = 4 * B. As a result, the number of definitions (I = 4) can be reduced.

Further, for example, if the syntax A [I + 1] = B [I + 1] * C [I + 1] is described in the language L _n in the program, the above-mentioned syntax is J = Optimized as I + 1 A [J] = B [J] * C [J], which can reduce the number of additions (I + 1) from 3 to 1.

The optimized intermediate code in the common module unit 2 of the optimization unit 22 is output to the DSP _m for the back-end portion 3 _m of the scheduling section 31 _m (Fig. 4), in the scheduling section 31 _m, DSP _m If the architecture of is capable of performing parallel processing, the intermediate code optimized by the common module unit 2 is divided into units (tasks) that can be executed in parallel, and each divided task is The DSP _m is composed of, for example, an ALU, a multiplier,
It is assigned (scheduled) to an adder, a shifter, or the like.

The code generating / register allocating unit 32
_{In m} , an object code corresponding to DSP _m is generated from the intermediate code output from the optimizing unit 22 of the common module unit 2, and register allocation for efficiently allocating variables to registers of DSP _m It is carried out, and an object code corresponding to the DSP _m is output to the optimization unit 33 _m. In the optimization unit 33 _m ,
If necessary, the data flow graph created by the dependency analysis unit 21 of the common module unit 2 is referred to, and the code generation /
The object code output from the register allocating unit 32 _m is subjected to optimization processing depending on DSP _m ,
Compiling of the program for DSP _m described in the language L _n is completed.

A program for realizing a 3-tap FIR digital filter with DSP _m is as follows: y (0) = h (0) * x (0) + h (1) * x (1) + h (2) * x (2 ) Y (1) = h (0) * x (1) + h (1) * x (2) + h (2) * x (3) y (2) = h (0) * x (2) + h (1 ) * x (3) + h (2) * x (4) as an example, the scheduling unit 31 _m of the back-end portion 3 _m for DSP _m, code generation / register allocation unit 32 _m, and the optimization unit 33 _m The operation will be further described. In addition,
In this program, h (0), h (1), and h (2) are filter coefficients, x (0), x (1), ...
• is the input signal to the filter, y (0), y (1), ...
・ Indicates the filter output.

When the above source code is expressed as an intermediate code, temp1 = h (0) * x (0) (a1) temp2 = h (1) * x (1) (a2) temp3 = h (2) * x (2) (a3) temp4 = temp1 + temp2 (a4) y (0) = temp3 + temp4 (a5) temp5 = h (0) * x (1) (b1) temp6 = h (1) * x (2) (b2) temp7 = H (2) * x (3) (b3) temp8 = temp5 + temp6 (b4) y (1) = temp7 + temp8 (b5) temp9 = h (0) * x (2) (c1) temp10 = h (1) * x (3) (c2) temp11 = h (2) * x (4) (c3) temp12 = temp9 + temp10 (c4) y (2) = temp11 + temp1 To become (c5).

Assuming that DSP _m has a sufficient number of registers, equations (a1) to (a5) and equation (b) are used.
1) to (b5) and equations (c1) to (c5) (hereinafter, referred to as equations (a1) to (c5)) have only the data dependence described above, that is, the equation (a1) and the equation (a1) When the flow dependence that the definition in a2) is referred to in expression (a4) is expressed as (a1), (a2) → (a4), expressions (a1) to (a5) and expressions (b1) to (b1) to (b1) b5) and the data dependence of the expressions (c1) to (c5) are (a1), (a2) → (a4) (a3), (a4) → (a5) (b1), (b2) → (b4). (B3), (b4) → (b5) (c1), (c2) → (c4) (c3), (c4) → (c5).

When the DSP _m does not have an architecture that can be executed in parallel, that is, when the DSP _m has only one 2-input 1-output arithmetic unit as an arithmetic unit, the scheduling unit 31 _m uses the formula (a1) The operations indicated by (c5) to (c5) are assigned (scheduled) to only one arithmetic unit incorporated in the DSP _m as shown in FIG.

That is, if the arithmetic unit incorporated in the DSP _m operates in one clock, the scheduling unit 31 _m executes the arithmetic operations represented by the expressions (a1) to (c5) at the 1st to 15th clocks, respectively. Assigned to be done in.

When the DSP _m has an architecture capable of being executed in parallel, that is, as the arithmetic units, for example, nine 2-input 1-output multipliers X _{1 to} X ₉ and 6
When the DSP _m has the 2-input 1-output adders Y _{1 to} Y ₆ , the scheduling unit 31 _m performs the operations represented by the expressions (a1) to (c5) by the multipliers X _{1 to} X included in the DSP _{m. 9} and adders Y _{1 to} Y ₆ are assigned (scheduled) as shown in FIG.

That is, the multipliers X _{1 to} X ₉ and the adder Y ₁
If Y to Y ₆ operate in one clock, in the scheduling unit 31 _m , at the first clock, the formula (a1)
To (a3), formulas (b1) to (b3), or formula (c
The operations (multiplication) indicated by 1) to (c3) are performed by the multiplier X.
_{1 to} X ₉ , respectively, and the operation (addition) represented by the formula (a4), (b4), or (c4) is performed by the adder Y ₁ , Y ₃ , or Y at the second clock. _Five
Assigned to take place respectively in 3
At the clock eye, expression (a5), (b5), or (c5)
The operation (addition) indicated by is the adder Y ₂ , Y ₄ , or Y
Assigned as done in ₆ respectively.

Further, the DSP _m has, for example, three 2-input 1-output multipliers X _{1 to} X ₃ and two 2-input 1-output adders Y ₁ and Y ₂ as arithmetic units. In this case, in the scheduling unit 31 _m , the operations represented by the formulas (a1) to (c5) are performed by the multipliers X _{1 to} X _{3 and the} adders Y ₁ and Y ₂ incorporated in the DSP _m as shown in FIG. Assigned (scheduled).

That is, the multipliers X _{1 to} X _{3 and the} adder Y ₁
If Y ₂ and Y ₂ operate in one clock, the scheduling unit 31 _m outputs the formula (a
The operations shown in 1) to (a3) are performed by the multipliers X _{1 to} X ₃
And the operations represented by the formulas (b1) to (b3) or the formula (a4) are performed by the multipliers X _{1 to} X ₃ or the adder Y ₁ at the second clock, respectively. And the operations represented by the formulas (c1) to (c3), the formula (b4), or the formula (a5) are assigned to the multipliers X _{1 to} X ₃ , the adder Y ₁ or Assigned as done in Y ₂ , respectively. Further, at the 4th clock, the operation represented by the formula (c4) or the formula (b5) is assigned to be performed by the adder Y ₁ or Y ₂ , respectively, and at the 5th clock, the formula (c5) is represented. The operations performed are assigned to be performed in adder Y ₂ .

Further, the DSP _m is, for example, as an arithmetic unit,
Two 2-input 1-output multipliers X ₁ and X ₂ and 1
In the case of having two 2-input 1-output adders Y ₁ , in the scheduling unit 31 _m , equations (a1) to (c5)
The operation indicated by is assigned (scheduled) to the multipliers X ₁ and X ₂ and the adder Y ₁ incorporated in the DSP _m as shown in FIG.

That is, the multipliers X ₁ and X ₂ and the adder Y
When ₁ is to operate in one clock, in the scheduling section 31 _m, a multiplier X _1, formula (a1), (a
3), (b2), (c1), or (c3) is assigned to be performed at each of the 1st to 5th clocks, and the multiplier X ₂ uses the expressions (a2), (b1),
The calculation represented by (b3) or (c2) is 1 to 4
It is assigned so as to be performed at each clock cycle, and at the adder Y ₁ , the equations (a4), (a5), (b
4), (b5), (c4), or (c5) is assigned so as to be performed at the second to seventh clocks, respectively.

When the scheduling by the scheduling unit 31 _m is completed, the code generation / register allocation unit 32
_{In m} , while register allocation for efficiently allocating variables to the register of DSP _m is performed, the DSP is changed from the intermediate code shown in formulas (a1) to (c5) to
_The object code corresponding to _m is generated.

DSP _m has three registers reg1 through r
In the case of having eg3, the code generation / register allocation unit 32
_{In m} , the variable t in equations (a1) to (c5)
emp1 to temp12 are registers reg1 to r
While being assigned to eg3, equations (a1) to (c)
From the intermediate code shown in 5), the object code corresponding to DSP _m is, for example, MUL h (0), x (0), reg1 (A1) MUL h (1), x (1), reg2 (A2) MUL h (2), x (2), reg3 (A3) ST reg3, mem1 (A4) ADD reg1, reg2, reg3 (A5) LD mem1, reg1 (A6) ADD reg1, reg3, y (0) (A7) MUL h (0), x (1), reg1 (B1) MUL h (1), x (2), reg2 (B2) MUL h (2), x (3), reg3 (B3) ST reg3, mem2 ( B4) ADD reg1, reg2, reg3 (B5) LD mem2, reg1 (B6) ADD reg1, reg3, y (1) (B7) MUL h (0), x (2 ), Reg1 (C1) MUL h (1), x (3), reg2 (C2) MUL h (2), x (4), reg3 (C3) ST reg3, mem3 (C4) ADD reg1, reg2, reg3 ( C5) LD mem3, reg1 (C6) is generated as ADD reg1, reg3, y (2) (C7).

Object code (A1) to (A3)
Are reg1 = h (0) * x (0), reg2 = h (1) * x (1), or reg3 = h (2) * x (2), respectively, and are expressed by equations (a1) to (a3). Corresponding to.
Since the DSP _m has only three registers reg1 to reg3, the contents of the register reg3 (expression (a (a4)
The contents of the variable temp3 in 3) is saved (stored) in the stack mem1 and the object code (A5)
Then, reg3 = reg1 + reg2 corresponding to the equation (a4) is calculated.

Then, in the object code (A6),
The variable te of the expression (a3) stored in the stack mem1
The contents of mp3 (h (2) * x (2)) are stored in the register re
The object code (A7) is loaded into g1 and y (0) = reg1 + reg3 corresponding to the expression (a5) is calculated.

Object codes (B1) to (B
7), or (C1) to (C7), in the same manner as in the case of the above object codes (A1) to (A7), the formulas (b1) to (b5) or (c1) to (c5) are respectively added. Corresponding processing is performed.

It should be noted that the DSP _m is, for example, three multipliers X each having two inputs and one output, which operate as one clock.
_{1 to} X ₃ , and two 2-input 1-output adders Y ₁ and Y ₂ , and if the data is loaded and stored in one clock, the above object code (A
1) to (A7), (B1) to (B7), and (C
1) to (C7) are executed as shown in FIG.

That is, at the first clock, the expressions (a1) to (a) corresponding to the object codes (A1) to (A3).
The operation shown in 3) is performed in each of the multipliers X _{1 to} X ₃ , and at the second clock, the operations shown in the expressions (b1) to (b3) corresponding to the object codes (B1) to (B3) are performed. , Multipliers X _{1 to} X ₃ respectively, and register r corresponding to the object code (A4)
Store to the stack mem1 of eg3.

At the third clock, the object code (C
Formula (c1) corresponding to 1) to (C3) or (A5)
To (c3) or the equation (a4) is performed in each of the multipliers X _{1 to} X ₃ and the adder Y ₁ , and the register r corresponding to the object code (B4)
The store of the eg3 to the stack mem2 is performed, and at the fourth clock, the operation represented by the expression (b4) corresponding to the object code (B5) is performed by the adder Y ₁ and the operation corresponding to the object code (C4) is performed. The register reg3 is stored in the stack mem3, and the register reg1 is loaded from the stack mem1 corresponding to the object code (A6).

At the 5th clock, the operation represented by the equation (c4) or (a5) corresponding to the object code (C5) or (A7) is performed by the adder Y ₁ or Y ₂ , respectively, and the object code The register reg1 is loaded from the stack mem2 corresponding to (B6), and at the sixth clock, the operation represented by the expression (b5) corresponding to the object code (B7) is performed by the adder Y ₂ and Object code (C
Register reg1 from stack mem3 corresponding to 6)
Is loaded.

At the 7th clock, the operation represented by the equation (c5) corresponding to the object code (C7) is
The processing is completed by the adder Y ₂ .

Next, as described above, an object code corresponding to the DSP _m is, when supplied to the optimization unit 33 _m, in the optimization unit 33 _m, with respect to the object code, depending on the DSP _m Optimization processing is performed.

That is, data is loaded from the memory mem to the register reg (D1) such as LD mem, reg (D1) ST reg, mem (D2), and the data of the register reg is immediately stored in the memory mem. In the object code indicating (D2), the same content (data) is stored in the memory m.
Since storing in em is useless, the optimization unit 33
_{At m} , the object code (D2) is deleted (redundant load / store instruction deletion).

Further, 0 is added to the register reg, such as ADD 0, reg, reg (E1) MUL 1, reg, reg (E2), and the register r is added.
In object code in which the result is stored in eg (E1) or the register reg is multiplied by 1 and stored in the register reg (E2), the addition of 0 and the multiplication of 1 do not change the result, which is also useless. From the optimization unit 3
At 3 _m , the object code (E1) and (E
Both 1) are deleted (algebraic reduction).

[0062] As described above, in this compiler front end portion 1 ₁ to Language language L ₁ corresponding to the language L ₁ to L _N describing the program L _N front end portion 1 _N
In Preprocess, performs post-processing in DSP ₁ to DSP ₁ for the back-end portion 3 ₁ to the back for DSP _M end portion 3 to output the object code corresponding to the DSP _{M M,} languages L ₁ to L _N and Since the common module unit 2 performs the processing (phase) that does not depend on the DSP _{1 to} DSP _M , the program written in any of the languages L _{1 to} L _N , and the DSP _{1 to} DSP _M A program compatible with any of the DSPs can be compiled.

[0063]

According to the compiling method of the first aspect, the source code of the digital signal processor (DSP) program corresponds to a plurality of languages for describing the DSP program or a plurality of DSPs. Converted to intermediate code common to object code,
The intermediate code is converted into an object code compatible with DSP. Therefore, regardless of DSP and language,
The program can be compiled.

According to the compiler of the second aspect, the source code of the program of the digital signal processor (DSP) is converted into an intermediate code common to the language, and the intermediate code is analyzed and optimized. Then, the optimized intermediate code is converted into an object code corresponding to each of the plurality of DSPs. Therefore, the program can be compiled independently of the DSP and the language.

According to the third aspect of the compiler, since the common processing means is caused to perform the optimization processing that does not depend on any of the plurality of DSPs with respect to the intermediate code, wasteful processing due to overlapping phases is eliminated. To be prevented.

A compiler according to a fourth aspect causes the post-processing means to divide the intermediate code into units that can be executed in parallel,
Since it is assigned to the DSP, it is possible to effectively use the function of the DSP capable of parallel processing.

The compiler according to the fifth aspect causes the post-processing means to perform register allocation, so that the registers of the DSP can be efficiently used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a compiler of the present invention.

FIG. 2 is a front end section 1 ₁ for a language L ₁ of the embodiment shown in FIG.
FIG. 6 is a diagram showing more details of the language L _N front end unit 1 _N.

FIG. 3 is a diagram showing more details of a common module unit 2 of the embodiment of FIG.

FIG. 4 is a diagram showing more details of the DSP ₁ back-end unit 3 _{1 to the} DSP _M back-end unit 3 _{M in} the embodiment of FIG.

5 is a diagram for explaining the scheduling performed by the scheduling unit of FIG.

FIG. 6 is a diagram for explaining scheduling performed by the scheduling unit of FIG.

FIG. 7 is a diagram for explaining scheduling performed by the scheduling unit of FIG.

FIG. 8 is a diagram for explaining scheduling performed by the scheduling unit in FIG.

9 is a diagram for explaining how the object code corresponding to the DSP _m generated by the code generation / register allocation unit 32 _m in FIG. 4 is executed.

[Explanation of symbols]

1 Front End Part 1 _{1 to} 1 _N Front End Part for Language L _{1 to} Language L _N Front End Part 2 Common Module Part 3 Back End Part 3 _{1 to} 3 _M Back End Part for DSP _{1 to} Back End Part for DSP _M 11n Lexical analysis unit 12n Syntax analysis unit 13n Semantic analysis unit 21 Dependency analysis unit 22 Optimization unit 31m Scheduling unit 32m Code generation / register allocation unit 33m Optimization unit

Claims (5)

[Claims] 1. A compiling method for converting a source code of a program of a digital signal processor into an intermediate code, and converting the intermediate code into an object code corresponding to the digital signal processor, wherein the intermediate code is of the digital signal processor. A compiling method characterized by being common to object codes corresponding to a plurality of languages for writing a program or a plurality of digital signal processors. 2. Preprocessing means for converting the source code of the program of the digital signal processor into intermediate code, common processing means for analyzing and optimizing the intermediate code output from the preprocessing means, and the common processing means. Post-processing means for converting the output from the digital signal processor into an object code corresponding to the digital signal processor, wherein the pre-processing means outputs an intermediate code common to a plurality of languages for describing a program of the digital signal processor. The post-processing means converts the intermediate code into object code corresponding to a plurality of digital signal processors, respectively. 3. The compiler according to claim 2, wherein the common processing means performs an optimization process on the intermediate code that does not depend on any of the plurality of digital signal processors. 4. The compiler according to claim 2, wherein the post-processing unit divides the intermediate code into units that can be executed in parallel and assigns the units to the digital signal processor. 5. The compiler according to claim 2, 3 or 4, wherein the post-processing means performs register allocation.