JPH05342014A - Data processing control method - Google Patents

Abstract

(57) [Summary] [Purpose] PL in operand access sequencer
The use of the field of A is minimized, the control is deleted for the entry in which the interrupt cannot occur, and the switching control by the interrupt is performed after limiting the interrupt to the possible interrupt. [Structure] 1-bit field 2 indicating interrupt enable
7, and 1 bit in the entry address also serves as the bit information 26 of the entry indicating that interrupt is possible. The determination of the interrupt condition and the address of the interrupt destination are performed by hardware, and the interrupt is permitted only when the 1-bit field 27 indicating the interrupt permission is on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor operand access control procedure for controlling an operand access stage as one stage of pipeline control.

[0002]

2. Description of the Related Art FIG. 7 shows an example of input / output to / from an operand access sequencer. In the figure, 1 is a request input to the operand access sequencer, 2
Is a Program Logic Array (hereinafter PL
A conventional operand access sequencer 3 using A) is the execution content output from the operand access sequencer 2.

FIG. 8 shows an example of a PLA bit field when a conventional operand access sequencer is implemented using PLA. In the figure, 4 is the upper 5 bits of the entry address, 5 is the lower 3 bits of the entry address,
6 is a sequence field that sets the sequencer to an end state when the sequencer end condition is satisfied, 7 is an access field that indicates the contents of access such as fetch and store,
8 is a translation index buffer mechanism (Transl) at the time of address translation.
(Operation Lookaside Buffer: hereinafter referred to as "TLB") Operand address operation field for instructing the operation of the second half page address when a page cross occurs during cache access, 9 indicates access to data from cache or external memory The data field 10 is an interrupt condition field indicating an interrupt condition, and 11 is an interrupt destination field indicating the upper 5 bits of the jump destination entry address when the interrupt condition is satisfied.

FIG. 9 schematically shows a peripheral hardware configuration related to the operand access sequencer according to this embodiment. 12 is a main memory, 13 is address translation and TLB, 14 is a line buffer, 15 is a cache, 16 is a circuit for generating an operand address, 17 is a virtual operand address, 18 is a logical operand address to be compared with the tag address of the line buffer, Reference numeral 19 indicates a logical operand address to be compared with the tag address of the cache, and 20 to 21 indicate the flow of operand data.

FIG. 10 is an example of operating according to the field contents of the PLA shown in FIG. 8 based on the hardware configuration shown in FIG. 9. Only the steps to be executed are extracted and shown as state transitions. .. 22 is a fetch entry, 23 is an entry when the cache page crosses, 24 is an entry when the first half page is line buffer hit by a subsequent instruction access, and 25 is a second half page is a line buffer hit by a subsequent instruction access. It is an entry when I did.

Next, in describing the operation of the operand access sequencer, its peripheral operation will be described. In FIG. 9, the operand address of the instruction is generated as a virtual address 17 by the operand address generation circuit 16, and the address is used for address translation and TLB.
13 is converted into a logical address. The logical address is compared 18 with the tag address in the line buffer 14, and if they match, a line buffer hit occurs. Further, the logical address is compared 19 with the tag address in the cache 15, and if they match, a cache hit occurs. When a cache miss occurs, transfer 20 of operand data from the main memory 12 is performed to the line buffer, and after registering the line buffer, data transfer 21 is performed from the line buffer to the cache. When the line buffer hits, the data is being transferred from the line buffer to the cache, and the line buffer and the cache are accessed again after waiting for the completion of the data transfer.

Next, an example of the operation will be described. In FIG. 7 and FIG. 8, the operand access sequencer 2 starts its operation when the request 1 is input. When the operand access sequencer receives the request, it generates the upper 5 bits 4 of the PLA entry address corresponding to the request, and according to the field contents 6 to 9 of the PLA by the 8-bit entry address in which the lower 3 bits 5 are added to the address. Run. When an entry address interrupt condition such as page cross or line buffer hit is satisfied after the entry is executed, the entry address 4 is switched according to the jump destination address of the interrupt destination field 11 and the next execution is performed. If the interrupt condition is not satisfied and the end condition is not satisfied, the entry address is 1
It is incremented and moves to the next execution.

An example of the execution procedure will be described below with reference to FIG. When the request accepted by the operand access sequencer is a fetch and cache page cross, the PLA entry address first indicates the fetch entry 22. In the first step of this entry, it is necessary to move the entry address to the entry 23 of the cache page cross fetch when the cache page cross occurs (when the interrupt condition is satisfied).
Since 0 and the interrupt destination field 11 are set, the execution shifts to the entry 23 of the page cross fetch of the cache after the end of the first step. If the subsequent instruction request is a line buffer hit, the interrupt condition is satisfied in the second step of this entry 23, and the designation of moving the entry address to the entry 24 of the line buffer hit is the interrupt condition field 10 and the interrupt destination field. Being touched by 11,
Execution moves to the entry 24 of the line buffer hit. Further, in the second step of the entry 24, the entry is designated to be moved when the interrupt condition is satisfied. However, if the condition is not satisfied here, the entry from the second step of the entry 24 to the entry 25 is performed. Execution does not shift to step 3, and the third step of entry 24 is executed.

[0009]

In the conventional configuration and control procedure as described above, since the address of the interrupt entry is specified by the interrupt destination field 11, the jump destination address due to the interrupt is the head of all entries. It is possible to indicate the address. However, the jump destination address due to the interrupt of the operand access sequencer is
Usually, it is limited to several types, and the entry steps in which an interrupt occurs are also limited. In other words, it is not always necessary to indicate the head addresses of all entries, or to generate fields to generate interrupts for all steps or to have a logical structure. For example, in FIG. 8, steps A to I are steps in which an interrupt may occur, but other steps are not used because all bits in the interrupt condition field 10 and the interrupt destination field 11 are zero. This is a wasted area.

The present invention has been made in order to solve such a problem and makes it possible to efficiently use the PLA field and delete the control of an entry in which an interrupt cannot occur. It is an object to obtain a data processing control method for controlling interrupts only.

[0011]

In the data processing control system according to the first invention, for example, a 1-bit field indicating an interrupt permission is provided in place of the interrupt condition field and the interrupt destination field of the conventional PLA. It has the following elements.
(A) a plurality of steps executed for processing the data; (b) a permission bit provided corresponding to the above steps and indicating whether or not each step can branch to another step;
(C) Control means for controlling the branch of the step based on the permission bit.

A data processing control system according to the second invention is
For example, one bit of an entry address is also used as the bit information of the entry indicating whether or not the entry can be interrupted, and in a data processing control system including a plurality of steps executed to process data, It is characterized in that at least one bit of the address at which the step exists is used as a branchable bit indicating whether the step can branch from another step.

[0013]

In the first aspect of the present invention, the bit provided only for interrupt switching is conventionally only the interrupt condition field and the interrupt destination field, but only one bit is the enable bit. Therefore, a useless area can be minimized. In the present invention, the interrupt determination using the conventional interrupt condition field and interrupt destination field is performed by the control means such as hardware in the present invention, and when the permission bit is set, the interrupt determined by the control means such as hardware is permitted. To do it.

Further, in the second invention, the predetermined bit of the address is set as the branchable bit, and the address at which the branchable bit is set is set as the destination address of the branch by the interrupt. Can be limited in advance, and the logical amount of the circuit required for generating the entry of the interrupt destination can be reduced.

[0015]

【Example】

Example 1. FIG. 1 shows a P when an operand access sequencer according to an embodiment of the present invention is realized by using a PLA.
An example of an LA bit field is shown. In the figure, 4 to 9 are the same as the conventional example shown above. Reference numeral 26 denotes an uppermost bit of the entry address and an interrupt enable bit (1 = enabled, 0 = disabled) indicating that the step can be interrupted by another step when the interrupt entry is enabled. Reference numeral 27 denotes an interrupt permission bit (1 = permitted, 0 = impossible) which indicates permission for switching the entry whether the entry may interrupt another entry.

Further, it is assumed that the processing corresponding to the interrupt condition field and the interrupt destination field shown in the conventional example is performed by hardware in this embodiment.
Therefore, the interrupt condition field and interrupt destination field shown in the conventional example do not exist in FIG.
Further, the input / output according to the present embodiment is the same as that in FIG. 7 shown in the above-mentioned conventional example, and the peripheral configuration of the operand access sequencer is the same as that in FIG. 10 shown in the above-mentioned conventional example.

The procedure will be described with reference to FIG. 2 assuming that the operand access sequencer has made a request similar to the conventional example.

When the request accepted by the sequencer is a fetch and the cache page crosses, the PLA
The entry address of indicates the fetch entry 28. The first step of this entry 28 can be interrupted when the interrupt condition is satisfied as indicated by the interrupt permission bit 27. However, not all entries can be interrupted, and the entries that permit interrupts are limited to the entries indicated by the interrupt enable bit 26.

That is, since the interrupt enable bit 26 of the entry indicated by X in FIG. 1 is 0, this part is a part that can be an entry address to enter at the beginning. In other words, it means that the address is not branched by an interrupt. Similarly,
The part indicated by Y in FIG. 1 is an interrupt enable bit 2
Since 6 is 1, it indicates an address that may possibly branch due to an interrupt. In other words, it indicates the part that is not the first entry executed.

Cache page cross entry 29
Is an interruptable entry, so if a cache page cross occurs, after the first step of entry 28, cache page cross fetch entry 29
Execution shifts to. When a subsequent instruction request hits the line buffer, the execution is shifted to the line buffer hit entry 30 after the second step ends due to the interrupt enable bit and the line buffer hit interrupt enable bit in the second step of this entry 29. .. Further, in the second step of this entry 30, an interrupt to the entry indicated by the interrupt enable bit 26 can be generated by the interrupt enable bit. However, if the interrupt condition is not satisfied here, it does not move to the entry 31. The third step of entry 30 is executed.

FIG. 3 is a diagram showing the meaning of each bit as to what the PLA output (each bit of the field) means when PLADAA 0:21 is related to the control of the computer thereafter. (0:21) indicates a signal line for transmitting 22 bits of data from the sequence field 6 to the interrupt permission bit 27 shown in FIG. As shown in FIG. 1, the 22nd bit (that is, bit 1) of each bit of the PLA indicates an interrupt enable bit 27. In FIG. 3, the 22nd bit is OSINT.
It is EN22P, and this is the signal generated by the interrupt permission bit 27 output from the PLA. Note that PH1H and PH2H indicate respective clocks of the two-phase clock, and PH1L and PH2L are inverted signals thereof.

Next, FIG. 4 is a diagram showing an example of an entry generation circuit for generating an entry at the beginning and an entry when an interrupt occurs. In the figure, A
Is a signal group indicating a boundary cross such as page cross or block cross, B is a signal group indicating the type of request (request such as fetch or store) currently being executed, C is a cache hit / miss, etc. A signal group indicating the cache state, D is a signal group indicating from which stage of the pipeline the request is made, E
Is a signal group indicating specific requests such as fetch and store.

FSTETY (1: 4) is a signal group indicating the entry address to enter at the beginning, and is (1: 4).
Indicate 1, 2, 3, and 4 of the address signal lines.
INTETY (1: 4) is a signal group indicating a jump address entered by an interrupt, and (1: 4) indicates 1, 2, 3, 4 of the address signal lines. The operand access sequencer 2 discloses the operation by the input of the request 1, but the hardware shown in FIG.
Calculate the conditions indicated by the C, D, E signals and determine all those signals before proceeding to the next step.

When it is determined whether or not an interrupt occurs by waiting for the interrupt condition field and interrupt destination field shown in the conventional example to be output from the PLA, the read time from the PLA and its determination time are set. Although both are required, in this embodiment, the processing corresponding to the interrupt condition field and the interrupt destination field can be performed by hardware as shown in the example in FIG. Therefore, it is not necessary to perform the operation of reading the interrupt condition field and the interrupt destination field from the PLA, and before the step having the interrupt enable bit 27 is executed and the interrupt enable bit is set as OSINTEN22P, or at least set as OSINTEN22P. At the same time, the address to be executed next is calculated. Therefore, according to this embodiment, the operation can be performed at a higher speed than the conventional one.

First, the entry address that is input first is output from FSTETY (1: 4). This FS
TETY (1: 4) is generated by inputting a signal group D indicating from which stage of the pipeline the request is made and a signal group E indicating a specific request such as fetch or store. INTETY (1: 4) is a signal group A indicating a boundary cross such as page cross or block cross, and a signal group B indicating the type of request (request such as fetch or store) currently being executed. It is generated as a jump address for making an interrupt (jump) according to the condition of the signal group C indicating the cache state such as cache hit / miss.

Next, FIG. 5 shows (1) an entry that enters first, (2) an entry that jumps by an interrupt,
(3) It is a circuit that determines which of the entries obtained by incrementing the address by 1 in order to execute the next step without causing an interrupt is actually executed. In the figure, F is a signal instructing to select an entry that enters first, G is a signal instructing to select an entry that enters first or an entry that is incremented, H is a signal that controls incrementing of an address, OSINTEN22P Is a signal for instructing (permitting) selection of an interrupt entry generated based on the interrupt enable bit 27 described in FIG. 3, PL
AADR (0: 7) is the entry that enters (1) above, (2) the entry that jumps by an interrupt,
(3) This signal indicates the address of the entry to be actually executed out of the entries obtained by incrementing the address by 1 in order to execute the next step without causing an interrupt.

Next, the operation will be described. As described above, the FSTETY (1: 4) generated by the signal groups D and E is the entry address performed first. Since bit 0 is used as an interrupt enable bit, it must be 0 for the first entry, and since the lower 3 bits of the input address are always 0, the requested bit is (1: 4). It will be good. Next, INTETY (1: 4) is obtained as the conditions of the signal groups A, B, and C are determined. This INTETY (1: 4) indicates an address at the time of interruption. Since the bit 0 of the address to be interrupted is always 1 and the lower 3 bits are always 0 according to the same idea as described above, the address to be obtained here may be (1: 4). As described above, since bit 0 of the entry address executed first is set to 0 and bit 0 of the interrupt address executed by the interrupt is set to 1, it is not necessary to consider the hardware configuration for bit 0. It is possible to reduce the logical amount related to entry generation.

An address obtained by adding 1 to the first entry address is also generated. This means that the address has already been calculated no matter which entry is to be performed next to the first entry. And FIG.
Determines which address to execute next.
That is, FSTETY (1: 4) is a bus for an address to be entered first, INTETY (1: 4) is a bus for a jump address when an interrupt occurs, and addresses after the second step thereafter are PLADR ( 0:
7) Enter. Then, in order for INTETY (1: 4) to be executed as an address to be executed next, the OS
It is necessary that INTEN22P (interruption enable bit) is ON.

As described above, this embodiment has the dynamic address conversion by the page address method, the TLB, the data cache, and the line buffer which temporarily holds the data when the data is transferred to the data cache. In the operand access sequencer of the microprocessor by the multi-stage pipeline processing capable of parallel access to the cache, an interrupt enable bit indicating entry switching permission is provided, and one bit in the entry address may interrupt when the interrupt entry is enabled. It is characterized by controlling the state transition of the above address conversion, TLB, cache, and line buffer access by also functioning as an interrupt enable bit indicating that it is possible. Characterized in that the advance limit the entry address by themselves.

As described above, according to this embodiment, only one field is used for interrupt switching control, and the field is composed of one bit.
Although the increase of the fields and bits inside is limited to 1 bit, the entry address can be generated only for the possible interrupts, so that the logical amount related to the entry generation can be reduced.

Example 2. In the above-described first embodiment, the case where the interrupt permission bit is 1 bit has been shown, but the interrupt permission bit is not limited to 1 bit and may be composed of a plurality of bits.

Example 3. In the first embodiment, the case where the conventional processing of the interrupt condition field and the interrupt destination field is performed by hardware has been described, but the determination of these conditions may be performed by firmware or software. Even when the condition is determined by the firmware or software, the same operation as that of the first embodiment can be performed by determining and using the 21st bit of the data output from the PLA as the interrupt enable bit.

Example 4. In the first embodiment described above, the case in which the interrupt enable bit 26 is also used as the most significant bit of the address is shown. However, it is not the case that only one bit is used as the interrupt enable bit, but as shown in FIG. Two
A bit may be used as the interrupt enable bit 26. In FIG. 6A, the case where the upper 2 bits are 00 is the address of the entry to be executed first, and the upper 2 bits are 01, 10 or 11 is the entry address executed by the interrupt. ing. Further, as shown in FIG. 6B, the second bit of the address may be used as the interrupt enable bit 26. For example, as shown in FIG. 6B, when the second bit is 0, the entry address is executed first, and when the second bit is 1, the entry address is executed by interrupt. You can divide it into In this way, there is a possibility of interruption,
By dividing the other addresses, it is possible to reduce the logical amount related to entry generation.

Example 5. In the first embodiment, PL
Although the case of using A has been described as an example, the present invention is not limited to PL.
The present invention can be applied not only to the case of using A but also to the case of using another device or apparatus.

[0035]

As described above, according to the first aspect of the present invention, it is possible to obtain the data processing control system in which the use of the field of the device is minimized without waste.

Further, according to the second aspect of the present invention, it is possible to separate an address which has a possibility of interruption and an address which does not have an interrupt, so that it is possible to reduce the logical amount relating to entry generation.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a PLA bit field when an operand access sequencer according to the present invention is realized by using a PLA.

FIG. 2 is a diagram showing, as state transitions, only steps for executing an example of operating according to the field contents of the PLA shown in FIG. 1 based on the hardware configuration shown in FIG. 9 according to the present invention. is there.

FIG. 3 is a diagram showing the meaning of a signal for each bit of a PLA output.

FIG. 4 is a diagram showing an example of an entry generation circuit that generates an entry upon entry and an entry upon occurrence of an interrupt.

FIG. 5 is a diagram showing a circuit for determining an entry to be executed next.

FIG. 6 is a diagram showing another embodiment of an interrupt enable bit according to the present invention.

FIG. 7 is a diagram showing an example showing input / output to and from an operand access sequencer.

FIG. 8 shows a conventional operand access sequencer PLA.
It is a figure which shows the PLA bit field example when implement | achieving using.

FIG. 9 is a diagram schematically showing a peripheral hardware configuration related to an operand access sequencer.

FIG. 10 is a diagram showing only the steps of executing an example of operating according to the field contents of the PLA shown in FIG. 8 based on the hardware configuration shown in FIG.
It is the figure shown as a state transition.

[Explanation of symbols]

1 request input to operand access sequencer 2 conventional operand access sequencer using PLA 3 execution content output from operand access sequencer 4 upper 5 bits of entry address 5 lower 3 bits of entry address 6 sequence field 7 access field 8 operand Address calculation field 9 Data field 10 Interrupt condition field 11 Interrupt destination field 12 Main memory 13 Address conversion and TLB 14 Line buffer 15 Cache 16 Operand address generation circuit 17 Virtual operand address 18 Line buffer comparison address 19 Cache comparison address 20-21 operand Data 22 Fetch entry 23 Cache page cross entry 24 lines Tsu file hit entry 25 second page line buffer hit entry 26 interrupt enable bit 27 interrupt enable bit 28 fetches entry 29 cache page crossing entry 30 line buffer hit entry 31 second page line buffer hit entry

Claims (2)

[Claims] 1. A data processing control method having the following elements: (a) a plurality of steps executed to process data, (b) provided corresponding to the above steps, and from each step to another step. Permission bit indicating whether branching is possible,
(C) Control means for controlling the branch of the step based on the permission bit. 2. A data processing control system comprising a plurality of steps performed to process data, wherein at least one bit of an address at which a step resides indicates whether that step can branch from another step. A data processing control method characterized by being used as a branchable bit.