JPH05342019A - Processor device - Google Patents

Abstract

(57) [Abstract] [Purpose] In the case where the time required to execute each task is short and the processing time of the OS at the time of occurrence of the event cannot be ignored compared to the time, the whole processor device concerned Improve the processing efficiency of. [Arrangement] The event occurrence flag 20 is for each task T1 to
Tm is a flag that can read whether or not an event has occurred. The event occurrence receiving means 10 uses the events E1 to En.
At each occurrence, the event occurrence flag 20 corresponding to this is set. The task switching means 14 assigns the tasks T1 to Tm to the tasks T1 to Tm.
Every time the execution right of m is abandoned, the run state is sequentially switched in a predetermined order. The processing on the operating system side such as the event occurrence receiving means 10 and the task switching means 14 can be reduced, and the overall processing efficiency can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor device which realizes multitasking by switching tasks which are in a run state in accordance with the occurrence of an event, and in particular, the time required to execute each task is short. The present invention relates to a processor device capable of improving the processing efficiency of the entire processor device when the processing time of an OS (operating system) at the time of the occurrence of an event cannot be ignored as compared with time.

[0002]

2. Description of the Related Art TSS (time s) developed at Bell Laboratories
UNIX, which is a general-purpose OS for haring system), provides a multi-user multi-tasking environment. Multiple users can perform multiple tasks while time-sharing computer resources. or,
Such a multi-tasking function is intended not only for the UNIX but also for various OSs, such as the UNIX, which is mainly used by operators such as the UNIX.
It is also realized by S, a measuring instrument, a communication device, a real-time OS used for controlling various machines, and the like.

FIG. 6 is a state transition diagram of task states of a conventional multiprocessor device having a multitasking function.

In FIG. 6, the states taken by each task in the conventional processor device, that is, the run state C11, the ready state C12, the idle state C13, and the wait state C14 are shown.
And a null state C15 is shown.

The run state C11 (execution state) is a state in which the corresponding task actually occupies the CPU (central processing unit) and the programs constituting the task are in execution. The ready state C12 (executable state) is a state in which various resources used by the corresponding task are secured and the CPU is waiting for allocation. The idle state C13 (end state) prepares an environment for execution of the task. Alternatively, it is in a state where the execution of the task is completed and preparations for releasing resources are made. The wait state C14 (waiting state) is a state in which the occupation of the CPU is abandoned in order to wait for the occurrence of a specific event such as securing various resources. The null state C15 is a state in which the OS having the multitasking function does not recognize the existence of the task.

According to the processor device having such a multi-tasking function, for example, the above-mentioned multi-user OS can be realized, and the real-time operation of a relatively large measuring device or communication control device can be realized. It is possible to realize the convenience of control.

[0007]

However, the above-mentioned U
In a conventional OS having a multitasking function such as NIX, an OS for realizing the multitasking function
Occasionally, the CPU occupancy time for executing the above process may become a problem. For example, the processing time for switching the task in the run state or switching the task state of each target task may become a problem due to the occurrence of an event.

For example, in UNIX, when a certain event occurs, when there are a plurality of tasks having the event, the OS temporarily transits all of the plurality of tasks to the ready state C12. After that, only one of the plurality of tasks is set to the run state C11.
When the task in the run state occupies the resource related to the event, the OS again shifts the remaining tasks to the wait state C14 (event waiting state).

In the UNIX, when an abnormality occurs in the processing performed by a task or when an exception event occurs such as when various errors occur, a signal is sent to other tasks related to this. , Notifies the occurrence of the event. If the task receiving the notification is in the wait state C14, the OS sets the task in the ready state C1.
Transition to 2. Also, when there are a plurality of tasks related to such an exception event, the OS performs such processing for a plurality of tasks.

As described above, in the conventional OS having the multitasking function such as UNIX, the processing time related to the multitasking function sometimes becomes a problem. Especially when the time required to execute each task executed by multitasking is relatively short,
The processing time for the multitasking function of the OS becomes a problem that cannot be ignored.

The present invention has been made to solve the above-mentioned conventional problems. In the processor device which realizes multi-tasking by switching the tasks which are in the run state in accordance with the occurrence of an event or the like, the individual tasks are executed. The time required for execution is short, and the O
An object of the present invention is to provide a processor device capable of improving the processing efficiency of the entire processor device even when the processing time of S cannot be ignored.

[0012]

SUMMARY OF THE INVENTION According to the present invention, in a processor device which realizes multitasking by switching tasks which are in a run state in accordance with the occurrence of an event or the like, an event occurrence flag by which each task can read the presence or absence of the event occurrence. A storage unit having an event occurrence reception unit that sets the event occurrence flag corresponding to the event occurrence time, and the plurality of tasks in a predetermined order for each execution of the task execution rights. A task switching means for sequentially switching to a run state, and processing corresponding to the event in each task is executed by confirming the event occurrence flag in each task,
The above object has been achieved.

[0013]

The present invention relates to a case where the time required for executing each task is short and the processing time of the OS at the time of occurrence of the event cannot be ignored as compared with the time, and the processor device in such a case is used. In order to improve the overall processing efficiency, the processing contents performed by each task and the processing contents performed by the OS are carefully examined. That is, the processing efficiency of the entire processor device is improved by reassessing the sharing of the processing performed by each task and the processing performed by the OS.

FIG. 1 is a block diagram showing the gist of the present invention.

As shown in FIG. 1, the processor of the present invention is characterized by an event occurrence receiving means 10 and
A predetermined storage means having an event occurrence flag 20 and a task switching means 14. Further, in the processor device of the present invention, a task group T including a plurality of tasks T1 to Tn is executed.

The event occurrence flag 20 is a flag that allows the tasks T1 to Tn to read out whether or not an event has occurred. That is, the event occurrence flag 20 indicates that the event has occurred and is "0" if, for example, "1" is set in the address corresponding to an event in the storage means from which the tasks T1 to Tn can be read. For example, it means that there is no occurrence.

When the events E1 to En occur, the event occurrence accepting means 10 sets a flag at a predetermined address of the event occurrence flag 20 corresponding to the event. For example, when a certain event E1 to En is from the outside of the processor device, the event occurrence receiving means 10 is activated by a hardware interrupt and sets the corresponding flag upon occurrence of the event E1 to En. Further, for example, when the generated events E1 to En are internal, the event generating means 10 is activated by a software interrupt and sets the corresponding flag.

The task switching means 14 sequentially switches the plurality of tasks T1 to Tn to the run state C11 in a predetermined order each time the execution right of each task is abandoned. That is, when a certain task in the run state C11 relinquishes the execution right, the task switching unit 14 determines another task which is predetermined to be in the run state C11 next to the task for which the execution right is relinquished. The run state C11 is set.

Note that, in FIG. 1, the event occurrence receiving means 10 and the task switching means 14 may be realized, for example, by processing within the OS. The present invention does not limit this. That is, the event occurrence receiving means 10 and the task switching means 14 may be means provided in advance for the plurality of tasks T1 to Tn.

As described above, according to the present invention, the processing performed when an event occurs is only the setting of the event occurrence flag 20 corresponding to the event occurrence.
Further, the processing performed by each of the tasks T1 to Tn also requires the event occurrence flag 20 required by each of the tasks T1 to Tn.
This is a process in which the processing time is relatively short because only the read-out is required. Therefore, according to the present invention, the processing efficiency of the entire processor device can be improved.

[0021]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention.

In FIG. 2, a processor device which is an inter-network connection device for connecting the network N1 and the network N2 is shown. The inter-network connection device can simultaneously perform a plurality of communications between these two networks N1 and N2.

The inter-network connecting device has an event occurrence flag 20 consisting of a reception request flag 20a, a line abnormality flag 20b, a relay request flag 20c, a transmission request flag 20d, and an available buffer existence flag 20e. ing. Further, the inter-network connection device has a line interface 30, a task execution right control unit 32, a buffer management unit 34, and a transmission / reception buffer 36. Further, in the inter-network connecting device, the communication processing between the network N1 and the network N2 is mainly performed by a plurality of receiving tasks TR1 to TRn and 1
One relay task TT and a plurality of transmission tasks TS1 to TS
formed by n and.

The reception request flag 20a and the line abnormality flag 20b are set by the driver program of the OS provided for the line interface 30 when a hardware interrupt occurs in the line interface 30 due to various causes. To be done. For example, when reception data from the network N1 or N2 is fetched into the reception buffer in the line interface 30, one of the corresponding reception request flags 20a is set. Alternatively, the network N1
Alternatively, if an abnormality occurs in a certain communication performed in N2, or if an abnormality occurs in the network N1 or N2 itself, the line abnormality flag 20b corresponding to the abnormality that has occurred is set.

The relay request flag 20c is used for transmitting a relay request between the receiving tasks TR1 to TRn and the relay task TT. The relay request flag 20c is
It is set by the receiving tasks TR1 to TRn and read by the relay task TT. The transmission request flag 20
d is the relay task TT and the transmission tasks TS1 to T
It is used to transmit a transmission request with Sn. The transmission request flag 20d is set by the relay task TT,
It is read by the transmission tasks TS1 to TSn.

Available buffer existence flag 20e
Are used to detect the presence / absence of an empty buffer area of the transmission / reception buffer 36 at each time in the reception tasks TR1 to TRn and the transmission tasks TS1 to TSn. The available buffer existence flag 20e is
When the buffer management unit 34 allocates an area in the transmission / reception buffer 36 to the reception tasks TR1 to TRn or the transmission tasks TS1 to TSn, a flag corresponding to the area is set.

The task execution right control unit 32 performs processing related to the task execution right such as switching the task state of each of the reception tasks TR1 to TRn, the relay task TT, and the transmission tasks TS1 to TSn. The transmission / reception buffer 36 uses the reception task TR1.
~ TRn are used when receiving received data from the line interface 30, and the transmission tasks TS1 to TS
It provides a buffer area used when n transmits from the line interface 30. The transmission / reception buffer 36
Has a total of 6 buffer areas of equal buffer capacity.

When the receiving tasks TR1 to TRn enter the run state C11, the receiving request flag 20a is received.
The presence / absence of reception from the network N1 or the network N2 is checked by. When the reception is confirmed, the reception tasks TR1 to TRn check the availability of the available buffer existence flag 20e to see if there is an empty area in the transmission / reception buffer 36. When the empty area is confirmed, a reception buffer request is made to the buffer management unit 34, and the reception process is executed after the reception buffer is acquired. Depending on the protocol of the communication performed in the network N1 or N2, there is a protocol in which the reception completion notification must be transmitted to the transmission source of the communication when the reception processing is completed. In this case, the reception completion notification is transmitted after the reception process ends after the reception buffer is acquired. Further, in the reception processing, the data sent from the network N1 or N2 is stored in the acquired reception buffer, the validity of the data is checked, and the line abnormality of the network N1 or N2 is constantly checked. The line abnormality flag 20b is used for monitoring.
At the end of the reception process, the relay request flag 20
A corresponding flag of c is set and a relay processing request is made to the relay task TT.

The relay task TT uses the run state C1.
When it becomes 1, the relay processing request from the receiving tasks TR1 to TRn is monitored by reading the relay request flag 20c. When there is a relay processing request, the relay task TT makes a transmission request to the corresponding transmission tasks TS1 to TSn, judging from the relay destination of the data for which the relay processing request has been made, so the corresponding transmission task Request flag 2
Set 0d.

When the transmission tasks TS1 to TSn enter the run state C11, the transmission tasks TS1 to TSn check the transmission request flag 20d to confirm whether or not there is a transmission request from the relay task TT. When there is a transmission request, the transmission tasks TS1 to TS
By reading the available buffer existence flag 20e, n confirms whether or not there is an empty area available as a transmission buffer in the transmission / reception buffer 36. If there is an empty area, a transmission buffer is acquired via the buffer management unit 34, transmission data is set, and transmission from the line interface 30 is performed. Depending on the protocol of communication performed in the network N1 or N2, there is one that receives a reception completion notification from the other party after the completion of the transmission processing. Such processing is performed by the transmission tasks TS1 to T1.
Sn does. During the transmission processing in the transmission tasks TS1 to TSn, the line abnormality flag 20b is read to constantly monitor the line abnormality of the networks N1 and N2.

FIG. 3 is a diagram showing the structure of the ready task queue of the above embodiment.

In FIG. 3, a total of four tasks A to A corresponding to the reception tasks TR1 to TRn, the relay task TT, and the transmission tasks TS1 to TSn shown in FIG.
D is shown for convenience. These four tasks A in total
D (task 40) is TCB (task control)
block) 40a and task body 40b.
The execution task pointer 42 indicates the position of the TCB 40a or the like of the task being executed.

In FIG. 3, when the task A relinquishes the execution right, the task B enters the run state C11, and when the task B relinquishes the execution right, the task C enters the run state C11. When the task D abandons the execution right, the task D enters the run state C11, and when the task D abandons the execution right, the task A enters the run state C11. The order of transition of the execution rights of these tasks A to D is predetermined, and is fixed in this embodiment.

From the viewpoint of effective use of the area of the transmission / reception buffer 36, the reception buffer and the transmission buffer are shared in this embodiment. As described above, when a plurality of tasks share the transmission / reception buffer 36, all the buffer areas may be in use. Also, even during such use, a plurality of tasks may issue a buffer use request. When the buffer is released in such a case, an event occurs that the transmission / reception buffer becomes available, and a situation occurs in which a plurality of tasks transit to the conventional wait state C14 of FIG. However, in the present embodiment, there is no state corresponding to the wait state C14, and for example, when an event occurs due to the release of the buffer as described above, the task waiting for the event causes the task at the beginning of the process to start. The event occurrence is confirmed by reading the available buffer existence flag 20e at.

For example, when the task C of FIG. 3 is waiting for a buffer release event and the event occurs while the task B is executing, as shown in the upper part of FIG. Task C is abandoned and task C is in run state C1
When it becomes 1, the program of the task C confirms the occurrence of the buffer release event at this point. If the buffer is not released even though the task C is in the run state C11, the task C abandons the execution right and the buffer is used when the next execution right is obtained. I hope it is possible. Therefore, when an event such as buffer availability occurs, when a plurality of tasks are waiting for the event, the task to which the execution right is given first acquires the right to use the event.

FIG. 4 is a state transition diagram of the task state of the above embodiment.

As shown in FIG. 4, in this embodiment, the wait state C as shown in FIG. 6 is used.
14 is gone. In the present embodiment, the task execution right control unit 32, which is a part of the OS, only switches the task among the run state C11, the ready state C12, and the idle state C13. And processing time is getting shorter.

FIG. 5 is a time chart showing transitions of task states in the above embodiment.

In FIG. 5, there are shown time charts of (1) the case of the conventional OS and (2) the case of the present embodiment, which can be compared with each other. In FIG. 5, the symbols 1 to 5 are as follows.

： Wake up task waiting for event ： Switch task ： Execute task ： Sleep waiting event ： Store event ： Check event

As shown in FIG. 5, when an event occurs in the conventional OS, a total of four codes are processed in order to wake up a total of four tasks A to D.
On the other hand, in the present embodiment, only the processing indicated by the code for storing the occurrence of the event is performed, and the processing time is shortened. Further, in the case of the conventional OS, when the resources corresponding to the event generated by the task A are already occupied even though the tasks B to D are woken up,
It takes a relatively long time to perform processing such as sleeping again.
In comparison, in the present embodiment, tasks B to D are relatively simple processes of simply reading the flag corresponding to the event occurrence, and the processing time is also short.

[0043]

As described above, according to the present invention, the time required to execute each task is shortened in the processor device which realizes multi-tasking by switching the tasks in the run state in accordance with the occurrence of an event. Even when the processing time of the OS at the time of occurrence of the event cannot be ignored compared to the time, it is possible to obtain an excellent effect that the processing efficiency of the entire processor device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing the structure of a ready task queue of the above embodiment.

FIG. 4 is a state transition diagram of task states of the above embodiment

FIG. 5 is a time chart showing transitions of task states in the above embodiment.

FIG. 6 is a state transition diagram of a conventional processor device having a multitasking function.

[Explanation of symbols]

 10 ... Event occurrence receiving means 14 ... Task switching means 20 ... Event occurrence flag 20a ... Reception request flag 20b ... Line error flag 20c ... Relay request flag 20d ... Transmission request flag 20e ... Available buffer existence flag 30 ... Line interface 32 ... Task Execution right control unit 34 ... Buffer management unit 36 ... Transmission / reception buffer 40 ... Whole task 40a ... TCB (task control block) 40b ... Task body 42 ... Execution task pointer C11 to C15 ... Task state E1 to En ... Event N1, N2 ... Network T ... Task group T1 to Tm ... Tasks TR1 to TRn ... Reception task TT ... Relay task TS1 to TSn ... Transmission task

Claims (1)

[Claims] 1. In a processor device that implements multitasking by switching tasks that are in a run state in accordance with the occurrence of an event, etc., each task has a storage means having an event occurrence flag capable of reading the presence or absence of an event occurrence. When an event occurs, an event occurrence receiving unit that sets the event occurrence flag corresponding to the event, and a task that sequentially switches the plurality of tasks to a run state in a predetermined order each time the execution right of each task is abandoned. A processor device comprising: a switching unit, wherein processing corresponding to the event in each task is executed while checking the event occurrence flag in each task.