JPH05344017A - Radio equipment of superheterodyne system - Google Patents

Abstract

PURPOSE:To provide a superheterodyne system radio equipment in which the circuit is made small in size and the power consumption is reduced. CONSTITUTION:A superheterodyne system radio equipment having at least stages of frequency conversion stages or over (1st mixer 2 and 2nd mixer 5) is provided with a fixed frequency oscillator and a mixer 22 used to down- convert an output frequency of a PLL frequency synthesizer 21, a loop of the PLL is formed by using a down-converted frequency and an output frequency of the PLL frequency synthesizer 21 is given to a 1st stage frequency converter (1st mixer 2) as a local oscillating frequency, the output frequency of the fixed frequency oscillator 24 is frequency-divided by a frequency divider 25 and the result is used for the local oscillating frequency for the 2nd and succeeding stages of the frequency conversion stages (2nd mixer 5).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superheterodyne radio apparatus having at least two frequency conversion stages.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional double superheterodyne receiver. In the figure, 1
Is a high frequency amplifier, 2 is a first mixer, 3 is a first intermediate frequency filter, 4 is a first intermediate frequency amplifier, 5 is a second mixer, 6
Is a second intermediate frequency filter, 7 is a second intermediate frequency amplifier, 8
Is a first local oscillator, 9 is a second local oscillator, and 10 is a detection circuit.

In the double super-heterodyne receiver having the above-mentioned structure, the modulated wave received at the input terminal IN is amplified by the high frequency amplifier 1, and the first local oscillator 8 by the first mixer 2.
Is mixed with the local oscillation output from the first intermediate frequency filter 3, becomes a first intermediate frequency signal through the first intermediate frequency filter 3, and is amplified by the first intermediate frequency amplifier 4. Further, the first intermediate frequency signal is
The local oscillation output from the second local oscillator 9 is mixed in the mixer 5, amplified by the second intermediate frequency amplifier 7 via the second intermediate frequency filter 6, and added to the detection circuit 10.

[0004]

In recent years, TDMA (Time Division Multiple Acces
In a wireless device that performs s: time division multiple access communication, a fast-switching frequency synthesizer is indispensable as the first local oscillator, and in order to achieve this frequency synthesizer, a preset frequency synthesizer (19
Various methods such as the 90th IEICE Autumn Meeting B-308) and a multi-frequency synthesizer have been proposed. However, all of these have a problem that the circuit becomes large in scale and power consumption increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a superheterodyne radio apparatus having a small circuit and low power consumption.

[0006]

In order to solve the above problems, the present invention provides a PLL in a superheterodyne radio apparatus having at least two frequency conversion stages.
A fixed oscillator and a mixer for down-converting the output frequency of the frequency synthesizer are provided, and a PLL loop is assembled at the down-converted frequency.
The output frequency of the L frequency synthesizer is given to the first frequency conversion stage as a local oscillation frequency, and the output frequency of the fixed oscillator is frequency-divided to be the local oscillation frequency of the second and subsequent frequency conversion stages. ..

[0007]

According to the present invention, as described above, in the super-heterodyne radio apparatus having at least two or more frequency conversion stages, the output frequency of the VCO of the PLL frequency synthesizer for the first local is town-converted at a certain fixed frequency, which is low. When the frequency is set to form a PLL loop, the frequency modulation sensitivity of the VCO does not change, but the frequency division ratio becomes small, so that the loop gain becomes large and, as a result, the lockup time becomes short. Also, the fixed frequency for down conversion is divided into the second
If the local oscillation frequencies of the second and subsequent stages are made equal, the local oscillators of the second and subsequent stages can be eliminated, and the circuit size and power consumption can be reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a super-heterodyne wireless device of the present invention. The wireless device includes a high frequency amplifier 1, a first mixer 2, a first intermediate frequency filter 3,
The configuration including the first intermediate frequency amplifier 4, the second mixer 5, the second intermediate frequency filter 6, the second intermediate frequency amplifier 7 and the detection circuit 10 is the same as the configuration of the double super heterodyne receiver of FIG. 21 is a PLL frequency synthesizer,
22 is a third mixer, 23 is a first LPF (low-pass filter) or BPF (band-pass filter), 24 is a fixed oscillator, 25 is a frequency divider, and 26 is a second LPF or BPF.

The output of the PLL frequency synthesizer 21 is supplied to the third mixer 22 at the same time as the first mixer 2, and is down-converted by the oscillation output from the fixed oscillator 24 in the third mixer 22 and, if necessary, the first LPF or BPF. After removing the unnecessary wave by, the signal is fed back to the PLL synthesizer 21.

The lock-up time of the PLL frequency synthesizer becomes faster as the natural frequency ω _{n of the} PLL increases.
The natural frequency ω _n is given by the following equation when the PLL loop fill uses a lag-lead filter as shown in FIG. K: Loop gain coefficient N: Frequency division ratio of programmable counter

When the output frequency of the PLL frequency synthesizer 21 is f ₀ and the reference frequency f _r , the output frequency f ₀ is represented by f ₀ = _Nfr (2), and (1) and (2) From the formula Becomes In the case of the present invention, the output frequency is down-converted to f ₀ to be a low frequency, thereby increasing the natural frequency ω _n and speeding up the lockup time.

On the other hand, the oscillation output of the fixed oscillator 24 is also supplied to the frequency divider 25 at the same time as the third mixer 22.
After being divided by N, the LPF or BP may be used as necessary.
After removing the unwanted wave in F26, it is added to the second mixer 5. For this reason, the second local oscillator, which has been conventionally required, is unnecessary, and the circuit can be downsized and the power consumption can be reduced.

Further, by dividing the oscillation output of the fixed oscillator 24 by M to obtain the frequency after the third local oscillator and the frequency of the local oscillator on the transmitting side, each local oscillator becomes unnecessary, and the circuit is miniaturized and the power consumption is reduced. It is also possible to use electricity.

[0014]

As described above, according to the present invention, the following excellent effects can be obtained. (1) The natural frequency ω _n of the PLL can be increased and the lockup time can be shortened by down-converting the output frequency of the PLL frequency synthesizer with the output frequency of the fixed oscillator to a low frequency.

(2) By dividing the output frequency of the fixed oscillator by a predetermined frequency to obtain the local oscillation frequency of the frequency conversion stages of the second and subsequent stages, the local oscillator of the frequency conversion stages of the second and subsequent stages is not required, and the circuit size is reduced. And low power consumption can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a super-heterodyne radio apparatus of the present invention.

FIG. 2 is a diagram showing a configuration example of a PLL loop fill.

FIG. 3 is a block diagram showing a configuration of a conventional double super heterodyne receiver.

[Explanation of symbols]

 1 High Frequency Amplifier 2 1st Mixer 3 1st Intermediate Frequency Filter 4 1st Intermediate Frequency Amplifier 5 2nd Mixer 6 2nd Intermediate Frequency Filter 7 2nd Intermediate Frequency Amplifier 10 Detection Circuit 21 PLL Frequency Synthesizer 22 3rd Mixer 23 1st LPF or BPF 24 fixed oscillator 25 frequency divider 26 second LPF or BPF

Claims (1)

[Claims] 1. A super-heterodyne radio apparatus having at least two or more frequency conversion stages, wherein a fixed oscillator and a mixer for down-converting the output frequency of a PLL frequency synthesizer are provided, and the PLL at the down-converted frequency is provided. An output frequency of the PLL frequency synthesizer is applied to the first frequency conversion stage as a local oscillation frequency, and the output frequency of the fixed oscillator is divided by a predetermined frequency to be the local oscillation frequency of the second and subsequent frequency conversion stages. A superheterodyne wireless device characterized by the above.