JPH0534708A - Liquid crystal display manufacturing method - Google Patents

Abstract

(57) [Abstract] [Purpose] To reliably form a fine pattern wiring layer such as a signal line in an active matrix liquid crystal display device. In forming a wiring layer connected to a thin film transistor in a liquid crystal pixel of a liquid crystal display device, after forming a _first wiring layer M ₁ formed by patterning a first conductive layer,
A second conductive layer is deposited and formed on this and patterned to form a _second wiring layer M ₂ , and a wiring layer having a laminated structure of the first and second wiring layers is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method for manufacturing an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Active matrix liquid crystal display devices are
As shown in FIG. 4, the liquid crystal pixels 62 are driven by the switching elements 61 arranged in a matrix.

In FIG. 4, 63 is the vertical scanning circuit,
Reference numeral 64 represents a video signal sample hold circuit. C _S is
In the above-described configuration, the switching element 61 is turned on to write an electric potential to the liquid crystal pixel 62, and then an additional capacitance for holding the potential for a predetermined period is shown. The additional capacitance is provided for each pixel 62.

Such an active matrix liquid crystal display device is remarkably popularized because the problem of crosstalk between pixels is improved and a fine image display can be performed.

In the liquid crystal display device having this structure, each switching element 61 is composed of, for example, a thin film transistor, and one of the source / drain (S /
The wiring layer, that is, the signal line L _S is derived from the region D). The signal line L _S is usually composed of an Al metal layer.

On the other hand, in this type of liquid crystal display device, in order to form the effective screen of the liquid crystal pixel in the smallest possible fixed area with the largest possible area, it is necessary that the signal line L _S be as narrow as possible. Will occur. On the other hand, in order to form the signal line L _S as a sufficiently low resistance layer, it becomes necessary to make the thickness as large as possible as the width of the signal line L _S becomes narrower.

Normally, the thickness of the Al signal line L _S is 0.
It is selected to be 6 μm or more. The Al signal line L _S is usually formed by forming an Al conductive layer on the entire surface and then forming it into a predetermined pattern by pattern etching by photolithography. That is, an Al layer is formed over the entire surface in ohmic contact with at least a predetermined S / D region of a thin film transistor of a predetermined switching element 61, and a photoresist is applied, exposed, and developed on the Al layer to form a predetermined pattern. Is used as an etching resist, that is, as a mask for etching, to remove the Al exposed to the outside without forming a photoresist layer by wet etching to form the signal line L _S with an Al wiring layer having a predetermined pattern. To be taken.

However, in the case of such wet etching, since the etching is isotropic, A
Etching that penetrates under the etching resist not only in the thickness direction of l but also in the surface direction progresses, which makes it difficult to surely form sufficiently thick Al in a predetermined narrow pattern by etching. In the case where it is formed over the stepped portion of the surface, if the thick Al layer is thinly patterned in this stepped portion, disconnection is likely to occur due to the in-plane etching thereof, which is problematic in terms of reliability.

[0009]

SUMMARY OF THE INVENTION The present invention makes it possible to reliably form a fine pattern with high reliability when forming a wiring layer in the above-mentioned liquid crystal display device.

[0010]

FIG. 1 shows a sectional view of an example of a liquid crystal display device obtained by the method of the present invention, and FIGS. 2 and 3 show manufacturing process diagrams of the manufacturing method of each example. 2A, when forming a wiring layer, that is, a signal line L _S connected to a thin film transistor TFT as a switching element in a liquid crystal pixel of a liquid crystal display device, the first conductive layer 81 is entirely covered as shown in FIG. 2A. 2B, the step of forming an etching resist 91 having a predetermined pattern on the first conductive layer 81, and the first conductive layer 81 using the patterned etching resist 91 as a mask as shown in FIG. 2B. Wet etching the first
Of forming a wiring layer M _1, and forming a second conductive layer 82 entirely on the first wiring layer M ₁ as shown in FIG. 2C, the second as shown in FIG. 3A A step of forming an etching resist 92 in a predetermined pattern on the conductive layer 82, and as shown in FIG. 3B, the second conductive layer 82 is wet-etched using the etching resist 92 as a mask to form a _second wiring layer M ₂ . 3C, the wiring layer 54 having the laminated structure of the first and second wiring layers M ₁ and M ₂ is formed as shown in FIG. 3C.

[0011]

According to the above-described method of the present invention, finally, for example, the signal line L _S is formed by the wiring layer 54 having a predetermined pattern,
A first wiring layer M ₁ is first formed by etching a predetermined pattern, then the wiring layers by you take the step of patterning the second wiring layer M ₂ M ₁
Since M ₂ and M ₂ may be formed to have a thin thickness of, for example, about ½ of the finally obtained wiring layer 54, the etching of the conductive layers 81 and 82 is wet etching of the thin conductive layer. Therefore, even if these are isotropic etchings and the etching progresses in the lateral direction, that is, in the surface direction of each of the first and second conductive layers 81 and 82, the etching amount in the surface direction is sufficiently smaller than the conventional one. Therefore, the wiring layer 54 having a required thickness can be surely formed in a fine pattern, which allows the wiring layer 54 to extend over the stepped portion on the surface having the stepped portion. Even in the case of forming, it can be surely formed without causing disconnection.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention can be applied, for example, to obtain the liquid crystal display device shown in FIG. The example of FIG. 1 is a transmissive active matrix liquid crystal display device, and in this case, substrates 1 and 2 facing each other made of transparent substrates such as glass and quartz, respectively.
Is provided, a pixel electrode 51 corresponding to each pixel is formed on one substrate 1, and a counter electrode 52 is provided on the other substrate 1.

A liquid crystal layer 3 filled with liquid crystal is sandwiched between the substrates 1 and 2.

A semiconductor layer 4 made of, for example, a polycrystalline silicon layer is formed on the inner surface of one substrate 1.

In the semiconductor layer 4, source / drain (S / D) regions 5 and 6 which form a thin film transistor TFT which becomes a switching element 61 of each pixel, and a channel forming region 7 are formed between them.

Further, the channel forming region 7 of the semiconductor layer 4 is formed.
A gate insulating layer 8 is formed on the gate insulating layer 8, and a gate electrode 9 is formed on the gate insulating layer 8 to form the thin film transistor TFT.
Is configured.

In the illustrated example, the gate insulating layer 8 of the thin film transistor TFT is made of, for example, Si in order to increase the breakdown voltage.
It is formed by a lower first insulating layer 31 made of O ₂ and a second insulating layer 32 made of, for example, Si ₃ N ₄ thereon.

On the other hand, in the other portion of the substrate 1, the additional capacitor C _S is formed in the same step as the fabrication of the thin film transistor TFT at the same time. The additional capacitance C _S forms a low resistivity region in a part of the semiconductor layer 4 formed on the substrate 1,
And one of the first electrode 21 constituting the additional capacitance C _S of this, the dielectric layer 2 constituting the additional capacitance C _S of the insulating layer having the same configuration as the gate insulating layer 8 of the thin film transistor TFT
3, the second electrode 22 is formed on the gate electrode 9 simultaneously with the formation of the gate electrode 9, and an additional capacitance C _S is formed between the electrodes 21 and 22.

Reference numeral 53 is an interlayer insulating layer made of, for example, PSG (phosphorus silicate glass) formed so as to cover the thin film transistor TFT, the additional capacitor C _S, etc., and the semiconductor layer 4 is formed through a contact window 53W ₁ formed in the insulating layer 53. Of the thin film transistor TFT, which is connected to one S / D region 5 of the low resistivity, that is, the high concentration S
In the / D area, the wiring layer 54 that becomes the signal line L _{S made of} an Al layer or the like connected to the sample hold circuit 64 shown in FIG.
However, he is contacted ohmic.

Further, an interlayer insulating layer 53 similar to the one described above is further formed thereon, and the thin film transistor T
A low-resistivity contact region 10, that is, a high-concentration S / D region is formed adjacent to the other S / D region 6 of the semiconductor layer 4 of the FT, and a contact window 53W ₂ formed in the interlayer insulating layer 53 in this region 10 Through, the liquid crystal pixel electrode 51 provided for each liquid crystal pixel is ohmic-contacted.

Particularly, in the present invention, this is particularly used to form the wiring layer 54, that is, the signal line L _S by making electrical contact with the source / drain region 5 of the thin film transistor TFT through the contact window 53W ₂ of the interlayer insulating layer 53. It has a two-layer structure of the first wiring layer M ₁ and the second wiring layer M ₂ .

An example of the manufacturing method of the present invention is shown in FIG.
And FIG. 3 will be described in detail. 2 and 3
The same reference numerals are given to the parts corresponding to those in FIG.
Omit it. In this case, as shown in FIG.
Contact window 53W drilled in 3 ₁Through the semiconductor layer 4
Of the first conductor to make ohmic contact with a predetermined part of
The electrode layer 81 is entirely formed by sputtering, vapor deposition, or the like.
It The first conductive layer 81 is the wiring layer 54 to be finally obtained.
For example, a half of the thickness of
It can be formed by an Al metal layer containing 1%.

Then, an etching resist 91 having a pattern corresponding to the pattern of the wiring layer 54, that is, the signal line L _S to be finally obtained on the first conductive layer 81 is formed to have a predetermined line width W _{1 of,} for example, 2.0 μm. .. That is, as is well known, a photoresist layer is applied over the entire surface and exposed and developed to form an etching resist 91 having a predetermined pattern.

As shown in FIG. 2B, the first wiring layer 81 is subjected to wet etching, for example, wet etching with phosphoric acid, using the etching resist 91 as an etching mask to form the _first wiring layer M ₁ . In this case, the first wiring layer M ₁ is relatively thin, for example 0.3 μm.
Since the thickness of the first wiring layer M ₁ is formed to a certain level, in this case, it is possible to reduce the surface direction etching that enters below the edge portion of the etching resist 91, so-called side etching, and to obtain the first wiring layer M ₁ thus obtained. Width W _M1 is 1.5μ
It became m.

Next, as shown in FIG. 2C, the etching resist 91 is removed, and a second conductive layer 82 including the first wiring layer M ₁ is formed on the entire surface by vapor deposition, sputtering or the like.
As the second conductive layer 82, for example, similarly, for example, 0.3 μ, which is half the thickness of the wiring layer 54 to be finally obtained, is used.
m of Al or ITO, or the same material as the first conductive layer 81 described above, that is, Al containing 1% of Si, for example.

Next, as shown in FIG. 3A, an etching resist 92 having a pattern corresponding to the finally obtained wiring layer 54 is formed on the second conductive layer 82. This etching resist 92 can be formed by applying, exposing, and developing a photoresist like the above etching resist 91.
In this case, the width W ₂ of the etching resist 92 is the first
Of a width larger than the width W _M1 of the wiring layer M ₁ of, for example, 2.5 μm
To form.

After that, the second conductive layer 82 is etched by wet etching using the etching resist 92 as an etching mask to form a _second wiring layer M ₂ . In this case, the width of the _second wiring layer M ₂ is
If it becomes the width W _M2 than the width W ₂ smaller the etching resist 92 by the side etching, for example, the width W ₂ of the etching resist 92 is 2.5 [mu] m, 2.0Myu
The width can be suppressed to about m.

Thus, according to the present invention, the wiring layer 54
Is formed by patterning the first wiring layer M ₁ and then by patterning the second wiring layer M ₂ to form the first and second wiring layers M ₁ and M ₂ . Since the first and second conductive layers 81 and 82 may be, for example, half the thickness of the wiring layer 54 to be finally obtained, it is possible to perform reliable pattern etching with less side etching, and thus finally. The width of the obtained wiring layer 54, that is, the signal line L _S can be formed in a pattern having a predetermined width, and the pattern etching may be performed on the first and second conductive layers 81 and 82 having such small thicknesses. If
Even when there is a step such as a step around the contact window 53W ₁ of the interlayer insulating layer 53 on the surface where the wiring layer 54 is formed, the wiring layer can be reliably patterned.

In the above-mentioned example, the present invention has been described with reference to the wiring layer 54 serving as the signal line L _S of the active matrix type liquid crystal display device, but it is not limited to the formation of other wiring layers in the liquid crystal display device. The present invention can be applied.

In the above example, the wiring layer 54
To the first and second wiring layers M₁And M ₂With a two-layer structure
In this case, the structure of two or more layers, that is, FIGS.
By repeating the process described in 1.
It is also possible to adopt the above laminated structure of wiring layers.
It

[0031]

As described above, according to the present invention, the first and second or more wiring layers M ₁ , M _2, ... Formed by sequentially etching the wiring layers 54 in the liquid crystal display device, respectively.
By adopting the above laminated structure, the wiring layer 54 can be reliably formed with high reliability, and the yield and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an example of a liquid crystal display device obtained by a manufacturing method of the present invention.

FIG. 2 is a partial process chart of an example of the manufacturing method of the present invention.

FIG. 3 is a partial manufacturing process diagram of an example of the manufacturing method of the present invention.

FIG. 4 is a configuration diagram of a liquid crystal display device.

[Explanation of symbols]

4 Semiconductor Layer 81 First Conductive Layer 82 Second Conductive Layer 91 Etching Resist 92 Etching Resist M ₁ First Wiring Layer M ₂ Second Wiring Layer 54 Wiring Layer L _S Signal Line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/12 A 8728-4M 29/784

Claims (1)

Claim: What is claimed is: 1. When forming a wiring layer connected to a thin film transistor in a liquid crystal pixel of a liquid crystal display device, a step of forming a first conductive layer over the entire surface, and the first conductive layer. A step of forming an etching resist having a predetermined pattern thereon; a step of wet-etching the first conductive layer using the patterned etching resist as a mask to form a first wiring layer; Forming a second conductive layer on the wiring layer over the entire surface; forming an etching resist having a predetermined pattern on the first conductive layer; and using the patterned etching resist as a mask, And a step of forming a second wiring layer by wet etching the second conductive layer to form a wiring layer having a laminated structure of the first and second wiring layers. Method of manufacturing a liquid crystal display device which.