JPH05347359A - 集積回路上の多レベルメタライゼーション構造およびその形成方法 - Google Patents

集積回路上の多レベルメタライゼーション構造およびその形成方法

Info

Publication number
JPH05347359A
JPH05347359A JP5029572A JP2957293A JPH05347359A JP H05347359 A JPH05347359 A JP H05347359A JP 5029572 A JP5029572 A JP 5029572A JP 2957293 A JP2957293 A JP 2957293A JP H05347359 A JPH05347359 A JP H05347359A
Authority
JP
Japan
Prior art keywords
metal
layer
nitride
dielectric material
sectional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5029572A
Other languages
English (en)
Japanese (ja)
Inventor
M Moslehi Mehrdad
エム．モスレヒ メールダッド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH05347359A publication Critical patent/JPH05347359A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP5029572A 1991-12-31 1993-01-04 集積回路上の多レベルメタライゼーション構造およびその形成方法 Pending JPH05347359A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81645691A 1991-12-31 1991-12-31
US816456 1991-12-31

Publications (1)

Publication Number Publication Date
JPH05347359A true JPH05347359A (ja) 1993-12-27

Family

ID=25220676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5029572A Pending JPH05347359A (ja) 1991-12-31 1993-01-04 集積回路上の多レベルメタライゼーション構造およびその形成方法

Country Status (4)

Country Link
EP (1) EP0550910A1 (2)
JP (1) JPH05347359A (2)
KR (1) KR100297901B1 (2)
TW (1) TW218422B (2)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
JPH08172132A (ja) * 1994-09-15 1996-07-02 Texas Instr Inc <Ti> マルチレベル相互接続部の容量および性能を最適化する素子および方法
US6255712B1 (en) * 1999-08-14 2001-07-03 International Business Machines Corporation Semi-sacrificial diamond for air dielectric formation
DE10034020A1 (de) 2000-07-07 2002-02-07 Infineon Technologies Ag Metallisierungsanordnung für Halbleiterstruktur und entsprechendes Herstellungsverfahren
WO2007093931A1 (en) * 2006-02-13 2007-08-23 Nxp B.V. Interconnect structure and method of manufacture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525733A (en) * 1982-03-03 1985-06-25 Eastman Kodak Company Patterning method for reducing hillock density in thin metal films and a structure produced thereby
JPS63249394A (ja) * 1987-04-06 1988-10-17 日本電気株式会社 多層回路基板
JPH02220464A (ja) * 1989-02-22 1990-09-03 Toshiba Corp 半導体装置及びその製造方法
JP3074713B2 (ja) * 1990-09-18 2000-08-07 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR100297901B1 (ko) 2001-10-22
EP0550910A1 (en) 1993-07-14
TW218422B (2) 1994-01-01
KR930014953A (ko) 1993-07-23

Similar Documents

Publication Publication Date Title
US5372969A (en) Low-RC multi-level interconnect technology for high-performance integrated circuits
US6016000A (en) Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics
US6143646A (en) Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
US6124198A (en) Ultra high-speed chip interconnect using free-space dielectrics
US5614765A (en) Self aligned via dual damascene
US5900668A (en) Low capacitance interconnection
KR100522130B1 (ko) 웨이퍼 패시베이션 구조 및 제조방법
US6566737B2 (en) Passivation structure for an integrated circuit
US6762120B2 (en) Semiconductor device and method for fabricating the same
US5543360A (en) Method of making a semiconductor device with sidewall etch stopper and wide through-hole having multilayered wiring structure
US6121146A (en) Method for forming contact plugs of a semiconductor device
US6870263B1 (en) Device interconnection
US4920403A (en) Selective tungsten interconnection for yield enhancement
WO2000035000A1 (en) Ultra high-speed semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectric
US20110086470A1 (en) Additional metal routing in semiconductor devices
US6071812A (en) Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes
JPH05347359A (ja) 集積回路上の多レベルメタライゼーション構造およびその形成方法
KR100257481B1 (ko) 플러그 금속막을 구비한 반도체 소자의 금속배선 형성방법
US6399471B1 (en) Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
JPH05251566A (ja) 多層配線構造
JP3210462B2 (ja) 半導体装置の製造方法
KR100398584B1 (ko) 반도체 소자의 제조 방법
JPH07235619A (ja) 高特性集積回路のための低ｒｃ多重レベル相互接続技術
HK1022380A (en) Damascene structure comprising surrounding liner