JPH05347364A - Cell structure of semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to provide a semiconductor integrated circuit which has a low cost and a high degree of freedom for high integration. In a cell arranged in a semiconductor integrated circuit, when wiring a predetermined signal line to the cell, a P-channel diffusion region and an N-channel diffusion region forming the cell are mutually insulated by insulating layers. At least one layer of conductive layers other than the first conductive layer, which are connected to each other through one of the wiring layers formed of a plurality of conductive layers formed in isolation The wiring layer made of (5) directly forms a direct contact portion with a predetermined portion located in the cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell structure of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the development of manufacturing technology for LSIs and the like, higher integration and higher speed of LSIs and the like have become necessary.
However, as the degree of integration of LSIs increases, the proportion of wiring regions in LSIs increases. Incidentally, in the conventional cell structure, as shown in FIG. 7, a wiring region is provided outside the cell, and the increase of the wiring region hinders high integration of the semiconductor integrated circuit. .

In the conventional semiconductor integrated circuit, the power supply wiring layer as shown in FIGS. 7 and 8 is fixedly provided inside the cell 1, and the signal line thereof is the outer peripheral edge of the cell 1. Many were formed on the part. That is, the cell 1 is provided with the P-channel 2 and the N-channel 3 as diffusion layers, and the P-channel diffusion layer 2 has contact portions C2, C.
4 and C3 are connected to the first power supply line (V _DD ) 4 and the N-channel diffusion layer 3 has a contact portion C5,
It is connected to the second power supply line (V _SS ) 5 via C8 and C9.

On the other hand, the contacts C6 and C7 in each diffusion region
The aluminum wiring 6 is connected to and a desired signal is output to the outside of the cell. Further, in FIG. 7, reference numeral 8 denotes a polysilicon conductive layer which acts as a gate and connects the P-channel 2 and the N-channel 3 to each other, and at the end thereof, the wiring layer 10 at the bottom layer via the contact C1. And a contact C10 at the other end of the lowermost wiring layer 10.
Is connected to the second conductive layer 20 through.

As can be seen from FIG. 7, the conductive layer 20 forming the second layer forms the input terminal IN, and a necessary signal is supplied to the inside of the cell via the input portion contact 9 provided outside the cell. It is input to the transistor. In addition, P- as a diffusion layer
Aluminum wiring 6 connecting channel 2 and N-channel 3
Acts as a signal output terminal OUT, but in the prior art, since the output aluminum wiring 6 is formed by the same wiring layer 10 as the lowermost layer as the power supply line, the degree of freedom of the wiring is high. It was restricted.

That is, in the example of the inverter shown in FIG. 7, the inverter is composed of two wiring layers provided outside the cell, and thereby the degree of freedom in wiring design is obtained. .. However, in the conventional semiconductor integrated circuit, the first power supply line (V _DD ) 4 which is the wiring for the power supply is used.
Since the second power supply line (V _SS ) 5 and the connection wiring 7 are formed in the first layer, the wiring area of the signal line for signal transmission inevitably exists in the outer peripheral edge portion of the cell. It was formed.

Therefore, in the prior art, a predetermined area is required especially in the signal wiring region of the semiconductor integrated circuit, and on the other hand, the signal wiring region is expanded as the integration degree of cells of the semiconductor integrated circuit is improved. Since this is unavoidable, it has been a hindrance to high integration and miniaturization of semiconductor integrated circuits. Further, in the prior art, when the first layer wiring (lowermost layer) made of a conductive layer and the second layer wiring are formed in the same cell to form an electrical contact, as shown in FIG. As shown, the contact portions C30 and C40 of each wiring layer are generally formed at different positions.

This is because, for example, once the contact portion C30 is formed in the lowermost wiring layer 10, unevenness is formed on the upper surface of the contact portion, so that the portion corresponding to the second conductive layer 20 is different. If the contact portions C40 are overlapped, defective formation of the contact portions may occur, which may cause defective products.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to provide a wiring area inside a cell mounted inside a semiconductor integrated circuit to provide a wiring area in an LSI. (EN) Provided is a cell structure of a semiconductor integrated circuit which can reduce the area to be filled and improve the degree of integration.

[0010]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, in a cell arranged in a semiconductor integrated circuit, when wiring a predetermined signal line to the cell, a P-channel diffusion region and an N-channel diffusion region forming the cell are formed.
A structure in which the channel diffusion region and the channel diffusion region are connected to each other through one of the wiring layers formed of a plurality of conductive layers separated from each other by an insulating layer, and other than the lowermost wiring layer A direct contact portion in which a wiring layer composed of at least one of the conductive layers directly or in a substantially vertical state through the wiring layer at the bottom directly makes contact with a predetermined portion located in the cell. And a cell structure of a semiconductor integrated circuit using the wiring layer as a signal wiring.

[0011]

According to the present invention, in a cell of a semiconductor integrated circuit, a metal commonly formed on the surface of a gate layer made of a polysilicon layer connecting both diffusion layers forming the cell or both diffusion layers. The signal wiring is simplified because one of the second or more multi-layered layers is formed directly on the metal source / drain made of a thin film to form the contact portion without being obstructed by the first wiring layer. In addition to simplifying the wiring design, the signal wiring group can be formed inside the cell, so that the cell structure of the semiconductor integrated circuit can be highly integrated and downsized. Further, the configuration according to the present invention enables automation of signal wiring.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the semiconductor integrated circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram for explaining the principle of the semiconductor integrated circuit according to the present invention and is a plan view showing a specific example of the semiconductor integrated circuit according to the present invention.

That is, in the concrete example of FIG. 1, a P-channel 2 and an N-channel 3 as diffusion layers are provided in the cell 1, and the P-channel diffusion layer 2 is provided with a contact portion C11 at the top. A first power supply line (V _DD ) 4 composed of a lower wiring layer (first conductive layer) 10 is connected, and the N
The channel diffusion layer 3 is the second power supply line (V _SS ) 5 composed of the lowermost wiring layer 10 via the contact portion C12.
Are connected.

On the other hand, in this embodiment, a polysilicon conductive layer 8 which connects the P-channel 2 and the N-channel 3 to each other and acts as a gate is formed, and the polysilicon conductive layer is further formed. The signal wiring 30 formed of the second conductive layer 20 is formed so as to overlap with No. 8.
The end portion of the signal wiring 30 constitutes the input terminal portion IN. Further, in the present invention, the second conductive layer 2
The signal wiring 30 formed of 0 is directly contacted with the polysilicon conductive layer 8 which is a predetermined portion of the cell regardless of the wiring layer (first conductive layer) 10 at the lowermost layer to form the direct contact portion DC1. is doing.

Further, in the embodiment of the present invention, the signal output wiring 6 is composed of the second conductive layer 20, and one end thereof constitutes the output terminal OUT. The signal output wiring 6 is connected to the P-channel diffusion layer 2 via a contact portion DC2 regardless of the lowermost wiring layer 10, and the N-channel diffusion layer 3 has a contact portion. It is connected via DC3 regardless of the lowermost wiring layer 10.

That is, in this example, when forming the wiring layer by forming the first and second conductive layers on the cell, the first power supply line (V _DD ) 4 and the first power supply line (V _DD ) 4 are connected. 2 power lines (V _SS )
5 and 5 are formed in the lowermost wiring layer, the input wiring 30 and the output wiring 6 which are the signal wirings are formed in the second conductive layer 20, and the second conductive layer 20 makes the cell 1 predetermined. part,
That is, the gate portion or each diffusion region portion is directly connected,
This is what constitutes a so-called direct contact portion DC.

The structure of the direct contact portion according to the present invention is not particularly specified, but FIG.
As shown in (A), the lowermost wiring layer 10 is not formed, or the lowermost wiring layer 10 is penetrated to connect the second conductive layer 20 directly to a predetermined portion 26 of the cell 1. The contact portion may be formed, or, as shown in FIG. 6B, the second conductive layer 20 is vertically formed by laminating on the contact portion formed by the lowermost wiring layer 10. By forming the contact part of the
The contact portion may be formed by connecting to the predetermined portion 26 of the cell 1 through the 0 contact portion. Such a structure has become possible in recent years due to the establishment of a technique for flattening the surface of the contact portion when forming a contact using a conductive layer.

In the present invention, any of the above structures is defined as a direct contact portion. As is clear from FIG. 6, the lowermost wiring layer 10 and the second conductive layer 2
An appropriate insulating film 25 is present between 0 and 0, or between the lowermost wiring layer 10 and the cell, if necessary. Also, the predetermined portion 2 of the cell 1 in the embodiment of the present invention
6 may be the polysilicon conductive layer 8 or either of the diffusion regions. Further, as will be described later, it may be a metal source / drain composed of a metal thin film commonly formed on the surfaces of the both diffusion regions.

Further, in the present invention, the conductive layer forming the wiring layer does not have to be limited to two layers and may be composed of a plurality of layers of two or more layers. Further, the conductive layer used in the present invention may be mainly composed of metal or may be composed of a conductive material such as polysilicon.

FIG. 2 is a diagram showing another specific example according to the present invention, which basically has the same configuration as the specific example shown in FIG. 1, except that the P-channel in the cell is different. The diffusion layer 2 and the N-channel diffusion layer 3 have a structure in which a metal source / drain composed of a metal thin film commonly formed on the surfaces of both diffusion regions is provided to electrically integrate both diffusion regions. It is what you are doing.

Therefore, in this embodiment, the output side signal wiring portion 6 formed especially from the second conductive layer 20 is the lowermost wiring layer 10 in the direct contact portion DC5 provided at one place. Irrespective of the above, it is connected to the metal source / drain surface of the P-channel diffusion layer 2. The direct contact portion DC4 in FIG. 2 has the same structure as the direct contact portion DC1 in FIG. In the above-mentioned two specific examples of the present invention, by adopting such a configuration, the signal wiring possible regions H1 to H3 as shown in FIG. 1 are formed, and the signal wiring as shown in FIG. Possible areas H4 to H6 are formed. In addition, in the area other than the power supply wirings 4 and 5 and the direct contact DC in the cell, an area in which the first wiring of the conductive layer can be formed is provided. Of course, the wiring made of the second conductive layer can also be provided by avoiding the input and output wirings.

Further, the range in which the direct contact portion DC according to the present invention can be arranged has a considerable degree of freedom, and FIG.
FIG. 2 is a view showing an arrangement possible range of the direct contact portion in the cell structure corresponding to the specific example of FIG. 1. That is, in FIG. 3, the necessary minimum number may be arranged within the direct contact portion disposable range R1 to R8 shown in the figure. In this specific example, the direct contact portion does not overlap with the power supply line, but if the complete penetrating means is used, the direct contact portion is formed even on the power supply line. Things are possible.

FIG. 4 shows the possible arrangement area of the direct contact portion in the cell structure corresponding to the specific example of FIG. That is, in FIG. 4, the minimum number of direct contact portions of the input signal wiring portion 30 may be arranged within the direct contact portion disposable range R9 to R12. Further, the minimum number of direct contact portions of the output signal wiring portion 6 may be arranged within the direct contact portion disposable range R13 to R15. In the present invention, by registering the structure of each cell described above in the memory that constitutes the cell library in advance, when the semiconductor integrated circuit such as the LSI is designed, the automatic signal wiring including the signal wiring in the cell is included. Design becomes possible.

[0024]

According to the present invention, since the above configuration is adopted, the wiring area is provided inside the cell mounted inside the semiconductor integrated circuit, and the area defined by the wiring area in the LSI is defined. The present invention provides a cell structure of a semiconductor integrated circuit capable of reducing the number of charges and improving the degree of integration. Specifically, as shown in FIG. 8, in the conventional semiconductor integrated circuit, the signal wiring SL group is formed only in the W between the cell array stages SA1 to SA3. Therefore, a necessary gap is provided between the cell array stages. However, it is impossible to reduce the size of the semiconductor integrated circuit. However, by adopting the configuration of the present invention, not only the inter-cell array stage W as shown in FIG. Since the signal wiring SL can be formed inside the cell as well, it is possible to reduce the signal wiring density between the cell array stages by that amount, so that the interval between the cell array stages can be reduced, which is why It is also possible to reduce the size of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a principle explanatory diagram according to the present invention, and is a plan view showing a specific example regarding a structure of a cell used in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a plan view showing another specific example of the structure of the cell used in the present invention.

FIG. 3 is a diagram showing an arrangement possible range of a direct contact portion in the structure of the cell shown in FIG.

FIG. 4 is a diagram showing an arrangement possible range of a direct contact portion in the structure of the cell shown in FIG.

FIG. 5 is a cross-sectional view showing a wiring relationship in a cell of a conventional semiconductor integrated circuit.

FIG. 6 is a cross-sectional view showing a wiring relationship in a cell of a semiconductor integrated circuit according to the present invention.

FIG. 7 is a plan view of the structure of a cell used in a conventional semiconductor integrated circuit.

FIG. 8 is a diagram showing a layout of cells and wirings of a conventional semiconductor integrated circuit.

FIG. 9 is a diagram showing a layout of cells and wirings of the semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Cell 2 ... P-channel diffusion layer 3 ... N-channel diffusion layer 4 ... 1st power supply line (V _DD ) 5 ... 2nd power supply line (V _SS ) 6 ... Signal output wiring 8 ... Polysilicon layer 7 Connection wiring 9 ... Input contact portion 10 ... Bottom wiring layer 20 ... Second conductive layer 25 ... Insulating layer 26 ... Cell surface portion 30 ... Input signal wiring C1 --- C12 ... Contact portion DC1 --- DC4 ... Direct contact part H1 --- H6 ... Wiring possible range R1 --- R11 ... Direct contact part disposing range SA1 --- SA3 ... Cell array stage SL ... Wiring area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hyakubu 10015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 1015 Kamiodanaka, Fujitsu Limited

Claims (5)

[Claims] 1. In a cell arranged in a semiconductor integrated circuit, when wiring a predetermined signal line to the cell,
A structure in which a P-channel diffusion region and an N-channel diffusion region forming the cell are connected to each other through one of wiring layers made of a plurality of conductive layers separated from each other by an insulating layer. In addition, a wiring layer formed of at least one conductive layer other than the lowermost wiring layer is in contact with a predetermined portion directly located in the cell or directly through the lowermost wiring layer. A cell structure of a semiconductor integrated circuit, characterized in that a direct contact portion is formed, and the wiring layer is a signal wiring. 2. A predetermined portion located inside the cell is a thin film body made of a metal material formed commonly on the surfaces of the P-channel diffusion region and the N-channel diffusion region formed inside the cell. The cell structure of a semiconductor integrated circuit according to claim 1, wherein 3. A direct contact portion penetrating the lowermost wiring layer, wherein one of the conductive layers other than the lowermost wiring layer has a direct contact portion forming a contact with a predetermined portion in the cell. The cell structure of the semiconductor integrated circuit according to claim 1. 4. The at least one conductive layer other than the lowermost wiring layer is directly on the contact portion where the lowermost wiring layer forms a contact with a predetermined portion in the cell. 2. The cell structure of a semiconductor integrated circuit according to claim 1, wherein a direct contact portion that is directly connected to form a multiple contact portion is formed. 5. The semiconductor according to claim 1, wherein the lowermost wiring layer is at least one of the first power supply line (V _DD ) and the second power supply line (V _SS ). Cell structure of integrated circuit.