JPH05347386A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to completely prevent the influence of the back gate effect from the substrate and prevent the phase shift and the operation failure with respect to the pulse response of the CMOS peripheral logic circuit. A N-FET (Qn) including an N type source region 2S, a drain region 2D and a gate electrode 2G, and a P type source region 3S, a drain region 3D and a gate electrode 3G are formed on an N type silicon substrate 1n. P-FET consisting of
In a CMOS inverter configured by forming (Qp), P-FET (Qp) from the bottom of N-FET (Qn)
A P-type first well region 4p is formed downward, and the P-FET (Q
p) An N-type second well region 5n is formed thereunder.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is suitable for use in, for example, a CMOS inverter or the like in a peripheral circuit of an image sensor composed of CCD, MOS and the like.

[0002]

2. Description of the Related Art Generally, a buffer circuit is connected to a peripheral circuit of an image sensor including a CCD, a MOS, etc., for example, a path until an output signal from the image sensor is supplied to a signal processing circuit in a subsequent stage. As the buffer circuit, an inverting amplifier such as a CMOS inverter, a non-inverting amplifier such as a source follower circuit, and a differential amplifier are used. Also, in the logic part of the peripheral circuit, an inverter, a NAND,
Others and the like are used.

FIG. 7 shows a sectional structure of a conventional CMOS inverter as an example. This CMOS inverter is
As shown in the figure, for example, on an N type silicon substrate 11n, an N channel type MOS field effect transistor (hereinafter, referred to as an N type source region 12S and a drain region 12D and a gate electrode 12G made of a polycrystalline silicon layer or the like)
Qn and P-type source region 13
A P-channel MOS field effect transistor (hereinafter, simply referred to as P-FET) Q including S and a drain region 13D and a gate electrode 13G including a polycrystalline silicon layer or the like Q
p is formed and configured.

Particularly, under the N-FET (Qn), the N-
A P-type well region 14p for separating the FET (Qn) and the silicon substrate 11n is formed. In addition, P-FE
T (Qp) is directly formed on the silicon substrate 11n.

The substrate potential Vsub is applied to the silicon substrate 11n, and the power source voltage Vdd is applied to the source region 13S of the P-FET (Qp) and the source region 12S and well region 14p of the N-FET (Qn). Are respectively applied with the ground potential Vss. An input signal is supplied to the common terminal φin connected to the gate electrodes 12G and 13G, and an output signal (inverter output) is output from the common terminal φout connected to the drain regions 12D and 13D. In the figure, a shaded region 11N near the back surface of the substrate 11n indicates a neutral region of the substrate 11p, and its potential is fixed to the substrate potential Vsub.

When a P type silicon substrate is used as the silicon substrate, as shown in FIG. 4, the P type silicon substrate 11 is used.
The P-FET is formed in the N-type well region 14n formed in p.
(Qp) is formed, and the N-FET (Qn) is directly formed on the silicon substrate 11p.

[0007]

By the way, the above-mentioned CCD
In an image sensor including a MOS, a MOS, or the like, an operation (electronic shutter operation, reset operation) of temporarily sweeping out signal charges in the light receiving portion to the substrate side is performed.

When these electronic shutter operations are performed, the substrate potential Vsub changes, and, for example, in FIG. 3, the P-FET (Q is directly formed on the silicon substrate 11n.
p) receives the back gate effect from the substrate 11n, and its Vth fluctuates. On the other hand, the N-FET (Qn) is not affected by the substrate potential Vsub, because the potential of the neutral region 14N (shown by diagonal lines) of the well region 14p is fixed to the ground potential Vss.

As described above, when the Vth of the FET constituting the CMOS inverter fluctuates, the operating point of the CMOS inverter changes, and the output (output signal) of the inverter is inverted. As a result, a phase shift or a malfunction of the pulse response of the image sensor peripheral logic or analog circuit is caused.

The same applies to the CMOS inverter shown in FIG. 8. In this case, the N-FET (Qn) formed directly on the silicon substrate 11p receives the back gate effect from the substrate 11p, and its Vth changes. Cause malfunctions of the image sensor peripheral logic and analog circuits.

The present invention has been made in view of the above problems, and an object of the present invention is to completely prevent the influence of the back gate effect from the substrate, and to provide an image sensor peripheral logic or analog circuit. It is an object of the present invention to provide a semiconductor device capable of preventing a phase shift and a malfunction due to a pulse response such as the above.

[0012]

The semiconductor device of the present invention comprises:
A first conductivity type semiconductor substrate, a well region formed in the semiconductor substrate, and a plurality of field effect transistors including at least a second conductivity type field effect transistor formed in the well region; The region has a first well region of the second conductivity type formed in the semiconductor substrate and a second well region of the first conductivity type formed in the first well region, and an electric field of the second conductivity type. An effect transistor is formed and formed in the second well region.

In the semiconductor device of the present invention, the semiconductor substrate 21 of the first conductivity type, the first well region 22n of the second conductivity type formed on the semiconductor substrate 21, and the first well region 22n are formed. A second well region 23p (or 23p ₁ or 23p ₂ ) of the first conductivity type formed inside the second well region 23p (or 23p ₁ or 23p ₂ ) and a second conductivity type formed inside the _second well region 23p (or 23p ₁ or 23p ₂ ). The field effect transistors Qn ₁ and Qn _{2 of} FIG.

The semiconductor device of the present invention includes a semiconductor substrate 1n (or 41) of the first conductivity type and the semiconductor substrate 1n.
(Or 41) the first well region 4p (or 4n, 42n) of the second conductivity type, and the first well region 4
A first field effect transistor Qn (or Qp, Qp ₃ , Q) of the first conductivity type formed in p (or 4n, 42n).
p ₄ ) and the first well region 4p (or 4n, 42)
n) second well region 5n of the first conductivity type formed in
(Or 5p, 43p) and the second field effect transistor Qp (or Qn, Qn ₃ , Qn ₄ ) of the second conductivity type formed in the second well region 5n (or 5p, 43p).
And is configured.

According to the present invention, in the semiconductor device of the second invention, the first conductivity type is P type and the second conductivity type is N type. Second
The conductive type field effect transistors Qn ₁ and Qn ₂ are formed to configure the source follower circuit 35.

Further, according to the present invention, in the above-mentioned second semiconductor device, the first conductivity type is P-type, the second conductivity type is N-type, and two first conductivity types are formed in the first well region 22n. 2 well regions 23p ₁ and 23p ₂ are formed, and
The second conductivity type field effect transistors Qn ₁ and Qn ₂ are formed in 3p ₁ and 23p ₂ to form the source follower circuit 20.
Compose

According to the present invention, in the semiconductor device of the third invention, the first conductivity type is P-type, the second conductivity type is N-type, the first field effect transistor Qp and the first field-effect transistor Qp. Two field effect transistors Qn are connected to each other by an inverter.

Further, in the semiconductor device according to the third aspect of the present invention, the first conductivity type is a P type, the second conductivity type is an N type, the first field effect transistor and the second field effect transistor. Two field effect transistors (Qn ₃ , Qn ₄ and Qp ₃ , Qp ₄ ) are formed to form the NAND circuit 40.

[0019]

According to the structure of the first invention, at least the second-conductivity-type field effect transistor has a channel separated from the substrate in the first and second well regions, and is formed in the first well region. If another field effect transistor is formed in the
, Its channel is separated from the substrate. Therefore, when the semiconductor device of the present invention is applied to a peripheral circuit of an image sensor composed of CCD or MOS, for example, a CMOS inverter or the like, an electronic shutter operation or reset is performed. Even if the substrate potential Vsub varies with the operation, the back gate effect from the substrate on the plurality of field effect transistors can be completely prevented.

According to the structure of the second invention, the second conductivity type
Field effect transistor Qn₁, Qn ₂Is the first and second
Well regions 22n and 23p (or 23p₁, 23p
₂), The channel is separated from the substrate.
Therefore, even if the substrate potential Vsub fluctuates, the field effect transistor is also changed.
Register Qn₁, Qn₂Back from the board 21 to
The gate effect can be completely prevented.

According to the structure of the third invention, the first field effect transistor Qn (or Qp, Qp ₃ , Qp ₄ ) has the first well region 4p (or 4n, 42n) whose channel is the substrate 1n (or Or 41) and is separated from the second field effect transistor Qp (or Qn, Q).
n ₃ and Qn ₄ ) are formed in the first and second well regions 4p (or 4n, 42n) and 5n (or 5p, 43p) because their channels are separated from the substrate 1n (or 41). Even if the substrate potential Vsub fluctuates similarly to, the back gate effect from the substrate on the first and second field effect transistors can be completely prevented.

In the fourth invention, two second conductivity type field effect transistors Q are provided in the second well region 23p.
Since the source follower circuit 35 is formed by forming n ₁ and Qn ₂ , these two field effect transistors Qn ₁ and Qn
n ₂ is in a form in which the respective channels are separated from the substrate by the first and second well regions 22n and 23p, and even if the substrate potential Vsub varies, the two electric fields forming the source follower circuit 35 are formed. It is possible to completely prevent the back gate effect from the substrate 21 on the effect transistors Qn ₁ and Qn ₂ and prevent malfunctions in the source follower circuit.

[0023] In the fifth invention, the two second well forming region 23p ₁ and 23p _2, the field-effect transistor of the second conductivity type corresponding to the respective second well region 23p ₁ and 23p in ₂ by configuring the source follower circuit 20 to form Qn _1, Qn _2, the field effect transistor Qn ₁ each, qn _2, the first and second well regions 22n and 23p _1, the respective channel 23p ₂ Is separated from the substrate 21, and even if the substrate potential Vsub fluctuates similarly to the above, the source follower circuit 2
Two field-effect transistors Qn ₁ and Qn forming 0
It is possible to completely prevent the back gate effect on the substrate ₂ from the substrate 21, and it is possible to prevent malfunction of the source follower circuit.

In the sixth invention, first and second field effect transistors Qp (or Q) connected in an inverter are connected.
n) and Qn (or Qp), the first field-effect transistor Qp (or Qn) has its channel separated from the substrate 1 in the first well region 4, and
In the field effect transistor Qp (or Qn), the channel is separated from the substrate in the first and second well regions 4 and 5, and therefore, even if the substrate potential Vsub varies as in the above case, It is possible to completely prevent the back gate effect from the substrate 1 on the second field effect transistors Qn and Qp and prevent malfunction of the inverter.

In the seventh invention, the NAND circuit 40
Of the four field effect transistors Qn ₃ and Q
In n ₄ , Qp ₃ and Qp ₄ , the field effect transistors Qp ₃ and Qp ₄ have their channels separated from the substrate 41 in the first well region 42n, and the field effect transistors Qn ₃ and Qn ₄ are the first and for that channel in the second well region 42n and 43p is a shape which is separated from the substrate 41, similarly to the above, even if the substrate potential Vsub is varied, the field effect transistor Qn _3, Qn
It is possible to completely prevent the back gate effect from the substrate 41 with respect to ₄ , Qp ₃ , and Qp ₄ , and
It is possible to prevent malfunctions and the like.

Therefore, according to the semiconductor device of the present invention, the first and second field effect transistors Qn and Qp are not affected by the back gate effect from the substrate 1, and the image sensor peripheral logic and analog circuit circuits are not affected. It is possible to prevent a phase shift with respect to the pulse response and a malfunction.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment, for example, a CMOS inverter.

As shown in the figure, this CMOS inverter is of an N-channel type composed of an N-type source region 2S, a drain region 2D, and a gate electrode 2G made of a polycrystalline silicon layer or the like on an N-type silicon substrate 1n. MOS type field effect transistor (hereinafter simply referred to as N-FET)
P composed of Qn, a P-type source region 3S, a drain region 3D, and a gate electrode 3G composed of a polycrystalline silicon layer or the like
A channel type MOS field effect transistor (hereinafter, simply referred to as P-FET) Qp is formed and configured.

Thus, in this example, the N-FET is
A P-type first well region 4p is formed from under (Qn) to under P-FET (Qp), and an N-type second well region 4p is formed under the P-FET (Qp) in the first well region 4p.
Well region 5n is formed to have a double-well structure. That is, the P-FET (Qp) is formed on the surface of the second well region 5n in the first well region 4p and the second well region 5n in the first well region 4p is not formed. N-FET on the surface
(Qn) is formed.

The substrate potential Vsub is applied to the silicon substrate 1n, and the power source voltage Vdd is applied to the source region 3S of the P-FET (Qp) and the second well region 5n.
The ground potential Vss is applied to the source region 2S and the first well region 4p of the N-FET (Qn), respectively.

Therefore, the substrate 1n and the first well region 4p
The neutral regions 1N, 4N, and 5N (indicated by diagonal lines) in the second well region 5n are fixed to the substrate potential Vsub, the ground potential Vss, and the power supply potential Vdd, respectively. An input signal is supplied to the common terminal φin connected to the gate electrodes 2G and 3G, and an output signal (inverter output) is output from the common terminal φout connected to the drain regions 2D and 3D.

According to the first embodiment, the N-FET (Q
n) is such that its channel is separated from the substrate 1n by the first well region 4p.
Since (Qp) has a channel whose channel is separated from the substrate 1n by the first and second well regions 4p and 5n, the image of the CMOS inverter or the like according to the first embodiment is composed of CCD or MOS. When applied to a peripheral circuit of the sensor, for example, a buffer circuit or a drive circuit, even if the substrate potential Vsub varies due to an electronic shutter operation or a reset operation, the N-FET (Qn) and P-FET (Qp) The back gate effect from the substrate 1n can be completely prevented.

Therefore, according to the CMOS inverter of the first embodiment, the N-FET (Qn) and the P-FET are provided.
Both (Qp) are not affected by the back gate effect from the substrate 1n, and it is possible to prevent a phase shift or a malfunction in the pulse response of the image sensor peripheral logic or analog circuit.

Next, a CMOS inverter according to the second embodiment will be described with reference to FIG. The same reference numerals are given to those corresponding to FIG. CMOS according to the second embodiment
The inverter has substantially the same structure as that of the first embodiment, but differs in that the conductivity types of impurities are reversed.

That is, a P-type silicon substrate 1p is used as the silicon substrate, and the N-FET (Qn) is the N-type first substrate.
P-type second well region 5 in the well region 4n of
The P-FET (Qp) is formed on the surface of p and is formed on the surface of a portion of the first well region 4n where the second well region 5p is not formed.

Then, as in the first embodiment, the substrate potential Vsub is applied to the silicon substrate 1p, and P-F
Source region 3S and first well region 4 of ET (Qp)
The power supply voltage Vdd is applied to n, and the ground potential Vss is applied to the source region 2S and the second well region 5p of the N-FET (Qn). Therefore, the neutral regions 1N, 4N and 5N (indicated by diagonal lines) in the substrate 1p, the first well region 4n and the second well region 5p are
Substrate potential Vsub, power supply potential Vdd, and ground potential V, respectively
It is fixed to ss.

Also in the second embodiment, as in the first embodiment, when applied to a peripheral circuit of an image sensor, such as a CCD or a MOS, for example, a buffer circuit or a drive circuit, an electronic shutter operation or Even if the substrate potential Vsub varies with the reset operation, N−
Substrate 1 for FET (Qn) and P-FET (Qp)
It is possible to completely prevent the back gate effect from p, and it is possible to prevent a phase shift or a malfunction with respect to the pulse response of the image sensor peripheral logic or analog circuit.

In the above first and second embodiments, CC
The example applied to the CMOS inverter used in the peripheral circuit of the image sensor including D, MOS, etc. is shown, but it can be applied to all circuits using CMOS, of course.

FIG. 3 shows a source follower circuit 20 according to the third embodiment of the present invention. In this example, as shown in the figure, the second substrate is formed on the silicon substrate 21 of the first conductivity type, for example, P type.
A conductive type or N type first well region 22n is formed, and two P type second well regions 22n are formed in the first well region 22n.
Well regions 23p ₁ and 23p ₂ are formed.

Then, one of the second well regions 23p₁
A pair of N type source region 24S and drain region 24
D and polycrystalline silicon formed through the gate insulating film
N-channel type M including a gate electrode 26 formed of a layer or the like
OS type field effect transistor, that is, driving MOS transistor
Dista Qn₁And the other second well region 23 is formed.
p₂A pair of N type source region 27S and drain region
27D and polycrystalline silicon formed through the gate insulating film
N-channel type consisting of a gate electrode 29 made of a con-layer or the like
MOS field effect transistor, that is, a load MOS transistor
Langista Qn ₂Is formed. 31 is due to selective oxidation
It is a field insulating layer.

The substrate potential Vsub is applied to the silicon substrate 21 to drive the MOS transistor Qn ₁ for driving.
The power supply voltage Vdd is applied to the drain region 24D and the first well region 22n, and the ground potential Vss (so-called GND) is applied to the source region 27S of the load MOS transistor Qn ₂ and the respective well regions 23P ₁ and 23P ₂ . 32
And 33 are second well regions 23p ₁ and 23p _{2 respectively.}
It is a high-concentration region for contact formed in the.

Therefore, the substrate 21 and the first well region 22
n and second well regions 23p _1, the neutral region in 23p ₂ 21N, 22N, 23N ₁ and 23N
₂ (indicated by diagonal lines) are fixed to the substrate potential Vsub, the power supply potential Vdd, and the ground potential Vss, respectively. Further, an input signal is supplied to the input terminal φin connected to the gate electrode 26 of the driving MOS transistor Qn ₁ , and an output signal is output from the common output terminal φout connected to each source region 24S and drain region 27D. It A bias voltage Vg is supplied to the gate electrode 29 of the load MOS transistor Qn ₂ .

The source follower circuit 20 of the third embodiment.
According to the driving MOS transistor Qn ₁ and the load MOS transistor Qn ₂ , the respective channels of the driving MOS transistor Qn ₁ and the load MOS transistor Qn ₂ are the first well region 22n and the second well regions 23p ₁ and 2p.
Since it is separated from the substrate 21 by 3p ₂ ,
When the source follower circuit 20 is applied to a peripheral circuit of an image sensor including a CCD, a MOS, or the like, for example, a buffer circuit or a drive circuit, even if the substrate potential Vsub varies with the electronic shutter operation, the drive M
The back gate effect from the substrate 21 on the OS transistor Qn ₁ and the load MOS transistor Qn ₂ can be completely prevented.

Therefore, also in the source follower circuit 20 according to the third embodiment, the driving MOS transistor Q is used.
Both n ₁ and the load MOS transistor Qn ₂ are on the substrate 21.
Therefore, it is possible to prevent a back-gate effect from being generated, and to prevent a phase shift and a malfunction in the pulse response of the image sensor peripheral logic and analog circuits.

FIG. 4 shows a source follower circuit according to the fourth embodiment of the present invention. In the figure, the parts corresponding to those in FIG. 3 are designated by the same reference numerals. In this example, a second conductivity type, that is, an N type first well region 22n is formed on a silicon substrate 21 of a first conductivity type, for example, a P type, and a P type second well region 22n is further formed in the first well region 22n. A well region 23p is formed, and two N-channel field effect transistors, that is, driving MOs, are formed in the common second well region 23p.
An S transistor Qn ₁ and a load transistor Qn ₂ are formed.

Then, similarly to the third embodiment, the substrate potential Vsub is applied to the silicon substrate 21, and the drain region 24D of the driving MOS transistor Qn ₁ and the first region are formed.
Power supply voltage Vdd is applied to the well region 22n of
The ground potential Vss (so-called GND) is applied to the source region 27S of the transistor Qn ₂ and the second well region 23p. Further, the bias voltage Vg is applied to the gate electrode 29 of the load MOS transistor Qn ₂ to drive the MO transistor for driving.
An input signal is supplied to the input terminal φin connected to the gate electrode 26 of the S-transistor Qn ₁ so that each source region 2
An output signal is output from the common output terminal φout connected to the 4S and the drain region 27D. It is also possible to provide the P-type high-concentration region 33 at a plurality of locations according to the resistance of the second well region 23p and apply the power supply voltage Vdd to each of them.

Therefore, the substrate 21 and the first well region 22
n and each of the neutral regions 21N, 22N and 23N (indicated by diagonal lines) in the second well region 23p are the substrate potential Vsub, the power supply potential Vdd and the ground potential Vs, respectively.
fixed to s.

Also in the source follower circuit 35 of the fourth embodiment, as in the third embodiment, when it is applied to, for example, a buffer circuit or a drive circuit of a peripheral circuit of an image sensor including, for example, a CCD or a MOS, an electronic circuit is used. Even if the substrate potential Vsub varies due to the shutter operation, the back gate effect from the substrate 21 on the drive MOS transistor Qn ₁ and the load MOS transistor Qn ₂ can be completely prevented, and the image sensor peripheral logic and analog It is possible to prevent a phase shift and a malfunction in the pulse response of a circuit or the like.

Although the above example is applied to an analog circuit, it can also be applied to a digital circuit such as a logic circuit. FIG. 5 shows a semiconductor device of the present invention in which a logic circuit such as N
It is a fifth embodiment when applied to the AND circuit 40. In this example, a silicon substrate 4 of the first conductivity type, for example, P type is used.
The first well region 42n of the second conductivity type, that is, the N type is formed in the first region, and the P-type second well region 43p is further formed in the first well region 42n.

Then, two P-channel field effect transistors, that is, 1 in the N-type first well region 42n.
Paired P-type source region 44S and drain region 44D
And a gate electrode 46 made of a polycrystalline silicon layer or the like formed via a gate insulating film.
(Qp ₃ ), a pair of P-type source region 47S and drain region 47D, and a second gate electrode 49 formed of a polycrystalline silicon layer or the like via a gate insulating film.
P-FET (Qp ₄ ) is formed.

Two N-channel field effect transistors, that is, a pair of N-type source region 51S and drain region 51D, are formed in the P-type second well region 43p.
A first N-FET (Qn consisting of a gate electrode 53 made of a polycrystalline silicon layer or the like formed via a gate insulating film)
₃ ), a pair of N-type source regions 54S and drain regions 54D, and a second N-type gate electrode 56 made of a polycrystalline silicon layer or the like formed via a gate insulating film.
FET (Qn ₄ ) is formed.

The substrate potential V is applied to the silicon substrate 41.
sub is applied to the first and second P-FETs (Q
p ₃₎ and (a source region 44S and the source region 47S of each of Qp _4), the power supply voltage Vdd is commonly applied to the P-type high concentration region 58 of the N-type first well region 42n i.e. the contact of The ground potential Vss (so-called GND) is commonly applied to the source region 51S of the first N-FET (Qn ₃ ) and the P-type second well region 43p, that is, the N-type high-concentration region 59 for the contact. Therefore, each of the neutral regions 41N, 42N and 43N (indicated by diagonal lines) in the substrate 41, the second well region 42n and the second well region 43p respectively has the substrate potential Vsub,
It is fixed to the ground potential Vss and the power supply potential Vdd.

[0053] The source region 54S of the drain region 51D of the first N-FET (Qn ₃₎ a second N-FET (Qn ₄₎ are connected in common. Furthermore, the first N-FE
T (Qn ₃ ) gate electrode 53 and first P-FET
The common first input terminal φin ₁ connected to the gate electrode 46 of (Qp ₃ ), the gate electrode 56 of the second N-FET (Qn ₄ ) and the gate electrode of the second P-FET (Qp ₄ ). An input signal is supplied to each of the common second input terminals φin ₂ connected to 49, and the second N-FET (Qn ₄ )
The drain region 54D and the second P-FET (Qp ₄₎
Common output terminal φo connected to the drain region 47D of the
An output signal is output from ut.

An equivalent circuit of the NAND circuit 40 having such a structure is shown in FIG.

Also in the NAND circuit of the fifth embodiment, the two P-FETs (Qp ₃ ) and (Qp ₄ ) are the first
Well region 42n, the channel is separated from the substrate 41, and two N-FETs (Q
n ₃ ) and (Qn ₄ ) are the first and second well regions 42.
Since the channel is separated from the substrate 41 by n and 43p, even if the substrate potential Vsub varies, the N-FETs (Qn ₃ ), (Qn ₄ ), and P-FET are formed.
_{-FET (Qp 3), (Qp} 4) the back gate effect from the substrate with respect to can be completely prevented, and a phase shift corresponding to the pulse response of the image sensor peripheral logic circuit, it is possible to prevent a malfunction, etc. it can.

[0056]

According to the semiconductor device of the present invention, the influence of the back gate effect from the substrate can be completely prevented, and the phase shift or the malfunction of the pulse response of the image sensor peripheral logic or analog circuit can be prevented. Can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a CMOS inverter according to a first embodiment.

FIG. 2 is a sectional view showing a configuration of a CMOS inverter according to a second embodiment.

FIG. 3 is a sectional view showing a configuration of a source follower circuit according to a third embodiment.

FIG. 4 is a sectional view showing a configuration of a source follower circuit according to a fourth embodiment.

FIG. 5 is a sectional view showing the configuration of the NAND circuit according to the fifth embodiment.

FIG. 6 is an equivalent circuit diagram of the NAND circuit of FIG.

FIG. 7 is a sectional view showing a configuration of a CMOS inverter according to a conventional example.

FIG. 8 is a sectional view showing a configuration of a CMOS inverter according to another conventional example.

[Explanation of symbols]

21, 24, 1n, 1p Silicon substrate 2S, 3S Source region 2D, 3D Drain region 2G, 3G Gate electrode Qn, Qn ₁ , Qn ₂ , Qn ₃ , Qn ₄ N-channel MOS field effect transistor (N-FET) _{) Qp, Qp 3, Qn 4} P -channel type MOS field effect transistor (P-FET) 42n, 22n , 4p, 4n first well region _{23p, 23p 1, 23p 2,} 5n, 5p second well region 21P, 22N, 23P ₁ , 23P ₂ , 42N, 43
P, 1N, 4N, 5N Neutral region 26, 29, 46, 49, 53, 56 Gate electrode 24S, 27S, 44S, 47S, 51S, 54S Source region 24D, 27D, 44D, 47D, 51D, 54D Drain region

[Procedure amendment]

[Submission date] March 19, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (7)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well region formed in the semiconductor substrate, and a plurality of field effect transistors including at least a second conductivity type field effect transistor formed in the well region. The well region has a second well region of the second conductivity type formed in the semiconductor substrate and a second well region of the first conductivity type formed in the first well region. A semiconductor device having a field effect transistor of two conductivity type formed in the second well region. 2. A first conductivity type semiconductor substrate, a second conductivity type first well region formed in the semiconductor substrate, and a first conductivity type first well region formed in the first well region. Second well region and a second well region formed in the second well region.
A semiconductor device having a conductivity type field effect transistor. 3. A first conductivity type semiconductor substrate, a second conductivity type first well region formed in the semiconductor substrate, and a first conductivity type first well region formed in the first well region. No. 1, a field effect transistor, a second well region of a first conductivity type formed in the first well region, and a second electric field of a second conductivity type formed in the second well region. A semiconductor device having an effect transistor. 4. The first conductivity type is P-type, the second conductivity type is N-type, and two second conductivity regions are provided in the second well region.
3. The semiconductor device according to claim 2, wherein a conductive type field effect transistor is formed to form a source follower circuit. 5. The first conductivity type is P-type, the second conductivity type is N-type, and two second conductivity types are provided in the first well region.
2. The well region of the second well region is formed, and the field effect transistor of the second conductivity type is formed in each of the second well regions to form a source follower circuit.
The semiconductor device described. 6. The first conductivity type is a P type, the second conductivity type is an N type, and the first field effect transistor and the second field effect transistor are inverter-connected to each other. The semiconductor device according to claim 3. 7. The first conductivity type is a P type, the second conductivity type is an N type, and two first field effect transistors and two second field effect transistors are formed to form an NA.
4. The semiconductor device according to claim 3, which constitutes an NA circuit.