JPH11112247A - Output buffer circuit - Google Patents

Abstract

(57) [Summary] A dynamic range is narrowed by an output change with respect to an input of a buffer output circuit. An output transistor M1 for outputting an input voltage Vin applied to a control electrode via an input terminal T1in from one electrode other than the control electrode, and an input voltage connected between the input terminal T1in and the control electrode. The voltage holding capacitor C that holds Vin at one electrode and the potential of the other electrode, and the holding voltage at the one electrode side is the output transistor M1.
And a voltage adjustment unit that adjusts such that the voltage change (drop) is reduced or canceled when the voltage is output from the controller. Preferably, an input cutoff switch S1 is provided between the input and output terminals, and the voltage adjusting unit is a diode-connected transistor M connected in parallel between the other electrode and the reference voltage supply line 6.
5 and a switch S2, and a current source I for supplying a constant current to one of them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit provided at the last stage of a functional circuit block and outputting input signals in the same phase.

[0002]

2. Description of the Related Art FIGS. 3 and 4 show a conventional output buffer circuit in a CMOS integrated circuit. Here, FIG. 3 shows a case where an output is taken out from an n-channel MOS transistor (nMOS transistor), and FIG. 4 shows a case where an output is taken out from a p-channel MOS transistor (pMOS transistor).

The output buffer circuit 30 shown in FIG. 3 has a current mirror configuration, and outputs an nMOS transistor M1 and a pMOS transistor M2 for output, and a predetermined mirror current i3 flows through these output transistors M1 and M2 to output the output. A current source I3 for determining the driving capability of the circuit,
And an output transistor M1 as a load of the current source I3.
An nMOS transistor M3 provided symmetrically with M2 and p
It is composed of a MOS transistor M4. In FIG. 3, T3in indicates an input terminal, and T3out indicates an output terminal.

An output nMOS transistor M1 and an output pMOS transistor M2 are connected in series between a power supply voltage V _DD supply line (V _DD line 5) and a ground line 6, and a connection node of both transistors is connected to an output terminal T3out. It is connected to the. Similarly, an nMOS transistor M3, a pMOS transistor M4, and a current source I3 are connected in series between the _VDD line 5 and the ground line 6. nMOS transistor M3
Has a gate connected to the output nMOS transistor M1 and a connection node connected to the input terminal T3in. The pMOS transistor M4 has a gate connected to the output pMOS transistor M2,
The connection node between the gates is a pMOS transistor M
4 is connected to the drain. The substrate or well of each of the MOS transistors M1 to M4 is connected to a source.

The basic configuration of the output buffer circuit 40 shown in FIG. 4 is the same as that of FIG. That is, the output buffer circuit 40 also has a current mirror type configuration, and the output nMOS transistor M1 and the pMOS transistor M2, and a predetermined mirror current i4 flows through these output transistors M1 and M2, thereby increasing the driving capability of the output circuit. The current source I4 to be determined, and the nMOS transistor M3 and the pMOS transistor M4 provided symmetrically with the output transistors M1 and M2 as the load of the current source I4
And an input terminal T4in and an output terminal T4out. Further, the V _DD line 5, the ground line 6, and the output terminal T4ou
t, these four MOS transistors M1 to M
4 and the current source I4 are the same as in FIG. That is, between the _VDD line 5 and the ground line 6, the output n
The MOS transistor M1 and the output pMOS transistor M2 are connected in series, and the connection node of both transistors is connected to the output terminal T4out. Similarly, between the _VDD line 5 and the ground line 6, an nMOS transistor M3, p
The MOS transistor M4 and the current source I4 are connected in series. Further, the fact that the gates of the nMOS transistors M1 and M3, the gates of the pMOS transistors M2 and M4 are connected to each other, and that the substrates or wells of the MOS transistors M1 to M4 are respectively connected to the sources are shown in FIG. Is the same as

The output buffer circuit 40 shown in FIG.
Unlike the case of FIG. 3, the input terminal T4in is not a connection node between the gates of the nMOS transistors M1 and M3,
It is connected to a connection node between the gates of the pMOS transistors M2 and M4. Further, the gate and the drain are short-circuited, not in the pMOS transistor M4.
This is an nMOS transistor M3.

In the output buffer circuits 30 and 40 having such a current mirror configuration, the same mirror current as the current i3 or i4 flowing from the current sources I3 and I4 flows through the output transistors M1 and M2, and the input signals are output in the same phase. Is output from the use transistor M1 or M2. The output buffer circuits 30 and 40 are provided, for example, at the last stage of a functional circuit block in a CMOS integrated circuit, and output signals subjected to predetermined processing up to the previous stage at the same phase and at a high speed. Used to lower the output impedance.

An output buffer circuit having the same configuration as this
The MOS transistors M1 and M3 are replaced by npn-type bipolar transistors, and the pMOS transistors M2 and M3 are replaced.
By replacing M4 with a pnp type bipolar transistor, it can be realized in a bipolar integrated circuit.

[0009]

However, as described above, p
In an output buffer circuit using a channel type or n-channel type output transistor (for example, M1 in FIG. 3 or M2 in FIG. 4) as a source follower (or emitter follower), an n-channel type output transistor is used as a source follower. The output signal voltage with respect to the input signal voltage decreases, and when a p-channel type output transistor is used as a source follower, the output signal voltage with respect to the input signal voltage increases. As a result, the dynamic range of the output buffer circuit increases. There are disadvantages such as narrowing.

For example, the output buffer circuit 3 shown in FIG.
At 0, an input signal is applied to the input terminal T3in. If the voltage of the input signal during a certain time is Vin and the gate threshold voltage of the output nMOS transistor M1 is VthM1, the output terminal T3out is connected to the input terminal Vin. The appearing output signal voltage Vout is expressed by the following equation, and the decrease of the output voltage value Vout with respect to the input voltage Vin is apparent.

[0011]

Vout = Vin−VthM1 (1)

This inconvenience may occur because the output MO
The same applies to the case of FIG. 4 in which the S transistor is p-type,
Assuming that the gate threshold voltage of the output pMOS transistor M2 in this case is VthM2, the following equation similar to the above equation (1) holds.

[0013]

Vout = Vin + VthM2 (2)

In particular, when such an output buffer circuit is used for an IC whose output dynamic range is an important factor, such as a driver IC for driving a subsequent-stage functional element, a decrease in the output dynamic range of the output buffer circuit is serious. Becomes Therefore, an improvement means for effectively reducing or preventing a decrease in the output dynamic range of the output buffer circuit has been strongly desired.

The present invention has been made in view of such circumstances, and has as its object to provide a new output buffer circuit having a wide output dynamic range by effectively preventing an output voltage from changing with respect to an input voltage. I do.

[0016]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, an output buffer circuit of the present invention comprises an input buffer applied to a control electrode via an input terminal. An output buffer circuit having an output transistor for outputting from one of the two electrodes other than the control electrode, wherein the output buffer circuit is connected between the input terminal and the control electrode and controls an input voltage applied to the input terminal. The voltage change by the output transistor when the voltage held by one capacitor electrode and the potential of the other electrode of the voltage holding capacitor are output from the output transistor when the voltage held by the one capacitor electrode is output from the output transistor. And a voltage adjusting unit that adjusts so as to reduce or cancel out. Preferably, an input cutoff switch is provided between the input terminal and the voltage holding capacitor, the switch being on before the input voltage is applied to the one electrode, and being turned off after the input voltage is applied.

Specifically, the voltage adjusting section includes a diode-connected transistor connected between the other electrode of the charge holding capacitor and a reference voltage supply line, and a diode-connected transistor connected between the other electrode and the reference voltage supply line. It is preferable that the switch further includes a switch connected in parallel with the diode-connected transistor, and a current source that supplies a constant current to the switch or the diode-connected transistor. This diode-connected transistor preferably has the same channel conductivity type or transistor size as the output transistor. When the output transistor and the diode-connected transistor are n-channel type, the switch is turned on before the input cutoff switch is turned off, and is turned off at the same time as or slightly after the input cutoff switch. . Conversely, in the case of a p-channel type, the switch is controlled to be turned off first and to be turned on at the same time as or slightly after the cutoff of the input cutoff switch.

In the output buffer circuit having such a configuration,
When the output transistor and the diode connection transistor are n-channel type, before an input signal is applied to the input terminal, a switch in the voltage adjustment unit is turned on,
Since a constant current from the current source flows through the switch to the reference voltage supply line, the other electrode of the charge holding capacitor is held at the reference voltage (for example, 0 V).
In this state, when the input signal applied to the input terminal is transmitted to one electrode of the charge holding capacitor, the input cutoff switch changes from the conductive state to the cutoff state, and at the same time or with a slight delay, the switch in the voltage adjusting unit also changes. Cut off. Then, the path of the constant current by the current source switches from the switch side to the diode-connected transistor side. If this diode-connected transistor is connected in advance so that the direction of the equivalent diode is directed from the charge holding capacitor to the reference voltage supply line, the potential of the other electrode of the charge-holding capacitor changes from the reference potential to the threshold of the diode-connected transistor. Value voltage. Therefore, the voltage of the input signal held at one electrode of the charge holding capacitor rises by the threshold voltage of the diode-connected transistor and is transmitted to the subsequent circuit. The change in the voltage of the output transistor is determined by the threshold voltage. When the output transistor is an n-channel type, the output voltage decreases with respect to the input voltage, while the input voltage is lower than the threshold voltage of the diode-connected transistor. Since the potential rises by the amount, this potential difference is reduced. In this case, in particular, when the threshold value of the diode-connected transistor is set to be the same as the threshold voltage of the output transistor, a decrease in the output dynamic range due to a change in the output voltage with respect to the input voltage can be completely prevented.

On the other hand, when the output transistor and the diode-connected transistor are p-channel transistors, the output voltage of the subsequent circuit rises with respect to the input voltage by the gate threshold value.
/ OFF is controlled for the input cutoff switch in the reverse of the above case, so that the voltage change due to the output transistor is reduced or canceled.

In order to completely prevent a change in the output voltage with respect to the input voltage, it is necessary to make the fluctuation direction and the fluctuation amount of the threshold voltage between the output transistor and the diode-connected transistor uniform. More specifically, the channel conductivity type and the size of the diode-connected transistor and the output transistor may be the same. In general, the threshold voltage of a transistor is location-dependent within a wafer, and even if the entire wafer fluctuates greatly, it is almost locally uniform. Therefore, in the output buffer circuit having the voltage adjustment unit, both transistors are used. Only by matching the channel conductivity type with the size of the channel, it is possible to completely prevent the output voltage from lowering and maximize the dynamic range of the output.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS There are various types of output buffer circuits. Here, the output buffer circuit of the present invention will be described below by taking as an example a case where the current mirror type output buffer circuit exemplified in the prior art is improved. The buffer circuit will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a circuit diagram showing an output buffer circuit according to this embodiment.

The output buffer circuit 1 is roughly divided into
Current mirror type output section, sample hold input section,
And a voltage adjusting unit. The output part of the current mirror type is composed of the output nMOS transistor M1 and p
It comprises a MOS transistor M2, a current source I3, an nMOS transistor M3 for loading a current source, and a pMOS transistor M4. The sample and hold input section
It comprises an input cutoff switch S1 and a charge holding capacitor C. The voltage adjustment unit includes a dynamic range improving nMOS transistor M5 and a current control switch S
2 and a current source I. Further, T1in and T1out are input and output terminals of the offset compensation circuit 1, and 5 and 6 are a supply line of the power supply voltage V _DD ( _VDD line) and a supply line of the reference voltage (for example, a ground line). The configuration and operation of the current mirror type output unit are not different from those of the output buffer circuit 30 shown in FIG.

The input cutoff switch S1 is connected between the input terminal T1in and the output terminal T1out of the output buffer circuit 1, and the input cutoff switch S1 and the output terminal T1ou.
One electrode of the voltage holding capacitor C is connected to a connection node NDa with t. NM between the other electrode of the voltage holding capacitor C and the ground line 6 for improving the dynamic range.
The OS transistor M5 and the current control switch S2 are connected in parallel. The current source I is connected between the connection node NDb on the other electrode side of the voltage holding capacitor C and the _VDD line 5. Since the output buffer circuit 1 has a basic configuration of a sample and hold circuit including an input cutoff switch S1 and a voltage holding capacitor C, the output buffer circuit 1 is in the category of a sample and hold circuit having a buffer output stage with an improved dynamic range. You can also catch it. In this case, the input cutoff switch S1 is indispensable. However, in other cases, the output impedance of the circuit connected to the preceding stage of the output buffer circuit 1 can be increased by the circuit operation. If it does not hinder charge retention,
The input cutoff switch S1 can be omitted.

The drain and gate of the dynamic range improving nMOS transistor M5 are short-circuited, thereby achieving diode connection. The dynamic range improving nMOS transistor M5 has the same transistor size as the output nMOS transistor M1 of the buffer output unit, and is desirably formed at the same time in an adjacent portion on the same substrate through the same process. The source and the substrate or the well of the dynamic range improving nMOS transistor M5 are short-circuited similarly to the transistor of the output buffer circuit 30.

Next, the operation of the output buffer circuit 1 will be described. In the initial state, the input cutoff switch S1
Is turned on, and one electrode side node N of the charge holding capacitor C
Da is connected to the input terminal T1in. Further, the current control switch S2 is turned on, and the constant current i from the current source I flows to the ground line 6 via the current control switch S2. Therefore, the other electrode side node NDb of the charge holding capacitor C
Is held at a reference voltage (for example, ground potential GND), and no voltage is applied between the source and the drain of the dynamic range improving nMOS transistor M5, and the transistor M5 is turned off.

When an input signal is applied to the input terminal T1in and transmitted to one electrode of the charge holding capacitor C, the voltage value Vin of the input signal at this time is held at the node NDa, and the potential Va satisfies the following equation.

[0028]

## EQU3 ## Va = Vin (3)

Immediately thereafter, the input cutoff switch S1 is turned off, and the potential Va in the equation (3) is
Thus, it is maintained even after the switch S1 is turned off. This hold potential Va is transmitted to the buffer output unit. The input voltage at the input terminal T3in at this time is Vin, and the output terminal T3ou
Assuming that the output voltage appearing at t is Vout, the following equation holds from the above equation (1).

[0030]

Vout = Vin−VthM1 = Va−VthM1 (4)

Simultaneously with or slightly after the input cutoff switch S1 is turned off, the current control switch S2 is also turned off, and the constant current i from the current source I is supplied to the dynamic range improvement nMO.
It flows through the S transistor M5. When a constant current i flows through the diode-connected nMOS transistor M5,
Since there is a voltage drop by the forward voltage of the equivalent diode, that is, the gate threshold voltage of the nMOS transistor M5,
The potential Vb of the node NDb rises from the reference voltage by the gate threshold voltage. Accordingly, the potential Va of the node NDa also increases by the same amount. Here, assuming that the gate threshold voltage of the dynamic range improving nMOS transistor M5 is VthM5, the potential after the rise of the nodes NDb and NDa is as follows.

[0032]

Vb = VthM5 (5-1) Va = Vin + VthM5 (5-2)

By substituting equation (5-2) into equation (4), the output voltage Vout of the buffer output section is obtained as follows.

[0034]

Vout = Vin + (VthM5−VthM1) (6)

Here, the output nMOS of the buffer output unit
The variation component of the gate threshold voltage VthM1 of the transistor M1 is (± ΔVthM1)
The variation component of the gate threshold voltage VthM5 of the S transistor M5 is (± ΔVthM5). When the above equation (6) is rewritten in consideration of these variation components, the following equation is obtained.

[0036]

Vout = Vin + (VthM5 ± ΔVthM5) − (VthM1 ± ΔVthM1) (7)

Generally, the gate threshold voltage Vth of a MOS transistor depends on the voltage VBS between the source and the back gate (substrate or well) and is expressed by the following equation.

[0038]

Vth = B × (VBS) ^1/2 + φ (8) where B and φ are predetermined coefficients given by physical constants, impurity concentrations, work functions, and the like.

Output nMO of output buffer circuit 1 of this embodiment
Since the substrate or well of the S-transistor M1 and the offset-compensating nMOS transistor M5 are connected to their respective sources, the voltage VBS between the source and the backgate becomes 0 in equation (8). In general, it is known that, in nMOS transistors of the same size in the same chip, if the layout positions are close to each other, the impurity concentration distribution is almost uniform. Naturally, physical constants,
Work functions are also equal. Therefore, in this case, the constants B and φ in equation (8) become substantially equal.

In an actual IC design, the output nMOS transistor M1 and the dynamic range improvement nMOS transistor M5 shown in FIG. After short-circuiting between gates and setting VBS = 0, a close pattern layout is performed. Output n at this time
The gate threshold voltage VthM1 (design center value) of the MOS transistor M1 and the gate threshold voltage VthM5 (design center value) of the dynamic range improving nMOS transistor M5 are
Can be estimated equally. Then, in the IC manufacturing process, the output nMOS transistor M1 and the dynamic range improving nMOS transistor M5 are collectively formed on the same substrate. In this manufacturing process, the gate threshold voltage often deviates from the design value. If the two transistors are separated from each other or have different sizes, the difference in the gate threshold voltage cannot be ignored. In this case, the output nMOS transistor M1 and the dynamic range improvement nMOS transistor M5 are the same device in close proximity pattern layout by design. Therefore, the direction and the amount of variation in the gate threshold voltage of both transistors are substantially equal.

As a result, the output nMOS transistor M
1 variation component (± ΔVthM1) of the gate threshold voltage ΔVthM1.
M1) and a variation component (± ΔV) of the gate threshold voltage VthM5 of the dynamic range improving nMOS transistor M5.
thM5) can be estimated to be equivalent. Therefore, (VthM5 ± ΔVthM5) ≒ (VthM1 ± ΔVthM1), and if this relationship is applied to the above equation (7), the following equation is established.

[0042]

Vout９Vin (9)

That is, in the output buffer circuit 1 of this embodiment, only by appropriately controlling the built-in switches S1 and S2, the amount of decrease in the output voltage Vout with respect to the input voltage Vin becomes zero. The output dynamic range of the buffer circuit 1 is maximized.

In the above description, the design is based on the condition that the gate threshold voltages are made uniform by forming the same device in a close pattern layout, but this design condition cannot be satisfied. Can't
Alternatively, even if the design and manufacturing conditions are the same, there is a gate threshold voltage difference when actually manufactured, and if this difference cannot be ignored, the output buffer circuit 1 of the present embodiment will not be able to maximize the output dynamic range. At least the effect of improving the dynamic range can be obtained. Also, when considering an IC having a plurality of output buffer circuits in which the output voltage is reduced with respect to the input voltage, the output reduction in each output buffer circuit can be reduced or completely prevented by making improvements in the present invention for each circuit. Thus, it is possible to avoid the conventional problem that the dynamic range of the output of the IC is greatly reduced. Further, when there is a subsequent circuit that uses each output voltage of a plurality of output buffer circuits as an input signal, variation between the input signals of the subsequent circuits is suppressed, and the subsequent circuit does not malfunction.

Second Embodiment This embodiment shows another embodiment of the output buffer circuit of the present invention, taking as an example a case where the output buffer circuit 40 of FIG. 4 using a p-type output MOS transistor is improved. Things. FIG. 2 is a circuit diagram illustrating the output buffer circuit according to the present embodiment.

The output buffer circuit 2 differs from the output buffer circuit 1 of the first embodiment in that the channel conductivity type of the dynamic range improving transistor M6 is p-type. Another configuration, that is, the input cutoff switch S
1, charge holding capacitor C, current control switch S2,
The connection relationship between the components including the current source I and the dynamic range improving pMOS transistor M6 is the first embodiment except that the gate of the pMOS transistor M6 is connected to the reference voltage supply line 6. Is the same as As in the first embodiment, the gate and the drain of the dynamic range improvement pMOS transistor M6 are short-circuited due to the diode connection, and the source is connected to the substrate or the well. The dynamic range improving pMOS transistor M6 has the same transistor size as the output pMOS transistor M2 of the buffer output unit, and is desirably formed at the same time in an adjacent portion on the same substrate through the same process. Here, T2in
And T2out are an input terminal and an output terminal of the output buffer circuit 2, and 5 and 6 are a supply line of the power supply voltage V _DD ( _VDD line) and a supply line of the reference voltage (for example, a ground line). Note that the configuration and operation of the buffer output unit are the same as those of the above-described conventional example (FIG. 4), and thus description thereof will be omitted.

The basic operation of the output buffer circuit 2 having such a configuration is the same as that of the first embodiment except that the ON / OFF control of the current control switch S2 with respect to the input cutoff switch is reversed. It is. That is, the current control switch S2 is turned off when the input cutoff switch S1 is first turned on, and is turned on at the same time as or slightly after S1 is turned off. This is because the output pMOS transistor M2 of this embodiment is connected to the GND side of the output terminal T4out, and the output voltage Vout (40) becomes higher than the input voltage Vin (40) by the gate threshold voltage VthM2. In order to cancel, the potential of the other electrode (or the node NDb) of the capacitor C is reduced by the gate threshold voltage VthM6 of the pMOS transistor M6 by switching the current control switch S2 from off to on.

For the above reasons, in the present embodiment, the gate threshold voltage VthM1 of the first embodiment is set to the gate threshold voltage (-VthM2) of the output pMOS transistor M2, and the gate threshold voltage VthM5 is set to the pMOS for dynamic range improvement.
The gate threshold voltage of the transistor M6 is replaced with (−VthM6), and the variation component (± ΔV
thM1) and (± ΔVthM5) are represented by the variation component of VthM2 (± ΔVthM2) and the variation component of VthM6 (± ΔVthM5).
By replacing with M6), the description of the operation in the first embodiment can be applied as it is.

That is, equation (5) in the first embodiment,
Equations (6-2) and (7) are the following equations (10) and (7), respectively.
Equations (11) and (12) are obtained. Further, the expression (8) in the first embodiment becomes like the following expression (13) in this example.

[0050]

Vout (40) = Vin (40) + VthM2 = Va + VthM2 (10) Va = Vin-VthM6 (11) Vout (40) = Vin + (VthM2-VthM6) (12) Vout (40) = Vin + (VthM2 ± ΔVthM2) − (VthM6 ± ΔVthM6) (13) where Vout is the output terminal T of the output buffer circuit 2.
The output voltage Vin appearing at 4out indicates the hold voltage of the input signal applied to the input terminal T2in of the output buffer circuit 2.

In the actual IC design, the output pMOS transistor M2 and the dynamic range improvement pMOS transistor M6 shown in FIG. If a short circuit is made between the gates and VBS = 0, and a close pattern layout is performed, the design value of the gate threshold voltage of both transistors can be estimated to be the same. In the process of manufacturing an IC, both transistors M
When the transistors M2 and M6 are collectively formed on the same substrate, the manner in which the gate threshold voltage shifts in this manufacturing process, that is, the direction and the amount of variation of the gate threshold voltage, are substantially equal between the transistors M2 and M6.

As a result, as in the first embodiment, (Vth
M6 ± ΔVthM6) ≒ (VthM2 ± ΔVthM2). If this relationship is applied to the above equation (13), the output buffer circuit 2
Of the output voltage Vout with respect to the input voltage Vin is completely prevented, and the conclusion expression of the expression (9) is obtained as in the first embodiment.

With the output buffer circuit 2 of the present embodiment, the same effects as in the first embodiment can be obtained. That is,
In the output buffer circuit 2, a change in the output voltage Vout with respect to the input voltage Vin is reduced or almost completely prevented, and as a result, the dynamic range of the output is improved (expanded). When a plurality of the output buffer circuits 2 are used, the output of the IC varies greatly due to the plurality of output buffer circuits whose output voltage changes with respect to the input voltage, or the output of the plurality of output buffer circuits having varied values is input. Since the signal is used as a signal, a conventional problem that a subsequent circuit malfunctions can be avoided.

[0054]

As described above, according to the output buffer circuit of the present invention, the output buffer circuit has a sample-and-hold function by the charge holding capacitor (and the input cutoff switch), and includes, for example, a transistor for improving the dynamic range, Source and switch, and has a voltage adjustment unit that adjusts the holding voltage of the capacitor in a direction to reduce or completely prevent a decrease in output of the subsequent circuit. Can be expanded and easily maximized. In addition, by improving the output dynamic range of each of the plurality of output buffer circuits or eliminating variations in the outputs, it is possible to effectively prevent malfunction of the subsequent circuit that inputs the plurality of outputs, or to incorporate the plurality of output buffer circuits. The dynamic range of the IC output can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an output buffer circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional output buffer circuit configured to extract output from an nMOS transistor in a CMOS integrated circuit.

FIG. 4 is a circuit diagram showing a conventional output buffer circuit configured to extract output from a pMOS transistor in a CMOS integrated circuit.

[Explanation of symbols]

1, 2 ... output buffer circuit, 5: supply line of power supply voltage V _DD , 6 ... supply line of reference potential (for example, ground potential GND), 30, 40 ... conventional output buffer circuit, M1, M2
... Output transistors, M3, M4 ... Current source load transistors, M5, M6 ... Dynamic range improvement transistors, C ... Voltage holding capacitors, I, I3, I4 ...
Current source, S1: input cutoff switch, S2: current control switch (switch), T1in, T2in, etc .: input terminal, T
1out, T2out, etc. output terminal, Vin input voltage, Vou
t ... output voltage.

Claims (9)

[Claims] 1. An output buffer circuit having an output transistor for outputting an input voltage applied to a control electrode via an input terminal from one of two electrodes other than the control electrode, the output buffer circuit comprising: A voltage holding capacitor connected between the control electrode and the input terminal, the input voltage applied to the input terminal being held by one of the capacitor electrodes; and the potential of the other electrode of the voltage holding capacitor being set to the holding voltage of the one of the capacitor electrodes. And a voltage adjustment unit that adjusts when the voltage is output from the output transistor so as to reduce or cancel a voltage change caused by the output transistor. 2. The voltage adjusting section, comprising: a diode-connected transistor connected between the other electrode of the charge holding capacitor and a reference voltage supply line; and a diode-connected transistor connected between the other electrode and the reference voltage supply line. The output buffer circuit according to claim 1, further comprising: a switch connected in parallel with the diode-connected transistor; and a current source that supplies a constant current to the switch or the diode-connected transistor. 3. An input cut-off switch between the input terminal and the voltage holding capacitor, the switch being turned on before an input voltage is applied to the one capacitor electrode and being cut off after the input voltage is applied. Output buffer circuit. 4. An input cut-off switch between the input terminal and the voltage holding capacitor, which is turned on before an input voltage is applied to the one capacitor electrode and cut off after the input voltage is applied. Output buffer circuit. 5. The output buffer circuit according to claim 2, wherein said output transistor and said diode-connected transistor have the same transistor size. 6. The output transistor is an n-channel transistor connected between a power supply voltage supply line and an output terminal, and the diode-connected transistor has a control electrode,
3. The output buffer circuit according to claim 2, wherein the output buffer circuit is an n-channel transistor in which two electrodes other than the control electrode are short-circuited to an electrode connected to the charge holding capacitor. 7. The transistor for output is a p-channel transistor connected between a reference voltage supply line and an output terminal, and the diode-connected transistor has a control electrode connected to the reference voltage supply line. 3. The output buffer circuit according to claim 2, wherein said output buffer circuit is a p-channel transistor. 8. An input cutoff switch between the input terminal and the voltage holding capacitor, which conducts before an input voltage is applied to the one capacitor electrode and cuts off after the input voltage is applied, wherein the switch comprises: The output buffer circuit according to claim 6, wherein the output buffer circuit is controlled so as to conduct before the input cutoff switch is cut off, and cut off at the same time as or slightly after the input cutoff switch. 9. An input cutoff switch between the input terminal and the voltage holding capacitor that conducts before an input voltage is applied to the one capacitor electrode and cuts off after the input voltage is applied, wherein the switch comprises: 8. The output buffer circuit according to claim 7, wherein the output buffer circuit is controlled to be turned off before the input cutoff switch is turned off, and to be turned on at the same time as or slightly after the cutoff of the input cutoff switch.