JPH053473A - Day scramble circuit - Google Patents

Abstract

(57) [Abstract] [Object] An object of the present invention is to provide a descrambling circuit which quickly starts a descrambling process when an input digital signal is supplied. [Structure] In addition to the first timing means forcibly synchronized with the sync pattern detection signal only when the sync pattern detection signal extracted from the input digital signal and the output sync position signal are in an asynchronous state, A second timing means synchronized by the synchronization pattern detection signal is provided, and the synchronization pattern position signal output by the second timing means when the asynchronous state is brought is added to the synchronization pattern position signal output by the first timing means. The descrambling processing circuit is controlled by the added signal. [Effect] The operation of the descrambling means can be advanced in timing as much as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a descramble circuit for restoring a scrambled digital signal.

[0002]

2. Description of the Related Art Conventionally, in order to improve reliability in recording / reproduction of information signals and data transmission, information signals are scrambled in advance, and then recording and data transmission are performed, and descramble processing is performed at the time of data demodulation. We are working to ensure error correction. For example, in the recording data format of the CD-ROM, one block is composed of 2352 bytes, but the data other than the sync pattern portion by the leading 12 bytes of each block is scrambled. Therefore, a descramble circuit is provided in the data demodulation section of the CD-ROM player.

A conventional example of such a descramble circuit will be described with reference to FIGS. A digital data input (DIN) signal, a bit clock (BCK) signal, and a left and right channel (LRCK) signal are supplied to the descrambling circuit shown in FIG. 5 from a disk playing unit of a CD-ROM player (not shown). The DIN signal is a digital data signal carrying a series of data blocks in which a data signal reproduced from a read signal obtained by playing a disc on which information is recorded is subjected to processing such as error correction in the first step, It is synchronized with the BCK signal. This DIN signal is supplied to the signal input terminal of the sync pattern detection circuit 1 and one input terminal of the exclusive OR circuit 2. BCK signal is DI
It is a so-called system clock signal synchronized with each bit of the N signal, and is supplied to each BCK clock input terminal of the sync pattern detection circuit 1 and the linear shift register circuit 3 in order to synchronize data processing. The LRCK signal corresponds to left and right channel data in the CD format, for example, 4
The clock signal is 4.1 KHz, and one cycle of this clock signal corresponds to 4 bytes of demodulated data, and 588 clocks of the LRCK signal corresponds to one data block. This LRCK signal is supplied to each clock input terminal of the flip-flop FF1 of the sync pattern detection circuit 1, the counter circuit 4, and the coincidence detection circuit 5.

The sync pattern detection circuit 1 uses the DIN
When a predetermined sync pattern displayed by 12 bytes for each data block is detected based on the signal, the BCK signal and the LRCK signal, the sync detection (SYD) signal corresponds to one clock of the LRCK signal as shown in FIG. It is generated and supplied to the coincidence detection circuit 5.

The counter circuit 4 counts the LRCK signal, and when the integrated value reaches the number corresponding to one data block, that is, 588, SR indicating a sync pattern period corresponding to 12 bytes.
The PS1 signal is generated, and this is generated by the linear shift register circuit 3
Supply to the preset input terminal of. In addition, the counter circuit 4
Eliminates the SRPS1 signal and simultaneously generates the MCL1 signal, which is supplied to the coincidence detection circuit 5. A part of the MCL1 signal supplied to the match detection circuit 5 is supplied as an MCL2 signal to the clear input terminal of the counter circuit 4 via the OR gate G1 of the match detection circuit 5. The counter circuit 4 resets the integrated value when the predetermined count value corresponding to one data block is reached by the MCL2 signal, and repeats the integration of the LRCK signal. The counter circuit 4 is provided and the linear shift register circuit 3 is operated by the SRPS1 signal regardless of the SYD signal, and the counter circuit 4 is reset by the MCL2 signal when the SYD signal does not occur or when the SYD signal is incorrect.
This is to prevent the malfunction of the linear shift register circuit 3 as much as possible when the D signal is generated.

The coincidence detection circuit 5 includes logic gates G1 to G5.
And a flip-flop FF1
Determine if the occurrence timings of both the signal and the MCL1 signal are synchronous. That is, AND gate G3
Generates a high level only when both the SYD signal and the MCL1 signal are at a high level (synchronous state), converts this to a low level signal via the NOR gate G5 and supplies it to the D input terminal of the flip-flop FF1. . This causes the next L
When the RCK signal rises, the Q output NGS signal is set to a low level indicating a synchronization state. When the AND gate G3 is outputting a low level (a state where synchronization coincidence is not detected), the NGS signal is low level (synchronization state) and M
When the CL1 signal becomes high level, the NOR gate G4 outputs low level. This output is converted to a high level via the NOR gate G5 and supplied to the D input terminal of the flip-flop FF1. As a result, when the LRCK signal rises next time, the NGS signal of Q output is set to a high level indicating an asynchronous state.

In this way, the NGS signal and the SYD signal and the MC
It is at a low level when it is synchronized with the L1 signal, and is at a high level when it is not synchronized. When the NGS signal is low level (synchronous state), only the MCL1 signal is input to the clear input terminal of the counter circuit 4 by the MCL by the OR gate G1.
Although it is relayed as two signals, when the NGS signal becomes high level (asynchronous state), the AND gate G2 opens and SY
The D signal is also relayed to the clear input terminal of the counter circuit 4 as the MCL2 signal, the integrated value is reset midway, and SYD
Pulling is performed so that the MCL1 signal is synchronized with the signal generation timing.

The linear shift register circuit 3 has the SRPS1
The signal is preset to "1" during the sync pattern period, and thereafter, the scramble data (SCD) signal is generated in synchronization with the BCK signal, and the exclusive OR circuit 2
Is supplied to the other input terminal of. The exclusive OR circuit 2 functions as an adder and adds the SCD signal to the DIN signal to obtain the descramble data DOUT.

[0009]

In such a descramble circuit, when a discontinuity occurs in the DIN signal due to a data search operation or the like, the counter circuit 4 is synchronized and the SRPS1 signal is generated from the time when the data discontinuity occurs. This is after the second sync pattern is supplied and the counter circuit 4 is synchronized. For example, D shown in FIG.
Although the data of the OUT signal block P does not generate an error in the data of the DIN signal but the SRPS1 signal does not occur, the descramble processing is not performed and normal data is obtained from the data block Q. . This delay in data processing causes a delay in data access speed, which hinders high-speed search.

Therefore, an object of the present invention is to provide a descrambling circuit which quickly starts a descrambling process when an input digital signal is supplied.

[0011]

In order to achieve the above object, the descramble circuit according to the first aspect of the present invention is arranged such that an input digital signal carrying a series of data blocks including a scrambled data signal and a sync pattern is synchronized with the sync pattern. Pattern detecting means for detecting a sync pattern and generating a sync pattern detection signal, and a first sync pattern position signal and a sync indicating the sync pattern in one data block and the position on the time axis at which the sync pattern detection signal should be generated, respectively. First timing means for repeating the generation of the position signal, and second timing means for generating a second synchronization pattern position signal which is cleared by the synchronization pattern detection signal and represents the position of the synchronization pattern in the data block on the time axis. , The scrambled data signal is decoded in response to the control signal. When the descramble processing means for performing the scrambling process to restore the original data signal is in synchronization with the synchronization pattern detection signal and the synchronization position signal, the descrambling process using the first synchronization pattern position signal as the control signal. When the sync pattern detection signal and the sync position signal are not synchronized with each other, the first and second sync pattern position signals are relayed to the descramble processing circuit as the control signal and the sync pattern is transmitted to the circuit. It is characterized by comprising coincidence detection means for supplying the detection signal as a clear signal to the first timing means.

The descramble circuit according to a second aspect of the present invention detects the sync pattern from an input digital signal that carries a series of data blocks including a scrambled data signal and a sync pattern, and generates a sync pattern detection signal. And a first clocking means for repeating the generation of the first synchronization pattern position signal and the synchronization position signal, which respectively indicate the position on the time axis at which the synchronization pattern and the synchronization pattern detection signal should be generated in one data block. And a third synchronization pattern position signal that is generated in response to the supply of the discontinuous display signal that indicates the discontinuity of the input digital signal, and that continues until the synchronization pattern detection signal is generated. The position signal generating means and the data signal subjected to the scramble processing in response to the control signal are descrambled. The descramble processing means for performing scramble processing to restore the original data signal, and the descramble processing circuit using the first synchronization pattern position signal as the control signal when the synchronization pattern detection signal and the synchronization position signal are synchronized. When the discontinuous display signal is generated, the first and third synchronization pattern position signals are relayed to the descrambling processing circuit as the control signals and the synchronization pattern detection signal is used as the clear signal. It is characterized in that it is provided with a coincidence detecting means for supplying to the time measuring means.

[0013]

According to the first aspect of the invention, in addition to the first timing means forcibly synchronized with the sync pattern detection signal only when the sync pattern detection signal and the sync position signal are in an asynchronous state, Two timing means are provided. The second timing means is always synchronized by the sync pattern detection signal. The synchronization pattern position signal output by the second timing means when the above-mentioned asynchronous state is achieved is added to the synchronization pattern position signal output by the first timing means.

This makes it possible to accelerate the operation of the descramble processing means as early as possible.

In the second aspect of the invention, attention is paid to the fact that the digital signal becomes discontinuous when data is searched for in a disc player or the like. For example, a search signal indicating a search state is determined by discontinuing the input digital signal. It is used as a discontinuous display signal. When the discontinuous display signal is generated, the coincidence detection means is forcibly set to the asynchronous detection state, and the descrambling processing circuit is put on standby so that it can be operated immediately after detecting the synchronization pattern detection signal.
A synchronization pattern position signal generating means is provided.

As a result, the descramble processing of the input digital data signal after the search is completed can be performed as quickly as possible.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The parts corresponding to those of the descrambling circuit shown in FIG. 5 are designated by the same reference numerals, and the description of those parts will be omitted.

In the first embodiment, logic gates G6 and G7 and a counter circuit 6 are added to the conventional circuit. The counter circuit 6 serving as the second timing means has the same configuration as the counter circuit 4 serving as the first timing means, and is reset by the SYD signal which is the synchronization pattern detection signal supplied from the sync pattern detection circuit 1 and is synchronized with the SYD signal. , Starts counting the LRCK signal supplied to the clock input terminal. When the pulses of the LRCK signal are integrated and the count value becomes 588, the SRPS2 signal which is the second synchronization pattern position signal is generated. The SRPS2 signal indicates the period in which the sync pattern of the data block occurs, and the AND gate G6
Is supplied to one input terminal. The NGS signal is supplied from the flip-flop FF1 to the other input end of the AND gate G6. When the NGS signal is low level indicating the synchronization state,
The SRPS2 signal is blocked from passing through the AND gate G6. When the NGS signal is low level indicating an asynchronous state, S
The RPS2 signal passes through the AND gate G6 and is supplied to one input end of the OR gate G7. The SRPS1 signal output from the counter circuit 4 is supplied to the other input terminal of the OR gate G7. OR gate G7 is SRPS1 signal and S
When any one of the RPS2 signals is supplied, this is used as an SRPS3 signal which is a control signal, and the linear shift register circuit 3
Supply to the preset input terminal of. The other structure is the same as the conventional circuit.

Therefore, the linear shift register circuit 3 is preset by the output of the counter circuit 4 in the synchronous state and is further preset by the output of the counter circuit 6 in the asynchronous state.

Next, the operation of the descramble circuit will be described with reference to FIG. The structure of the coincidence detection circuit 5 is the same as that of the conventional circuit, and the DIN signal and the counter circuit 4 are
When and are in sync, the NGS signal remains low. Therefore, the AND gate G6 is closed and SR
Only the PS1 signal is supplied to the linear shift register circuit 3 via the OR gate G7 and operates as in the conventional circuit.

When data discontinuity occurs in the DIN signal due to a data search operation or the like, the generation timings of the SYD signal and the MCL1 signal differ, and the AND gate G3 continues to output a low level. The NOR gate G4 outputs a high level when both the MCL1 signal and the NGS signal are low levels, and supplies the low level to the flip-flop FF1 via the NOR gate G5. However, when the MCL1 signal is generated, the AND gate G3 is at a low level and the NOR gate G4 is
Becomes a low level, the output of the NOR gate G5 becomes a high level, and the high level is supplied to the D input of the flip-flop FF1.
The Q output is set to a high level at the next rise of the LRCK signal. As a result, the NGS signal is at a high level (asynchronous state)
The AND gate G6 is opened, and the SRPS2 signal output from the counter circuit 6 is relayed to one input terminal of the OR gate G7. The counter circuit 6 is always cleared by the SYD signal. The SRPS3 signal output from the OR gate G7 is SRP only when it is in the asynchronous state with the SRPS1 signal.
It has a structure to which the S2 signal is added. On the other hand, the counter circuit 4 is reset by the first SYD signal after the asynchronous state is detected and the NGS signal becomes high level by the action of the AND gate G2. In other words, the operations of the counter circuit 4 and the counter circuit 6 are both S
Although the counter circuit 4 is synchronized with the YD signal, the counter circuit 4 is synchronized with the counter circuit 6 when it is in an asynchronous state in order to prevent malfunction due to an incorrect SYD signal, whereas the counter circuit 6 is always SY.
The two operations differ in that they are synchronized by the D signal.

As a result, the counter circuit 6 is synchronized by the first sync pattern after discontinuity, and its output SRP
The linear shift register is preset by S2. Therefore, as shown in the timing chart of FIG. 3, a discontinuity occurs in the input data and the normally descrambled DOUT signal can be obtained from the data of the second block P.

A second embodiment will be described with reference to FIG.
2, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and description of those parts will be omitted.

In this embodiment, a search (SRCH) signal obtained from a disc playing unit (not shown) is used,
It attempts to deal with the discontinuity of data that occurs immediately after the search. When the search is instructed, the disc playing section calculates the difference between the address currently being played and the target address, drives the pickup according to the address difference, and converges the information reading spot on the target track to set the target address. It has a function of performing a search operation for restarting the reading of information from. The SRCH signal is a signal showing a high level during the period from the start of the search operation to the end of the search operation.

In the descrambling circuit shown in FIG. 2, the flip-flop circuit FF1 is changed to one having a set input terminal, and further the flip-flop circuit FF2.
And, a NOR gate G8 is added.

The SRCH signal is supplied to each set input terminal of the flip-flop circuits FF1 and FF2. A low level is always applied to the D input terminal of the flip-flop circuit FF2, and the SYD signal is supplied to the clock input terminal.
The Q output of the flip-flop circuit FF2 is supplied to one input end of the OR gate G8 as the SRCHQ signal which is the third synchronization pattern position signal. The SRPS1 signal is supplied to the other input terminal of the OR gate G8. OR gate G8 is S
When either the RPS1 signal or the SRCHQ signal is supplied, this is supplied to the preset input terminal of the linear shift register circuit 3 as the SRPS4 signal which is a control signal.
Other configurations are similar to those of the conventional circuit.

Next, the operation of the descrambling circuit will be described with reference to FIG.

The configurations of the counter circuit 4 and the coincidence detection circuit 5 are substantially the same as those of the conventional circuit, and the operation of the conventional circuit is fully provided. That is, if the SYD signal and the MCL1 signal are not synchronized, the logic gates G3 to G5 detect the non-synchronization, set the output NGS signal of the flip-flop FF1 to a high level, and open the AND gate G2 to open the SYD signal.
The signal is supplied to the clear input terminal of the counter circuit 4, and the MCL
1 signal and SRPS1 signal are synchronized. Logic gate G
When 3 and G5 detect the synchronization between the SYD signal and the MCL1 signal, the NGS signal which is the output of the flip-flop FF1 is set to the low level, the gate 2 is closed, and the SYD signal is not captured. SRPS1 output by the counter circuit 4
The signal becomes the SRPS4 signal via the OR gate G8 and is supplied to the preset input terminal of the linear shift register circuit 3.

When the disc playing portion starts the search operation, the SRCH signal becomes high level, and the high level is maintained until the search operation is completed. When the SRCH signal becomes high level, the high level is applied to each set S input terminal of the flip-flops FF1 and FF2, and the Q output of each flip-flop is set to the high level. Flip flop F
F2 supplies the SRCHQ signal, which is the Q output, as a high level to the OR gate G8. The flip-flop FF2 is S
After the RCH signal goes low, the S
When the YD signal is supplied, the low level applied to the D input terminal is set to the Q output, and the SRCHQ signal is set to the low level.

The flip-flop FF1 is a high level SR
When the CH signal is supplied to the set input terminal, the Q output is N
Set the GS signal to high level for asynchronous status display,
The gate G2 is opened to supply the SYD signal to the counter circuit 4. As a result, the MCL1 signal and the SRPS1 signal are synchronized with the SYD signal whose time axis has changed due to the search operation. The SRCHQ signal and the SRPS1 signal are combined by the OR gate G8 to form the SRPS4 signal, which is supplied to the preset input terminal of the linear shift register circuit 3.

Therefore, a high level is forcibly applied to the preset input terminal of the linear shift register circuit 3 from immediately after the search operation is started until the search operation ends and the first SYD signal is demodulated. The preset state is maintained, and the descrambling process is started at the same time as the supply of the SYD signal. After that, the synchronous output SR of the counter circuit 4
Presets are controlled by the PS1 signal.

In this way, even when the input data is discontinuous due to the track search, the DOUT output that has been normally descrambled can be immediately obtained if the sync pattern can be detected.

The present invention is not limited to the CD-ROM,
It can also be used for a descramble circuit in wired and wireless data transmission, digital data demodulation of broadcast signals and the like.

[0034]

As described above, the descramble circuit of the present invention can quickly start the descrambling process when the input data signal is supplied even if the input data signal is discontinuous due to a search operation or the like. Is possible.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a timing chart showing generation timing of each signal in the block circuit diagram of the first embodiment.

FIG. 4 is a timing chart showing generation timing of each signal in the block circuit diagram of the second embodiment.

FIG. 5 is a block circuit diagram showing a conventional example.

FIG. 6 is a timing chart showing generation timing of each signal in the block circuit diagram of the conventional example.

[Explanation of symbols] 1 Sync pattern detection circuit 2 Exclusive OR gate circuit 3 Linear shift register 4 counter circuit 5 Match detection circuit 6 counter circuit

Claims (2)

[Claims] 1. A sync pattern detecting means for detecting the sync pattern from an input digital signal which carries a series of data blocks including a scrambled data signal and a sync pattern and generating a sync pattern detection signal, and one data block. In the above, the first synchronization pattern position signal indicating the position on the time axis at which the synchronization pattern and the synchronization pattern detection signal should be generated, respectively, and a first timing means for repeating generation of the synchronization position signal, and being cleared by the synchronization pattern detection signal. Second clocking means for generating a second sync pattern position signal representing the position of the sync pattern on the time axis in the data block, and descramble processing is performed on the scrambled data signal in response to a control signal. A descramble processing means for performing and restoring the original data signal, When the synchronization pattern detection signal and the synchronization position signal are synchronized, the first synchronization pattern position signal is relayed to the descramble processing means as the control signal, and the synchronization pattern detection signal and the synchronization position signal are synchronized. When not, the first and the second
A descramble circuit comprising: a synchronization pattern position signal as the control signal, which is relayed to the descramble processing means; and a coincidence detection means which supplies the synchronization pattern detection signal as a clear signal to the first timing means. . 2. A sync pattern detecting means for detecting the sync pattern from an input digital signal which carries a series of data blocks including a scrambled data signal and a sync pattern and generating a sync pattern detection signal, and one data block. In the first time counting means for repeating the generation of the first synchronization pattern position signal and the synchronization position signal respectively representing the position on the time axis at which the synchronization pattern and the synchronization pattern detection signal should be generated, and the discontinuity of the input digital signal. Responsive to a control signal and a third sync pattern position signal generating means for generating a third sync pattern position signal in response to the supply of the discontinuous display signal, and continuing this until the sync pattern detection signal is generated. Then, descramble processing is performed on the scrambled data signal to restore the original data signal. When the descrambling processing means and the synchronization pattern detection signal and the synchronization position signal are in synchronization, the first synchronization pattern position signal is relayed to the descrambling processing means as the control signal, and the discontinuous display signal is Coincidence detection means for relaying the first and third synchronization pattern position signals as the control signals to the descrambling processing means when they occur and supplying the synchronization pattern detection signals as clear signals to the first timing means; A descrambling circuit comprising: