JPH0535521A - Input circuit - Google Patents

Abstract

PURPOSE:To shorten the test time despite the increase of the number of ports and to prevent the increase of the check cost the of an integrated circuit by providing the input buffers to receive the signals inputted to the data input terminals and the gates which receive all output signals of the input buffers. CONSTITUTION:The data input terminals I0-I7 are provided together with the input buffers 1a0-1a7 which receive the signals inputted to the terminals I0-I7, and the gates 1f and 1i which receive all output signals of the buffers 1a0-1a7. Then the output signals of the bus buffers of a port 2a0 that are selected by the control signals TSTH and TSTL are connected to a bit 0 of an internal bus 2b. At the same time, the output signals of the bus buffers of a port 2a1 are successively connected to a bit 1 of the bus 2b. The outputs of the bus buffers selected by both signals TSTH and TSTL are transmitted to a CPU via the bus 2b. The CPU decides the data equivalent to 8 bits of the bus 2b and at the same time performs the tests of 64 input buffers at one time. Thus the test time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to an input buffer provided on an integrated circuit chip.

[0002]

2. Description of the Related Art Generally, an input circuit incorporated in a microcomputer constitutes one group (port) with eight terminals, and data is input by executing a data input instruction for each port.

FIG. 3 shows a conventional example of such an input circuit.
Ports are shown. In FIG. 3, the buffer 3a0
Is an input buffer for receiving the signal 3b0 input to the data input terminal 10, and the buffer 3c0 is a bus buffer for receiving the output signal 3d0 of the input buffer 3a0 and driving the internal bus 3e by the read signal RD from the CPU (not shown). , Similar circuits for each data input terminal (8)
Only have.

The test of the input buffers 3o0-3a7 is as follows.
A high level voltage or a low level voltage is applied to the data input terminals I0 to I7, the CPU executes a (read) instruction to read the data of the data input terminal, and the read signal RD reads and inputs the data via the internal bus 3e. Determine the level.

[0005]

In the above-mentioned conventional input circuit, when the input buffer is tested, an input instruction is executed for each port to determine the input level. Therefore, when the number of ports increases, There is a drawback that the test time becomes long and the inspection cost of the integrated circuit increases.

An object of the present invention is to solve the above-mentioned drawbacks and to provide an input circuit which can be inspected in a short time.

[0007]

An input circuit according to the present invention has a plurality of data input terminals, each input buffer receiving a signal input to the data input terminal, and all output signals of the input buffer. And a gate for receiving.

[0008]

1 is a block diagram showing an input circuit according to an embodiment of the present invention.

Referring to FIG. 1, the input circuit of one embodiment of the present invention receives the signal 1b0 input to the data input terminal 10, receives the input buffer 1a0 and the output signal 1d0 of the input buffer 1a0, and reads them from the CPU. A bus buffer 1c0 for driving the internal bus 1e by a signal RD.
Only).

Further, an AND gate 1f receiving the output signals 1d0-7 of the input buffers 1a0-7 and an output signal 1h of the AND gate 1f receiving a control signal TST from the CPU.
Bus buffer 1 that drives internal bus 1e by H
g, an OR gate 1i receiving the output signals 1d0 to 7 of the input buffers 1a0 to 7 and an output signal 1k of the OR gate 1i, and an internal bus 1e in response to a control signal TSTL from the CPU.
Bus buffers 1j, which drive the.
Here, the bus buffer 1g and the bus buffer 1j can have only one output signal to the internal bus 1e by selecting only one of the control signals TSTH and TSTL.

In the test of the input buffer, when a high level is applied to the data input terminals I0 to 7 and the output signals 1a0 to 7 of all the input buffers 1a0 to 7 become high, the output signal 1h of the AND gate 1f becomes high. And the output of the bus buffer 1g also goes high. Also, the data input terminals I0 to I0
A low level is applied to 7, and all input buffers 1a0
When the output signals 1d0 to 7 of ~ 7 become low, the output signal 1k of the OR gate 1i becomes low and the output of the bus buffer 1j also becomes low. The CPU reads the data on the internal bus 1e and determines the input level.

FIG. 2 is a block diagram when testing the eight ports of FIG. 1, and all the ports 2a0-7 are the same as the input circuit shown in FIG.

In FIG. 2, control signals TSTH and TS
The output signal of the bus buffer of port 2a0 selected by TL is connected to bit 0 of internal bus 2b,
The output signal of the bus buffer 1 (not shown) is transferred to the internal bus 2
Sequentially connect to bit 1 of b. The output of the bus buffer selected by the control signal TSTH or TSTL is the internal bus 2
sent to the CPU via the internal bus 2b
When the bit data is determined, 64 input buffers are tested at the same time.

[0014]

As described above, according to the present invention, a large number of input buffers can be tested at a time by adding a small number of gates, so that the test time can be shortened even if the number of ports is increased. This has the effect of suppressing an increase in the inspection cost of the integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an input circuit for one port according to an embodiment of the present invention.

FIG. 2 is a block diagram of an input circuit for eight ports in FIG.

FIG. 3 is a block diagram of a conventional input circuit.

[Explanation of reference numerals] I0 to I7, I00 to I07, I70 to I77 Input terminals 1a0 to 1a7, 3a0 to 3a7 Input buffers 1c0 to 1c7, 3c0 to 3c7, 1g, 1j Bus buffers 1e, 2b, 3e Internal bus 1f AND gate 1i OR gate 2a0 to 2a7 port RD, RD0, to RD7, TSTH, TSTL control signal

Claims (1)

Claim: What is claimed is: 1. A plurality of data input terminals, an input buffer for receiving signals respectively input to the data input terminals, and a gate for receiving all output signals of the input buffer. Input circuit characterized by.