JPH0535937B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a timing extraction circuit, and particularly to a timing extraction circuit.
This invention relates to a timing extraction circuit that extracts timing information (clock signal) from a CMI-encoded input signal.

[Prior art]

CMI (Coded Mark Inversion) code is a binary NRZ (non-return to zero) transmission code that has good DC balance and does not lose timing information, and is configured to prevent the generation of consecutive “0” and “1”. Although it requires a transmission bandwidth twice as large as the required bandwidth of the original information signal, it has the advantage that the timing information is constantly transmitted and the clock signal can be easily regenerated on the receiving side. In recent years, it has become widely used in optical transmission lines with plenty of room and digital transmission systems with small to medium capacity. In order to reproduce a clock signal from this CMI code on the receiving side, conventionally, a method is generally used in which the input signal is passed through a tuning circuit to extract the frequency spectrum components of the transmitted clock signal.

[Problems to be solved by the invention]

Although this method is simple, it is possible to use LC as a tuned circuit.
Since it includes a circuit, it is necessary to change parts or adjust the circuit when the clock frequency changes, and it has the disadvantage that it is not suitable for IC implementation. Furthermore, if the bit rate of the original information signal becomes high, the Q of the tuning circuit cannot be set high, so that there is a drawback that only the frequency component of the clock signal is not completely separated and phase jitter increases.
An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a timing extraction circuit that can be easily integrated into an IC without using an LC tuning circuit, and can extract a stable clock signal with little phase jitter.

[Means to solve the problem]

The timing extraction circuit of the present invention includes a voltage controlled oscillator that can oscillate the clock frequency of the CMI code,
A flip-flop circuit that samples a CMI-encoded input signal using the output of the voltage-controlled oscillator, and a low-pass filter connected to the output of the flip-flop circuit, and controls the voltage-controlled oscillator using the output of the low-pass filter. is configured to do so.

[Effect]

Next, the present invention will be explained in detail with reference to the drawings.
FIG. 1 is a block diagram of the basic configuration for explaining the operation of the present invention, in which a voltage controlled oscillator (VCO) 1 capable of oscillating a CMI code clock frequency _p and a CMI coded input signal applied to input terminal D are shown. Flip-flop circuit (FF) that samples with the output of VCO1 applied to timing terminal C
2 and a low-pass filter (LPF) 3 connected to the output terminal Q of the FF 2, and is configured to control the VCO 1 with the output of the LPF 3.

FIG. 2 is a waveform diagram showing an example of the configuration of a CMI code, in which the information bit "0" (original information signal) is made to correspond to two codes "0, 1" at twice the bit rate, and the information bit "1" is ” to “1, 1” or “0,
This is a binary NRZ code that is configured to be sent out alternately in correspondence with one of the 0's.With this code, the clock frequency information of the information bit rate is transmitted even when there is no input (information bits are continuous 0's). is transmitted, so the clock signal can always be regenerated on the receiving side and timing information will not be lost.

As shown in Figure 2, in a CMI-encoded signal, the sign change at the midpoint _tc of the time slot T of the information bit is always a rising edge (0→1) and a falling edge (1→0). do not. Therefore, the first
As shown in the figure, VCO is connected to timing terminal C of FF2.
When an output of 1 is supplied, if the phase of the output of VCO 1 (the time when the output changes from negative to positive) is ahead of the midpoint t _c of time slot T and the sampling time is t ₁ in Fig. 2, then The output of FF2 for the information bit "0" is "1", and conversely, it lags behind _tc and the sampling time is _T2 .
The output of FF2 becomes "0". Therefore, Q of FF2
Add the output to VCO1 via LPF3 and apply the Q of FF2.
When the output is "1" (when the output of LPF3 becomes large), the frequency of VCO1 is lowered (delayed phase), and when the output is "0" (when the output of LPF3 becomes small), the frequency of VCO1 is lowered (delayed phase). If the frequency of FF2 is controlled to be raised (advance the phase), FF2
The phase of the output of the VCO 1 is controlled so that the ratio of "1" and "0" of the Q output of the VCO 1 is the same, that is, the sampling time is _tc . In addition,
When the information bit is "1", neither rising nor falling edges appear at the _tc point, so there is no effect on the control information. At the boundary point _tb of each time slot, both rising and falling signs occur, but since there is no regularity, the output phase of the VCO 1 is not locked to _tb . In this method, since the phase jitter of the VCO 1 is determined by the characteristics of the LPF 3, the phase jitter does not deteriorate even if the clock frequency becomes high.

The above explanation shows that the CMI code waveform is complete and VCO1
Although the amplitude of the output sine wave was assumed to be sufficiently large, it is easy to understand that almost the same operation can be performed even if the waveform is not perfect.

〔Example〕

FIG. 3 is a block diagram of one embodiment of the present invention, and shows a CMI using the timing extraction circuit of the present invention.
Part of the code decoder is shown. In Figure 3, VCO1, FF2, LPF3 and delay line (DL)
DL4 constitutes a timing extraction circuit similar to that shown in FIG.
The VCO is set at the midpoint _tc of the time slot T.
1 is controlled. FF5 and FF6 are input signal 10
0 branch signal, FF2 timing signal 101
This is a decoding circuit that samples with a timing signal (output of DL7) 102 whose phase is delayed by T/4 and a timing signal (output of DL8) 103 whose phase is advanced by T/4. According to this circuit, if the delay times of DL7 and DL8 are correctly selected with respect to the delay time of DL4, the sampling time is automatically adjusted to the optimum sampling time.

〔Effect of the invention〕

As explained in detail above, according to the timing extraction circuit of the present invention, it is possible to stably extract a clock signal without using an LC circuit, it can easily respond to changes in clock frequency, and it can be integrated into an IC. It also has the effect of making it easier.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the basic configuration of the present invention, Figure 2 is a block diagram of the basic configuration of the present invention.
The figure is a waveform diagram showing an example of the configuration of a CMI code, and FIG. 3 is a block diagram of an embodiment of the present invention. 1... Voltage controlled oscillator (VCO), 2, 5, 6...
...Flip-flop circuit (FF), 3...Low pass filter (LPF), 4, 7, 8...Delay line (DL).

Claims (1)

[Claims] 1. A voltage controlled oscillator that can oscillate the CMI code clock frequency, and the output of this voltage controlled oscillator.
comprising a flip-flop circuit for sampling a CMI-encoded input signal and a low-pass filter connected to the output of the flip-flop circuit;
A timing extraction circuit characterized in that the circuit is configured to control the voltage controlled oscillator using the output of the low-pass filter.