JPH0536298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To detect the failure such as the short-circuit of the boosted nodal point in a short time by stopping the supply of a charge to the boosted nodal point. CONSTITUTION:A control circuit 3 to control the supply of a charge to a boosted nodal point A of a charge supply circuit 2 is provided. When the control circuit is set to a test mode by an internal test mode signal TI and a control signal from an external part satisfies the prescribed conditions, the charge supplying action of the charge supply circuit 2 is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device including a circuit that performs a predetermined function by a signal obtained by boosting a power supply voltage supplied from the outside.

[0002]

2. Description of the Related Art Generally, a word line or the like of a semiconductor memory device is boosted by a booster circuit to a voltage higher than a power supply voltage supplied from the outside during a selection operation. After boosting, the boosted potential is generally ensured at the boosted node by a charge supply circuit that operates by receiving an asynchronous oscillator output or the like in the semiconductor memory device.

FIG. 6 shows an example of a conventional semiconductor memory device.

In this example, a booster circuit (not shown) for boosting a power supply voltage supplied from the outside to generate a boost signal,
An internal circuit (not shown) provided with a boosted node A and having a predetermined function according to the boosted signal supplied to the boosted node A, and supplying electric charges to the boosted node A according to the boosted signal to boost the boosted node A. And a charge supply source circuit 2a for keeping the voltage at a predetermined potential.

Next, the operation of this example will be described.

When the node A to be boosted exceeds the power supply voltage by the boost signal, the transistor Q1 turns on and
The output level of the NAND gate G1 changes in synchronization with the output of the oscillator 1. Accordingly, the voltage at the gate and drain of the transistor Q3 is boosted by the capacitor C1,
Charges are replenished to the node A to be boosted through the transistors Q1, Q2 and Q3. In this way, the boosted node A is held at the potential boosted by the boosting signal.

[0007]

SUMMARY OF THE INVENTION Here, the boosted node A
Consider a case where a short circuit occurs with a node having a different potential lower than the potential of the boosting signal. The resistance of this short-circuit portion is sufficiently large, and the time constant with the capacitance of the node A to be boosted is assumed to be larger than the cycle of the output signal of the oscillator 1 input to the charge supply circuit 2a. The potential change at the node A to be boosted when such a short circuit occurs is as shown by the curve C3 in FIG. The potential of the boosted node A gradually drops while receiving the supply from the charge supply circuit 2a. Therefore, it takes a sufficiently long time for the potential of the node A to be boosted to lose the boosted potential.

Therefore, there is a problem that a sufficiently long test time is required to detect a defect due to the boosted node A losing the boosted potential.

An object of the present invention is to provide a semiconductor memory device capable of detecting a defect such as a short circuit of a node to be boosted in a short time.

[0010]

A semiconductor memory device of the present invention includes a booster circuit for boosting a power supply voltage supplied from the outside to generate a boosted signal, and a boosted node, which is supplied to the boosted node. An internal circuit that performs a predetermined function according to the boosting signal, a charge supply source that supplies charges to the boosted node according to the boosting signal to maintain the boosted node at a predetermined potential, and a test mode by an external test mode signal. And a charge supply control circuit for stopping the supply of charges to the boosted node of the charge supply source when a control signal from the outside satisfies a specific condition.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 6 in that a NAND gate G2 is provided between the boosted node A and one input terminal of the NAND gate G1.
The charge supply circuit 2 includes a G3 and an inverter IV1 and is set to a test mode by an external test mode signal (TST) and the external control signals (LCH, AD) satisfy a specific condition. The control circuit 3 for stopping the supply of the electric charge to the boosted node A is provided.

The fact that the test mode is set by the test mode signal TST from the outside means that the internal test mode signal TI generated by the test mode entry circuit 4 shown in FIG.
The internal clock signal CKI output from the internal clock generation circuit 5 shown in FIG. 3 is used to determine whether the external control signals (address latch signal LCH, external address signal AD) satisfy a specific condition. To detect.

Next, the operation of this embodiment will be described.

The test mode is set by setting the test mode signal TST to a higher potential than the normal high level, and the internal test mode signal TI becomes high level.

The internal clock generation circuit 5 latches the external address signal AD when the address latch signal LCH is at the high level, and latches the internal clock signal CKI at the low level when the address latch signal LCH is at the low level,
When it is at a high level, it is made a high level output or a low level output by the external address signal AD.

Now, it is assumed that the test mode signal TST has a high potential and the test mode is set. When the internal test mode signal TI is high level and the external address signal AD is low level, the internal clock signal CKI becomes high level and NA
The output of the ND gate G2 is at a low level, the output of the control circuit 3 is at a low level, and the output of the NAND gate G1 is fixed at a high level, so that the charge supply source circuit 2 is in a non-operating state and goes to the boosted node A. The supply of the electric potential of is stopped. At this time, if there is a short circuit between the boosted node A and the low potential node as described above, the potential OUT of the boosted node A is short-circuited to the boosted node A as shown by the curve C1 in FIG. The potential decreases according to the time constant determined by the resistance and capacitance,
Settle to the potential of another low potential node. Further, since the charge supply source circuit 2 becomes non-operation in synchronization with a control signal from the outside, the electric charge supply circuit 2 becomes non-operation at a timing when the potential of the boosted node A does not change due to interference noise or the like in a stable state inside the semiconductor memory device. It is possible to

In the first embodiment, the case in which only the charge supply source circuit 2 for ensuring the boosted potential to the boosted node A is inoperative in the test mode has been described, but the electric supply to the boosted node A is supplied. When all the sources are inoperative, the node A to be boosted is brought into a completely floating state, so that the final potential of the node A to be boosted drops to the potential of the short-circuited different potential portion, as shown by the curve C2 in FIG. It is possible. In this case, there is an advantage that it is easier to detect a defect in the boosted node A.

FIG. 5 shows an example of a charge supply control circuit for the node A to be boosted according to the second embodiment of the present invention.

PRC is a precharge signal AS is a selection signal at the time of activation, and VH is an output signal of the boosted potential supply source.

In operation, since the selection signal AS is at a low level and the gate of the transistor Q26 is precharged to a high potential, the boosted potential is given to the boosted node A by the output signal VH.

When the test mode is set, the internal test mode signal TI is at the high level, and when the external address AD is at the low level, the internal clock signal CKI is at the high level, and the gate of the transistor Q24 is at the high level. The gate becomes low level, the supply of electric charges from the boosted potential supply source is stopped, and the node A to be boosted is brought into a completely floating state.

Therefore, as described above, when the boosted node A is short-circuited with the low potential part, the potential of the boosted node A is lowered to the potential of the different potential part, and the defect detection becomes easy.

[0025]

As described above, according to the present invention, the supply of the electric charge of the charge supply source circuit to the boosted node A is stopped in the test mode, so that the potential drop of the boosted node can be accelerated. Therefore, there is an effect that the defective portion can be detected in a short time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a test mode entry circuit for generating an internal test mode signal of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a specific example of an internal clock signal generation circuit for generating an internal clock signal of the embodiment shown in FIG.

FIG. 4 is a potential waveform diagram of a node to be boosted for explaining the operation and effect of the embodiment shown in FIG.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

1 oscillator 2,2a Charge supply circuit 3 control circuit 4 Test mode entry circuit 5 Internal clock generation circuit 6 Precharge circuit 7 Charge supply control circuit C1 capacitor G1 to G4 NAND gate IV1-IV8 inverter Q1 to Q27 transistors

Claims (2)

[Claims] 1. A booster circuit which boosts a power supply voltage supplied from the outside to generate a boosted signal, and an internal circuit which has a boosted node and performs a predetermined function according to the boosted signal supplied to the boosted node. , A charge supply source for supplying electric charge to the boosted node according to the boosting signal to keep the boosted node at a predetermined potential, and a test mode set by an external test mode signal and a specific external control signal. And a charge supply control circuit for stopping the supply of charges to the boosted node of the charge supply source when the conditions are satisfied. 2. A charge supply source disconnection control circuit for electrically disconnecting the node to be boosted from all the charge supplies when the test mode is set and the control signal satisfies a specific condition. Semiconductor memory device.