JPH0536722A - Manufacture of thin film transistor - Google Patents

Abstract

(57) [Summary] [Objective] In the process of removing the natural oxide film on the surface of the lower electrode layer exposed by the contact hole opened in the gate oxide film, the gate oxide film is protected from corrosion and stable. Maintain gate oxide. [Constitution] Amorphous silicon is deposited on the gate oxide film 13 to form a protective layer 14a, a contact hole 15 is opened, and then a surface of the lower gate electrode layer 12 exposed by the contact hole 15 is formed. The natural oxide film was etched and removed by dilute hydrofluoric acid treatment or the like, and at this time, the gate oxide film 13 was protected by the protective layer 14a from corrosion. Then, the protective layer 14a
By depositing amorphous silicon over the entire surface of the contact hole 15, the active layer 14 connected to the gate electrode layer 12 is formed in the contact hole 15, and the bottom gate type TFT is manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is, for example, a stack type S
The present invention relates to a method of manufacturing a bottom gate type thin film transistor formed on a bulk transistor of a RAM (static RAM).

[0002]

2. Description of the Related Art A stack type S formed on a semiconductor substrate
Attempts have been made to form a bottom gate type thin film transistor (TFT) on the surface layer of a RAM via an interlayer insulating film. In such a TFT, the gate oxide film and the active layer are laminated in this order on the gate electrode layer. Since the active layer needs to make contact with the gate electrode layer therebelow or another electrode layer that is further laminated thereunder, after the gate oxide film is laminated,
It is necessary to form a contact hole in the gate oxide film. After forming the contact hole by etching or the like, it is necessary to remove the natural oxide film formed on the surface of the electrode layer exposed in the contact hole, and immediately after that, stack the active layer. This is because if the natural oxide film remains, the contact resistance in the contact hole between the active layer and the gate electrode layer increases. That is, at a stage immediately before depositing amorphous silicon or the like on the gate oxide film 13 to form an active layer, the natural oxide film on the surface of the lower electrode layer exposed by the contact hole is treated by dilute hydrofluoric acid treatment or the like. Must be etched away.

[0003]

However, in the step of removing the natural oxide film, the gate oxide film may be eroded by the dilute hydrofluoric acid. The thickness of the gate oxide film depends on the type of semiconductor device, but is 300 to
The film thickness is limited to about several hundred angstroms, and since the film is usually formed by the LPCVD method, the thickness is likely to vary and the diluted hydrofluoric acid treatment may cause the film to be too thin. Therefore, it is possible to form the gate oxide film 13 with a large film thickness in consideration of this erosion, but it cannot be formed too thick due to the characteristics of the gate oxide film. Therefore, there is a problem that the dielectric breakdown resistance of the gate oxide film deteriorates. In addition, there is a problem that the dielectric breakdown voltage of the gate oxide film 13 may locally deteriorate due to local erosion. It is also possible to treat the surface of the electrode layer with dilute hydrofluoric acid with some protective film attached to the surface of the gate oxide film. In that case, the active layer should be removed after removing the protective film. An operation for forming is required, and the number of steps is increased. Further, the surface of the electrode layer formed of polysilicon or the like is very easily oxidized, and a natural oxide film is generated during the formation of the active layer by removing the protective film, and the natural oxide film cannot be removed. There is a disadvantage to say.

The present invention has been made in view of the above-mentioned circumstances, and is effectively performed in the step of removing the natural oxide film on the surface of the lower electrode layer exposed by the contact hole opened in the gate oxide film. It is an object of the present invention to provide a method for manufacturing a thin film transistor, which can remove a natural oxide film, protect the gate oxide film from corrosion, and maintain a stable gate oxide film.

[0005]

In order to achieve the above object, the manufacturing method of the present invention comprises: a first step of forming a gate oxide film on a gate electrode layer; and a step of forming a gate oxide film on the gate oxide film.
The second step of forming a protective layer by depositing a layer of a material that constitutes the active layer, and opening a contact hole at a specific portion of the protective layer and the gate oxide film, and forming a gate electrode layer or another layer underneath. A third step of exposing the surface of the electrode layer, a fourth step of etching and removing a natural oxide film on the surface of the electrode layer exposed by the contact hole, and a step of removing the protective layer and the contact hole. A fifth step of depositing a layer of a material forming an active layer over the entire surface and forming an active layer connected to the gate electrode layer in the contact hole.

[0006]

According to the above-mentioned manufacturing method, the contact hole is opened after the protective layer is formed by depositing the layer of the material forming the active layer on the gate oxide film. In the step of removing the exposed native oxide film on the surface of the lower electrode layer by dilute hydrofluoric acid treatment or the like, the protective layer protects the gate oxide film from erosion.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are views showing a manufacturing process according to an embodiment of the present invention. In this embodiment, an N type silicon substrate 1 is prepared, a P well 2 is formed on the N type silicon substrate 1, and the P well 2 is formed.
A field oxide film 3 is formed on the surface of the silicon substrate in the well 2.
A is formed, element isolation is performed, and the source and drain regions of the LDD structure are formed. The source and drain regions of the LDD structure are composed of a low concentration N ⁻ diffusion layer 4 and a high concentration N ⁺ diffusion layer 5.

After that, the gate oxide film 3b is formed on the surface of the substrate.
Is formed, and the first electrode layer 6 and the first auxiliary electrode layer 7 to be word lines are laminated in a predetermined pattern on the gate oxide film 3b. The first electrode layer 6 is a gate electrode layer made of polysilicon doped with phosphorus. Also,
The first auxiliary electrode layer 7 is a low resistance electrode layer made of tungsten silicide. On these electrode layers 6 and 7, a second electrode layer 9 and a second auxiliary electrode layer 10 to be a bit line are laminated via a first interlayer insulating layer 8. These electrode layers 9 and 10 are made of the same material as the electrode layers 6 and 7, respectively. In this embodiment, a bottom gate type thin film transistor is formed on a bulk transistor of a stack type SRAM (static RAM) having such a structure. Therefore, the second interlayer insulating layer 11 is laminated on the second auxiliary electrode layer 10. The insulating film forming the first interlayer insulating layer 8 and the second interlayer insulating layer 11 is not particularly limited, but for example, a silicon oxide film, a silicon nitride film, a phosphorus-doped silicon oxide film (PSG film), a boron-doped silicon oxide film (BS
G), arsenic-doped silicon oxide film (AsSG film) and the like. These are, for example, the CVD method or the plasma CV.
The film is formed by the D method.

A gate electrode layer 12 is formed on the second interlayer insulating layer 11 in a predetermined pattern. Gate electrode layer 1
2 is composed of a polysilicon film, and P-type boron is ion-implanted. After that, a gate oxide film 13 is formed on the gate electrode layer 12 and the interlayer insulating layer 11 by, for example, the LPCVD method. The gate oxide film 13 has a thickness of 300 to
It is a silicon oxide film having a thickness of several hundred angstroms. Next, as shown in FIG. 2, a TFT is formed on the gate oxide film 13.
The protective layer 14a made of the same material as the active layer is formed. If the active layer is amorphous silicon, the protective layer will also be amorphous silicon. Next, FIG.
As shown in FIG. 4, by masking the portion other than the specific portion A where the contact hole is to be formed with the photoresist 16 and etching, as shown in FIG. Hall 15
To open. Then, the photoresist 16 is removed.

Next, as shown in FIG. 5, the natural oxide film on the surface of the gate electrode layer 12 exposed by the contact hole 15 is etched and removed by dilute hydrofluoric acid treatment. Here, since the entire surface of the gate oxide film 13 is covered with the protective layer 14a, the gate oxide film 13 is protected from erosion by dilute hydrofluoric acid. In particular, when the protective layer 14a is amorphous silicon, this material is preferable because it is unlikely to be corroded by dilute hydrofluoric acid. After that, as shown in FIG. 6, amorphous silicon for forming the active layer of the TFT is deposited on the entire surface of the protective layer 14a and the contact hole 15, and the active layer 1 having a prescribed thickness is formed.
4 is formed. As a result, the active layer 14 and the gate electrode layer 12 are electrically connected to each other at the contact hole 15. Finally, crystallize the active layer 14,
By implanting P-type boron ions into the source and drain regions and patterning into a predetermined shape, T
FT is completed.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-mentioned embodiment, the contact with the gate electrode layer 12 is shown, but the second auxiliary electrode layer 1
The method of the present invention can be applied to the case of making contact with 0 or the first auxiliary electrode layer 7. Further, the electrode layers 6, 7, 9, 12 are not limited to the polysilicon film, and in short, when the contact hole 15 is opened,
An electrode layer made of any material may be used as long as it is a conductive film whose natural oxide film on the surface needs to be removed with dilute hydrofluoric acid or the like. Further, the material forming the active layer 14 is not limited to amorphous silicon, and other materials such as single crystal silicon may be used.

[0012]

As described above, according to the present invention,
A natural oxide film on the surface of the lower gate electrode layer exposed by the contact hole after forming a protective layer by depositing a layer of a material that constitutes the active layer on the gate oxide film Is removed by dilute hydrofluoric acid treatment or the like, the gate oxide film can be effectively protected from erosion by the protective layer, and thus a stable gate oxide film can be maintained. Moreover, since the protective film is similar to the material forming the active layer, it is not necessary to remove the protective film, and a natural oxide film is formed on the surface of the electrode layer during the process of removing the protective film. Nor. Further, unlike the conventional case, it is not necessary to form a thick gate oxide film in consideration of the amount of corrosion, and there is no possibility that the dielectric breakdown voltage of the gate oxide film is locally deteriorated by the corrosion. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a first step of an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a second step of the embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the resist process of the third step of the embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the etching process of the third step of the embodiment of the present invention.

FIG. 5 is a sectional view for explaining a fourth step of the embodiment of the present invention.

FIG. 6 is a sectional view for explaining a fifth step of the embodiment of the present invention.

[Description of Reference Signs] 12 ... Gate Electrode Layer 13 ... Gate Oxide Film 14 ... Active Layer 14a ... Protective Layer 15 ... Contact Hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/40 A 7738-4M

Claims (1)

Claim: What is claimed is: 1. A first step of forming a gate oxide film on a gate electrode layer, and a protective layer by depositing a layer of a material forming an active layer on the gate oxide film. A second step of forming a contact hole, a third step of opening a contact hole at a specific portion of the protective layer and the gate oxide film, and exposing a surface of a gate electrode layer or another electrode layer located thereunder, A fourth step of etching and removing a natural oxide film on the surface of the electrode layer exposed by the contact hole; and covering the entire surface of the protective layer and the contact hole,
A fifth step of depositing a layer of a material that constitutes an active layer, and forming an active layer connected to the gate electrode layer in the contact hole.