JPH0536736A - Hybrid integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Improves heat dissipation of a large output circuit of a large output hybrid integrated circuit in which a large output circuit and a small output circuit are formed and solders chip parts forming the small output circuit. This prevents cracks from occurring in the solder joint due to the temperature cycle at the joint, and improves the heat dissipation of the chip component. [Structure] A first insulating resin layer (2) having a low thermal resistance and a second insulating resin layer (5) having ductility having holes (7B) at predetermined positions are provided on one main surface of a substrate (1). The power semiconductor element (6) is mounted on the first insulating resin layer (2), and the chip component (4) is arranged on the substrate (1) with the adhesive layer (12) arranged in the hole (7B) region. It is mounted on the second insulating resin layer (5) so as to be fixed to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to improvement of a hybrid integrated circuit having a power device.

[0002]

2. Description of the Related Art A conventional hybrid integrated circuit is shown in FIG. The hybrid integrated circuit substrate (21) is an aluminum substrate whose surface is anodized, and a conductive path (22) having a desired shape is formed on the substrate (21) via an insulating resin layer. Circuit elements (23) such as semiconductor chips, chip capacitors and printed resistors are mounted on or between the conductive paths (22) and are interconnected via the conductive paths (22). Although not shown, the conductive path (22) is formed via an insulating adhesive layer such as an epoxy resin adhered to the substrate (21).

The hybrid integrated circuits described above are commonly used for low power applications. This is because a circuit is formed on the substrate (21) via an insulating resin layer (not shown), so that the thermal resistance increases. Therefore, various hybrid integrated circuits have been proposed in which a filler such as alumina, silica, or boron is contained in the insulating resin layer of the hybrid integrated circuit structure to reduce the thermal resistance. Therefore, in the case of a hybrid integrated circuit having a large output circuit or a large output circuit and a small signal circuit around the large output circuit, those circuits are generally formed on a substrate having a resin layer containing a filler giving priority to thermal resistance. To be done.

[0004]

SUMMARY OF THE INVENTION A hybrid integrated circuit as described above.
Chips such as chip resistors and chip capacitors mounted on top
Since the plug-in parts are generally connected on the conductive path with solder,
The following problems occur. That is, an aluminum substrate is
The thermal expansion coefficient α of the substrate used as the base substrate is 23 × 10 ^-6/ ° C
And the thermal expansion of the above-mentioned chip component, such as a chip resistor.
Expansion coefficient α is 7 × 10^-6/ ° C, thermal expansion of chip capacitors
Expansion coefficient α is 10 × 10^-6/ ° C, so both expansion coefficients
Due to the significant difference in α
The temperature of the soldered part that connects the
Stress is applied and cracks occur in the soldered part.
There is a problem of poor connection.

Next, the mechanism by which cracks occur
Explain. As described above, the expansion coefficient of the aluminum substrate
The number α is 23 × 10^-6/ ° C, expansion coefficient α of chip parts is 7
~ 10 x 10^-6/ ° C, solder for joining chip components
Expansion coefficient α is about 23 × 10 ^-6/ ° C, so room temperature
In the state, as shown in A of FIG. 6, stress is applied to the substrate, the solder, and the chip part.
Do not join. However, in the high temperature state, as shown in FIG.
Since α of the plate and solder is larger than the chip component, pull in the direction of the arrow.
As a result, the joint solder is only laid in the direction of the arrow.
It transforms to spread. In the low temperature state, it is shown in Fig. 6C.
As a result, compressive force is applied in the opposite arrow direction, and as a result,
The hem of the bonding solder spreads only in the direction of the arrow. For example, -5
Dozens under severe temperature cycle conditions of 0 to + 150 ° C
~ By repeating several hundred cycles, as described above, α
Cracks on the joint surface of chip parts and solder
Occur. The reason is that a temperature cycle produces a microcrystalline state.
Tin and lead components of a certain solder component are separated and aggregated in the solder
Does it reduce mechanical strength to form a continuous lead layer?
It is.

The above-mentioned problems are peculiar to integrated circuits based on metal substrates, particularly aluminum substrates, and do not occur on integrated circuits based on other substrates such as printed boards. This is because such a base substrate does not cause the above-mentioned problems due to the difference between the expansion coefficient α of the chip component or the printed resistor and the expansion coefficient α of the substrate.

[0007]

The present invention has been made in view of the above-mentioned problems, and a low thermal resistance resin layer and an insulating resin layer having ductility are present on the same main surface of a metal substrate,
In a hybrid integrated circuit in which a conductive path having a desired shape is formed on both the resin layers, a power semiconductor element is fixedly mounted on the low thermal resistance resin layer, and a circuit element such as a chip resistor is fixedly mounted on the insulating resin layer, The circuit element is characterized in that it is mounted on a substrate through a hole provided in the insulating resin layer and an adhesive resin layer containing a filler arranged in the hole.

Further, a polyimide resin is used as the insulating resin layer having the ductility characteristic.

[0009]

In the hybrid integrated circuit configured as described above, the power semiconductor element is mounted on the low thermal resistance resin layer,
Other circuit elements such as chip resistors, chip capacitors, and other chip parts are mounted on an insulating resin layer that has ductility characteristics. Even if a cycle occurs, in the case of chip resistors, chip capacitors, and other chip component-shaped circuit elements mounted on an insulating resin layer that has ductility, the stress on the solder joints of chip components caused by temperature cycling is ductile. This can be alleviated by the insulating resin layer having characteristics, and the heat dissipation of the chip component can be improved because the chip component is temporarily adhered to the substrate via the adhesive resin layer containing the filler.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A hybrid integrated circuit of the present invention will be described below based on the embodiment shown in FIG. FIG. 1 is an enlarged sectional view of an essential part showing a hybrid integrated circuit of the present invention. (1) is a metal substrate,
(2) is a first insulating resin layer, (3) is a conductive path, (4) is a chip component such as a chip resistor or a chip capacitor, (1)
Reference numeral 2) is a temporary adhesive layer for temporarily bonding the chip component, (5) is a second insulating resin layer, and (6) is a power semiconductor element.

As the metal substrate (1), for example, an aluminum substrate or an aluminum substrate whose surface is anodized is used, and the latter aluminum substrate is used here. A conductive path having a desired shape is formed on one main surface of the substrate (1) via an insulating resin layer, and various circuit elements are fixedly mounted on the conductive path. In the present invention, two kinds of insulating resin layers (2) and (5) made of different materials are present on the substrate (1). That is, the first insulating resin layer (2) on which the power semiconductor element (6) such as a power transistor is mounted and the second insulating resin layer (on which the circuit element (4) other than the power semiconductor element (6) is mounted ( 5).

As the first insulating resin layer (2), a low thermal resistance type insulating resin layer is used in order to improve heat dissipation of the power semiconductor element (6). The first insulating resin layer (2) is formed of a resin such as an epoxy resin, a phenol resin, or a xylene resin in a predetermined weight ratio, for example, 30 to 80.
% Of BeO, MgO, Al ₂ O _{3 and} other oxide ceramics, AIN, BN and other nitride ceramics fillers of a predetermined particle size are mixed, and the thermal resistance of the first insulating resin layer (2) is increased. Is set low.

On the other hand, the second insulating resin layer (5) is stressed due to the difference in the coefficient of thermal expansion α of the circuit element (4) mounted on the substrate (1) and the second insulating resin layer (5) during the heat cycle. An insulating resin layer having a ductile characteristic capable of absorbing and relaxing is used. A polyimide resin such as Kapton (trade name) is used as the second insulating resin layer (5). The ductility of such a polyimide resin is about 80 to 85%, and is capable of sufficiently absorbing and relaxing stress due to heat cycle.

By the way, the first insulating resin layer (2) on which the power semiconductor element (6) is mounted is attached to the entire surface of the substrate (1). At this time, a copper foil is previously integrated in the fixing region of the power semiconductor element (6) of the first insulating resin layer (2). Then, the copper foil is etched to form a fixing pad (3) to which the power semiconductor element (6) is fixed and a power conductive path (not shown) extending from the fixing pad (3).

The above-mentioned second insulating resin layer (5) is adhered on the first insulating resin layer (2) other than the fixing region of the power semiconductor element (6) via the adhesive layer (6A). . A copper foil is previously integrated on the second insulating resin layer (5) via an adhesive layer (6B), and has a hole (7A) surrounding the fixing region of the power semiconductor element (6). A hole (7B) is provided for temporarily adhering the chip component (4). The fixing pad (3) previously formed by this hole (7)
Also, a part of the power conductive path and the first insulating resin layer (2) is exposed. After sticking the second insulating resin layer (5) on the first insulating resin layer (2), the copper foil on the second insulating resin layer (5) is etched to form a conductive path (3) having a desired shape. ) Is formed. At this time, no adverse effect occurs because the protective resist ink is applied to the exposed portion of the first insulating resin layer (2), that is, the power semiconductor fixing pad (3) and the power conductive path. do not do.

A first insulating resin layer (2) and a second insulating resin layer (5) are adhered to a substrate (1), and a predetermined conductive path (on the respective resin layers (2) and (5)). 3) After forming (3), predetermined circuit elements are mounted on the conductive paths (3) and (3). That is, the power semiconductor element (6) is mounted and connected to the fixing pad (3) on the first insulating resin layer (2) via a heat sink (8) such as a copper piece fixed by a brazing material. On the other hand, in the conductive path (3) on the second insulating resin layer (5), chip parts (4) such as a chip resistor and a chip capacitor, and other small signal type semiconductor elements (not shown) may be solder or the like. It is fixedly mounted by the material.

By the way, according to the present invention, when the chip components (4) of the chip capacitor and the chip resistor are connected on the conductive path (3), the chip components (4) are mounted as described above. The chip component (4) and the first insulating resin layer (2) exposed by the holes (7B) of the second insulating resin layer (5) in the region are fixed. That is, the first insulating resin having a low thermal resistance by the temporary adhesive (12) for temporarily adhering the chip component (4) on the substrate (1) before soldering the connection electrode of the chip component (4) and the conductive path. The layer (2) and the chip component (4) are temporarily bonded. The temporary adhesive (12) not only temporarily bonds the chip component (4),
In order to effectively dissipate the heat generated by the chip component (4), a filler having a desired weight ratio is mixed in an adhesive such as acrylic resin or silicon resin. According to this structure, the chip component (4) can be temporarily adhered to the substrate (1), and even if the chip component (4) generates heat, the heat can be effectively released to the outside.

The power semiconductor element (6) is connected by a wire line (9) to the conductive path (3) extended at the peripheral end of the hole (7) of the second insulating resin layer (5), The power semiconductor element (6) and the other circuit element (4) are electrically connected to each other. At this time, Ni plating (10) treatment is applied to the conductive path (3) to facilitate wire bonding.

According to the structure of the present invention, the first insulating resin layer (2) of the low thermal resistance resin layer is formed on the substrate (1) as described above.
And the second insulating resin layer (5) having ductility, the heat quantity of the heat-generating power semiconductor element can be sufficiently dissipated and a severe temperature cycle, for example, -50.
Chip resistance due to the difference of α even in the range of + 150 ° C,
Since the stress generated in the solder joint portion of the chip component (4) such as the chip capacitor is absorbed by the second insulating resin layer (5), it is possible to remarkably suppress the crack generation in the solder joint portion as in the conventional case.

Now, it will be explained with reference to FIG. 2 why the use of the structure of the present invention makes cracks less likely to occur at the solder joints of the chip component (4) such as a chip capacitor and a chip resistor. When the substrate (1) to which the chip parts (4) are fixed is left at a high temperature of about 150 ° C, α of the substrate (1) becomes 2
Since it is as large as 3 × 10 ⁻⁶ / ° C., a large stress indicated by an arrow is generated on the substrate (1). Then, since the first insulating resin layer (2) also has a predetermined content of the filler mixed therein, α becomes as large as about 23 × 10 ⁻⁶ / ° C., and thus a large stress is generated as in the case of the substrate (1). Since the stress generated in the first insulating resin layer (2) is as thin as several tens of μ, the stress of the substrate (1) is substantially transmitted to the first insulating resin layer (2) as it is. . However, since the chip component (4) is mounted on the second insulating resin layer (5) having ductility, a large stress generated in the substrate (1) is generated in the second insulating resin layer (5). Absorption is relaxed as indicated by the arrow in the thickness direction, and the large stress generated in the substrate (1) is not applied to the solder joint portion (11). At this time, if the film thickness of the second insulating resin layer (5) is about 10 μm or less, the stress generated in the substrate (1) cannot be effectively relieved. When the film thickness is set to about 10 μm or more, the stress generated in the substrate (1) can be relaxed sufficiently. As described above, the stress generated in the substrate (1) is relaxed in the second insulating resin layer (5), so that the microcrystalline state of the solder component of the solder joint portion (11) is maintained and the solder joint is performed. No crack is generated at the interface between the part and the chip component (4) such as the capacitor.

On the other hand, FIG. 3 shows the defective crack generation rate at the solder joint in the temperature cycle test when the chip capacitor (4) is mounted on the structure (A) of the present invention and the conventional structure (B). FIG. The temperature cycle condition was −40 ° C. (30 minutes) to + 125 ° C. (30 minutes), and a 3.2 × 1.6 mm chip capacitor was mounted on an aluminum substrate. As is clear from the figure, the conventional (B)
In 670 cycles, a defect started to occur, and in 1000 cycles, a connection defect due to a solder crack occurred in all of the 8 test samples. On the other hand, in (A) of the present invention, it was confirmed that no cracks were generated at the solder joint even after 1500 cycles.

FIG. 4 is a sectional view showing another embodiment, in which the first insulating resin layer (2) and the second insulating resin layer having substantially the same film thickness are formed on the same layer on the same main surface of the substrate (1). (5) and are formed. According to this structure, the second insulating resin layer (5)
When the hole (7B) is provided in the substrate (1), the alumite layer of the substrate (1) is exposed to improve the heat radiation function, but the above-mentioned embodiment is preferable in consideration of the breakdown voltage.

[0023]

As described in detail above, according to the present invention,
Even in a temperature cycle under severe conditions, it is possible to almost completely prevent the occurrence of cracks at the solder joints of chip components such as chip capacitors and chip resistors. As a result, it is possible to realize a highly reliable hybrid integrated circuit for high output which is excellent in heat dissipation of the power semiconductor element and which is suitable for extremely severe temperature cycle conditions.

Further, according to the present invention, the chip component mounted on the first insulating resin layer having the ductility characteristic has the thermal conductivity arranged in the hole region provided in the first insulating resin layer. By being fixed to the substrate via the excellent adhesive, even if the chip component generates heat, the heat can be efficiently released.

[Brief description of drawings]

FIG. 1 is an enlarged sectional view of an essential part showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating stress in a solder joint portion according to an embodiment of the present invention.

FIG. 3 is a characteristic diagram showing a crack generation defect rate of a solder joint portion in a temperature cycle test.

FIG. 4 is an enlarged cross-sectional view of a main part showing another embodiment.

FIG. 5 is a cross-sectional view showing a conventional hybrid integrated circuit.

FIG. 6 is a diagram illustrating stress in a conventional solder joint.

[Explanation of symbols]

(1) Metal substrate (2) First insulating resin layer (3) Conductive path (4) Chip parts (5) Second insulating resin layer (6) Power semiconductor element (12) Temporary adhesive layer

Claims (2)

[Claims] 1. A low thermal resistance resin layer and an insulating resin layer having ductility are present on the same main surface of a metal substrate, and a conductive path having a desired shape is formed on both of the resin layers, and the low thermal resistance resin layer is formed on the low thermal resistance resin layer. In a hybrid integrated circuit in which a power semiconductor element is fixedly mounted and a circuit element such as a chip resistor is fixedly mounted on the insulating resin layer, the circuit element straddles a hole provided in the insulating resin layer and is arranged in the hole. A hybrid integrated circuit characterized by being mounted and fixed on a substrate through an adhesive resin layer containing a filler. 2. The hybrid integrated circuit according to claim 1, wherein a polyimide resin is used as the insulating resin layer having the ductility characteristic.