JPH0537251Y2 - - Google Patents
Info
- Publication number
- JPH0537251Y2 JPH0537251Y2 JP12526687U JP12526687U JPH0537251Y2 JP H0537251 Y2 JPH0537251 Y2 JP H0537251Y2 JP 12526687 U JP12526687 U JP 12526687U JP 12526687 U JP12526687 U JP 12526687U JP H0537251 Y2 JPH0537251 Y2 JP H0537251Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- resistor
- mosfet
- connection point
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Electronic Switches (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案は、MOSトランジスタで構成された
LSIに内蔵される電圧検出回路に関し、特に、印
加される電源電圧を検出する回路に関する。[Detailed explanation of the invention] (a) Industrial application field This invention consists of MOS transistors.
The present invention relates to a voltage detection circuit built into an LSI, and particularly to a circuit that detects an applied power supply voltage.
(ロ) 従来の技術
一般に、マイクロコンピユータやその他の
MOSトランジスタを用いたLSIに於いて、その
電源電圧を検出する必要性が生じる。代表的なも
のに、電源投入時にその電源が所定値に達するま
で内部回路の動作を禁止し、初期状態にする、い
わゆる初期設定回路がある。(b) Conventional technology In general, microcomputers and other
In LSIs using MOS transistors, there is a need to detect the power supply voltage. A typical example is a so-called initial setting circuit that inhibits the operation of internal circuits until the power reaches a predetermined value when the power is turned on, and sets the circuit to an initial state.
従来、電圧検出回路は、第３図に示す如く、入
力電圧VINを抵抗R1とR2で分割し、抵抗R3とツエ
ナーダイオード１で作成される基準電圧Vrefと
分割された電圧をコンパレータ２で比較してい
る。 Conventionally, a voltage detection circuit divides the input voltage V IN by resistors R 1 and R 2 as shown in Fig. 3, and connects the divided voltage to a reference voltage Vref created by resistor R 3 and Zener diode 1 to a comparator. 2 is compared.
また、初期設定回路として用いられるような電
圧検出回路は、第４図に示す如く、電源VDDと接
地間にMOSトランジスタ３とコンデンサ４を直
列接続し、その接続点の電圧をインバータ５の入
力に印加して構成され、コンデンサ４の端子電圧
がインバータ５のスレツシヨルド電圧に達するま
で初期設定パルスが持続するようになつている。 In addition, a voltage detection circuit used as an initial setting circuit has a MOS transistor 3 and a capacitor 4 connected in series between the power supply V DD and the ground, and the voltage at the connection point is applied to the input of the inverter 5, as shown in FIG. The initial setting pulse continues until the terminal voltage of the capacitor 4 reaches the threshold voltage of the inverter 5.
特に、第４図に示されたような回路は、実公昭
57−21065号公報に記載されている。 In particular, the circuit shown in Figure 4 was
It is described in Publication No. 57-21065.
(ハ) 考案が解決しようとする問題点
しかしながら、第３図に示された回路をLSIに
内蔵する場合には、基準電圧Vrefを作成するた
めのツエナーダイオードは、MOSトランジスタ
を形成する標準プロセスでは作れず、ツエナーダ
イオードのための特殊なプロセスが必要となる。(c) Problems to be solved by the invention However, when the circuit shown in Figure 3 is built into an LSI, the Zener diode for creating the reference voltage Vref cannot be formed using the standard process for forming MOS transistors. A special process for Zener diodes is required.
また、第４図に示された回路は、容易にLSIに
内蔵できるが、コンデンサが占有するチツプ上の
面積が大きくなる欠点があつた。 Furthermore, although the circuit shown in FIG. 4 can be easily built into an LSI, it has the disadvantage that the area occupied by the capacitor on the chip becomes large.
(ニ) 問題点を解決するための手段
本考案は、上述した点に鑑みて創作されたもの
であり、入力電圧が印加される端子と接地電位間
に直列接続された第１の抵抗、第１の
MOSFET、及び、１以上の第２のMOSFETと、
前記端子と接地電位間に直列接続された第２の抵
抗、第３の抵抗、及び、第３のMOSFETを備
え、第２の抵抗と第３の抵抗の接続点が第１の
MOSFETのゲートに接続され、第１の抵抗と第
１のMOSFETの接続点が第３のMOSFETのゲ
ートに接続されることにより、入力電圧が所定値
になつたことを検出するものである。(d) Means for solving the problems The present invention was created in view of the above points, and includes a first resistor, a first resistor, and a second resistor connected in series between the terminal to which input voltage is applied and the ground potential. 1 of
a MOSFET and one or more second MOSFETs;
A second resistor, a third resistor, and a third MOSFET are connected in series between the terminal and the ground potential, and the connection point of the second resistor and the third resistor is connected to the first resistor.
It is connected to the gate of the MOSFET, and the connection point between the first resistor and the first MOSFET is connected to the gate of the third MOSFET, thereby detecting that the input voltage has reached a predetermined value.
(ホ) 作用
上述の手段によると、入力電圧が第３の
MOSFETのスレツシヨルド電圧VtNになると第
３のMOSFETがオンして第２の抵抗と第３の抵
抗に電流が流れて、その接続点に分割された電圧
が生じる。この分割された電圧が第１及び第
2MOSFETのスレツシヨルド電圧の和、即ち、
2VtNになると第１のMOSFETがオンして、第３
のMOSFETのゲート電圧を引き下げるため、第
３のMOSFETがオフする。この第３の
MOSFETのオフによつて変化するドレン電圧を
出力として取り出すことにより、検出が為される
のである。(E) Effect According to the above-mentioned means, the input voltage is
When the threshold voltage VtN of the MOSFET is reached, the third MOSFET is turned on, current flows through the second resistor and the third resistor, and a divided voltage is generated at the connection point. This divided voltage is applied to the first and
The sum of the threshold voltages of 2 MOSFETs, i.e.
When the voltage reaches 2Vt N , the first MOSFET turns on and the third MOSFET turns on.
The third MOSFET is turned off to lower the gate voltage of the second MOSFET. This third
Detection is performed by outputting the drain voltage that changes when the MOSFET is turned off.
(ヘ) 実施例
第１図は、本考案の実施例を示す回路図であ
る。入力端子６には検出すべき電圧VINが印加さ
れ、入力端子６と接地間には、第１の抵抗７と、
第１のMOSFET８及び第２のMOSFET９が直
列接続されると共に、第２の抵抗１０と、第３の
抵抗１１と第３のMOSFET１２が直列接続され
る。これら、第１、第２及び第３のMOSFET
８，９，１２はすべてＮチヤンネル型で形成され
る。第１のMOSFET８のゲートは第２の抵抗１
０と第３の抵抗１１の接続点に接続され、第１の
MOSFET８のサブストレートは、そのソースに
接続される。また、第２のMOSFET９のゲート
は、そのドレインに接続され、サブスレートはソ
ースに接続される。更に、第３のMOSFET１２
のゲートは、第１の抵抗７と第１のMOSFET８
の接続点に接続され、サブストレートはソースに
接続される。検出出力は、第３の抵抗１１と第３
のMOSFET１２の接続点から取り出され、図示
はしないがインバータ等の入力に導びかれる。こ
こで、第１、第２及び第３の抵抗７，１０，１１
の抵抗値は、第１、第２及び第３のMOSFET
８，９，１２のオン抵抗より十分大きな値に設計
されている。(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. A voltage V IN to be detected is applied to the input terminal 6, and a first resistor 7 is connected between the input terminal 6 and the ground.
The first MOSFET 8 and the second MOSFET 9 are connected in series, and the second resistor 10, the third resistor 11, and the third MOSFET 12 are connected in series. These first, second and third MOSFETs
8, 9, and 12 are all formed of N-channel type. The gate of the first MOSFET 8 is connected to the second resistor 1
0 and the third resistor 11, and the first
The substrate of MOSFET 8 is connected to its source. Further, the gate of the second MOSFET 9 is connected to its drain, and the substrate is connected to its source. Furthermore, the third MOSFET12
The gate of the first resistor 7 and the first MOSFET 8
and the substrate is connected to the source. The detection output is generated by the third resistor 11 and the third resistor 11.
It is taken out from the connection point of the MOSFET 12, and is led to the input of an inverter, etc. (not shown). Here, the first, second and third resistors 7, 10, 11
The resistance values of the first, second and third MOSFETs are
It is designed to have a value sufficiently larger than the on-resistance of 8, 9, and 12.
第２図は、第１図に示された回路の動作を示す
波形図である。第２図に於いて、VINは入力電
圧、Vaは第２と第３の抵抗１０，１１の接続点
の電圧、Vbは、第１の抵抗７と第１のMOSFET
８の接続点の電圧、VOUTは、第３の抵抗１１と
第３のMOSFET１２の接続点の電圧である。ま
た、VtNは、第１、第２、第３のMOSFET８，
９，１２の各々のスレツシヨルド電圧であり、同
一プロセスで形成されるためすべて等しくなつて
いる。 FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1. In Fig. 2, V IN is the input voltage, Va is the voltage at the connection point of the second and third resistors 10 and 11, and Vb is the voltage at the connection point between the first resistor 7 and the first MOSFET.
The voltage at the connection point of No. 8, V OUT , is the voltage at the connection point of the third resistor 11 and the third MOSFET 12. In addition, Vt N is the first, second, third MOSFET8,
9 and 12, and because they are formed by the same process, they are all equal.
第１図及び第２図に於いて、入力電圧VINがゼ
ロから立ち上がる場合、電圧Va及びVbは入力電
圧VINと同じに立ち上がる。電圧Vbがスレツシヨ
ルド電圧VtNになると、第３のMOSFET１２が
オンするため、電圧Vaは、第２の抵抗１０と第
３の抵抗１１で入力電圧VINを分割した電圧とな
り、電圧VOUTは、接地電位に引き下げられる。
更に、入力電圧VINが上昇して、電圧Vaが2VtN
になると、第１のMOSFET８がオンして、電圧
Vbは第１のMOSFET８及び第２のMOSFET９
により、略VtNに引き下げられ、これにより、第
３のMOSFET１２はオフし、電圧Va及びVOUTは
入力電圧VINに引き上げられる。この電圧VOUTが
入力電圧VINに引き上げられることにより、入力
電圧VINが所定電圧になつたことが検出される。
このときの入力電圧VINは、
（R2＋R3）／R3×2VtN
となる。ここで、R2は第２の抵抗１０の値、R3
は第３の抵抗１１の値である。 In FIGS. 1 and 2, when the input voltage V IN rises from zero, the voltages Va and Vb rise to the same level as the input voltage V IN . When the voltage Vb reaches the threshold voltage Vt N , the third MOSFET 12 turns on, so the voltage Va becomes the voltage obtained by dividing the input voltage V IN by the second resistor 10 and the third resistor 11, and the voltage V OUT becomes Pulled down to ground potential.
Furthermore, the input voltage V IN increases and the voltage Va decreases to 2Vt N
, the first MOSFET8 turns on and the voltage
Vb is the first MOSFET8 and second MOSFET9
As a result, the third MOSFET 12 is turned off , and the voltages Va and V OUT are pulled up to the input voltage V IN . By raising this voltage V OUT to the input voltage V IN , it is detected that the input voltage V IN has reached a predetermined voltage.
The input voltage V IN at this time is (R 2 + R 3 )/R 3 ×2Vt N. Here, R 2 is the value of the second resistor 10, R 3
is the value of the third resistor 11.
次に、入力電圧VINが立ち下がる場合には、入
力電圧VINと電圧Vaが同じに立ち下がるため、入
力電圧VINが2VtNになつたとき第１のMOSFET
８がオンとなり、電圧Vbが接地電位に引き下げ
られる。更に、第３のMOSFET１２がオンする
ため、電圧Vaは第２及び第３の抵抗１０，１１
の分割電圧になり、電圧VOUTは接地電位になる。 Next, when the input voltage V IN falls, the input voltage V IN and the voltage Va fall at the same level, so when the input voltage V IN reaches 2Vt N , the first MOSFET
8 is turned on, and voltage Vb is lowered to ground potential. Furthermore, since the third MOSFET 12 is turned on, the voltage Va increases across the second and third resistors 10 and 11.
, and the voltage V OUT becomes the ground potential.
このように、第１図の回路では、入力電圧VIN
の立ち上がり時の検出電圧は、第２及び第３の抵
抗１０，１１、スレツシヨルド電圧VIN、及び、
第２のMOSFET９の接続段数によつて決定され
るのであり、更に、入力電圧VINの立ち下がり時
の検出電圧はスレツシヨルド電圧VtNと第２の
MOSFET９の接続段数によつて決定される。こ
れにより、ヒステリシス特性も持つのである。 In this way, in the circuit of Figure 1, the input voltage V IN
The detection voltage at the rise of the second and third resistors 10 and 11, the threshold voltage V IN , and
It is determined by the number of connected stages of the second MOSFET 9, and furthermore, the detection voltage when the input voltage V IN falls is determined by the threshold voltage Vt N and the second MOSFET 9.
It is determined by the number of connected MOSFETs 9. As a result, it also has hysteresis characteristics.
(ト) 考案の効果
上述の如く本考案によれば、通常のプロセスで
形成されるMOSFETと抵抗のみで、電圧検出回
路を最小の素子数で形成できるので、特殊なプロ
セスが不要でチツプ上の面積の増加も最小ですむ
利点を有し、初期設定回路としてLSIに使用して
有効なものである。(g) Effects of the invention As mentioned above, according to the invention, a voltage detection circuit can be formed with the minimum number of elements using only MOSFETs and resistors formed in normal processes, so there is no need for special processes and It has the advantage of minimizing the increase in area, making it effective for use in LSI as an initial setting circuit.
第１図は本考案の実施例を示す回路図、第２図
は第１図に示された回路の動作を示す波形図、第
３図及び第４図は従来例を示す回路図である。
６……入力端子、７……第１の抵抗、１０……
第２の抵抗、１１……第３の抵抗、８……第１の
MOSFET、９……第２のMOSFET、１２……
第３のMOSFET。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1, and FIGS. 3 and 4 are circuit diagrams showing a conventional example. 6...Input terminal, 7...First resistor, 10...
second resistor, 11... third resistor, 8... first resistor
MOSFET, 9...Second MOSFET, 12...
Third MOSFET.
Claims (1)
に直列接続された第１の抵抗、第１の
MOSFET、及び、１以上の第２のMOSFETと、
前記端子と接地電位間に直列接続された第２の抵
抗、第３の抵抗及び第３のMOSFETとを備え、
前記第２の抵抗と第３の抵抗の接続点が前記第１
のMOSFETのゲートに接続され、前記第１の抵
抗と第１のMOSFETの接続点が前記第３の
MOSFETのゲートに接続されたことを特徴とす
る電圧検出回路。 a first resistor connected in series between the terminal to which the voltage to be detected is applied and the ground potential;
a MOSFET and one or more second MOSFETs;
comprising a second resistor, a third resistor, and a third MOSFET connected in series between the terminal and ground potential,
The connection point between the second resistor and the third resistor is the first resistor.
The connection point between the first resistor and the first MOSFET is connected to the gate of the third MOSFET.
A voltage detection circuit characterized in that it is connected to the gate of a MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12526687U JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12526687U JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6433669U JPS6433669U (en) | 1989-03-02 |
| JPH0537251Y2 true JPH0537251Y2 (en) | 1993-09-21 |
Family
ID=31375720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12526687U Expired - Lifetime JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537251Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2510779B2 (en) * | 1990-10-30 | 1996-06-26 | 東レ株式会社 | Heat-fusible heat-insulating fiber mat and method for producing the same |
-
1987
- 1987-08-18 JP JP12526687U patent/JPH0537251Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6433669U (en) | 1989-03-02 |
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