JPH0537323A - Switching circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The ON time is increased when the load current is small, and the ON time is shortened as the load current increases. [Configuration] Switch terminals 11 and 12 to be controlled on / off
A main FET 13 and a resistor 14 for current detection connected in series between the drain and the gate of the main FET are respectively connected to the drain and the gate, and the source is connected to the first end of the resistor on the side opposite to the main FET. A discharging sub-FET 16 connected via the switching element 15, a discharging resistor 21 connected in parallel to the sub-FET, a driving power supply 18 connected to the gate of the main FET via the second switching element,
First switching element and second switching element 1
A switch circuit is configured from an input terminal 20 for turning on the first switching element and turning on the second switching element by inputting an external signal to 7 as a trigger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit, and more particularly to a switch circuit for a circuit in which the load changes greatly.

[0002]

2. Description of the Related Art Conventionally, a switch circuit is generally constructed so that it is made conductive only during a certain time when an input signal is applied, and is used in a pulse width modulation circuit as shown in FIG. 5, for example. That is, the pulse width modulation circuit 1
The input terminals 2a and 2b to which the power source 2 should be connected, and the load 3
And the output terminals 3a and 3b to which the
a capacitor 4 connected between a and 3b, a coil 6 having one end connected to a + side input terminal 2a through a switch circuit 5 and the other side connected to a + side output terminal 3a, and this coil 6 1 and a diode 7 connected to the-side output terminal 3b, and the-side output terminal 3b is connected to the-side input terminal 2b.

The pulse width modulation circuit 1 configured as described above
According to the above, the voltage from the power supply 2 is applied to the load 3 at the output voltage Vo via the switch circuit 5 and the coil 6, and the switch circuit 5 is turned on for a certain period of time. The load current Ids flows through the load 3 as indicated by the arrow.

[0004]

However, in this case, the relationship between the output voltage Vo and the load current Ids is that the output voltage Vo rapidly increases as the load current Ids decreases, as shown by the solid line in FIG. Since the difference between the output voltage Vo under no load and the output voltage Vo under load is not linear (shown by the dotted line), it is difficult to perform appropriate control by monitoring the output voltage Vo. there were.

In view of the above points, it is an object of the present invention to provide a switch circuit in which the ON time is long when the load current is small and the ON time is short as the load current increases. ..

[0006]

In order to achieve the above object, the switch circuit of the present invention comprises a main FET and a current detecting resistor connected in series between switch terminals to be ON / OFF controlled, and the main FET. Drain and gate are connected to the gate and source of the resistor, respectively, and the source is connected to the end of the resistor on the side opposite to the main FET via the first switching element, and a discharge sub-FET in parallel with the sub-FET. A discharge resistor connected to the main FET, a driving power source connected to the gate of the main FET via a second switching element, and an external signal trigger input to the first switching element and the second switching element. And an input terminal for turning off the first switching element and turning on the second switching element.

[0007]

According to the above construction, when the external signal is pulse-input, when the external signal is at the H level with a predetermined pulse width, the main FET is turned on to bring the switch terminals into conduction, and the external signal is returned to the L level. The gate of the main FET
The electric charge accumulated between the sources is discharged through the discharging resistor, and the voltage generated across the current detecting resistor is input to the gate of the sub-FET to partially bring the sub-FET into conduction. The charge accumulated between the gate and the source of the main FET is discharged through the sub FET according to the load current flowing between the switch terminals. For this reason, the on time of the main FET is shortened as the load current increases. Therefore, by incorporating this switch circuit in a pulse width modulation circuit or the like, the difference in the output voltage between no load and load is linear. Therefore, it becomes possible to perform appropriate control by monitoring the output voltage.

[0008]

FIG. 1 shows an embodiment of a switch circuit according to the present invention. In this figure, the switch circuit 10 is
A main FET 13 and a current detection resistor 14 connected in series between the switch terminals 11 and 12 to be turned on and off.
And to the gate of the main FET 13 via the resistor 13a and to the source of the main FET 13 via the resistor 16a.
Via the first switching element, which is the transistor 15 in the figure, to the end of the resistor 14 on the side opposite to the main FET 13, that is, the switch terminal 12 side. A sub-FET 16 for discharging, a drive power source 18 connected to the gate of the main FET 13 via a second switching element, a transistor 17 in the case shown, a base of the first transistor 15 and a second transistor. The input terminal 20 is connected to the base of the sub FET 17 via the resistor 19, and the resistor 21 is connected in parallel between the drain and the source of the sub FET.

The switch circuit 10 according to the present invention is configured as described above, and the input terminal 20 has a symbol P in FIG.
As shown by, when a pulse signal having a pulse width of a certain time Tw is input, the transistor 1 is connected via the resistor 19.
7 is turned on, and the voltage from the power supply 18 is applied to the gate of the main FET 13 via the transistor 17. As a result, the main FET 13 is turned on and the switch terminals 11 and 12 are electrically connected.
At this time, for the input signal P, the conduction state of the main FET 13 and the gate-source voltage Vgs thereof are as shown in FIG.
Is shown in.

When the input signal P becomes zero or less after the time Tw has elapsed, the transistor 17 is turned off and the transistor 15 is turned on. As a result, the main FET 13
The electric charge accumulated between the gate and the source of is gradually discharged through the resistors 13a and 21. When the voltage Vgs becomes equal to or lower than the minimum voltage Vth necessary for maintaining the conduction of the main FET 13 by this discharge,
The main FET 13 is turned off. In this case, the main FET13
Means that the ON state is held for a time longer than the pulse width Tw of the input signal P. The on-time is the load current Id
It is the maximum when s is zero, and as the load current Ids increases, the product of the resistor 14 and the load current Ids, that is, Ve
By equivalently decreasing the output voltage Vgs by the amount of, the on-time is shortened. This shortening of the ON time is determined by the resistance value of the resistor 14.

By the way, a voltage Ve is generated across the resistor 14, and the voltage Ve is applied to the gate of the sub FET 16 through the resistor 16a. The sub-FET 16 is an enhancement type F-FET configured to start conduction from zero gate-source voltage.
Since ET is used, the equivalent impedance between the drain and the source has a characteristic that is inversely proportional to the gate-source voltage, and when the gate-source voltage rises, the equivalent impedance between the drain and source is Will be reduced. Therefore, due to the generation of the voltage Ve, the sub-FET 16 becomes partially conductive, and the discharge can be performed through the sub-FET 16 together with the resistor 21.

Thus, the factors that determine the on-time of the main FET 13 as the load current Ids increases are: Reduction amount due to generation of voltage Ve in the resistor 14. The gate of the main FET 13 when the sub FET 16 is turned on.
This means that the charge between the sources is discharged through the sub FET 16. As a result, as the load current Ids increases, the on-time of the main FET 13 gradually decreases, as shown in FIG. 3, and finally approaches Tw.

FIG. 4 shows another embodiment of the switch circuit according to the present invention. Since an input signal is sent from the control side having different potentials, the power source 18 of FIG. The secondary side of the pulse transformer 22 is connected to, a rectifying diode 23, a smoothing capacitor 24, a driving FET 25, a gate resistor 26, a resistor 27 and a capacitor 28 for absorbing excitation energy of the pulse transformer 22, and surge absorption. For capacitors 2
The configuration is almost the same as that of the embodiment shown in FIG. 1 except that a resistor 9 and a resistor 30 are provided.

[0014]

As described above, according to the present invention, when a pulse of an external signal is input, the main FET is turned on when the external signal is at the H level of a predetermined pulse width, and the switch terminals are electrically connected. When the external signal returns to the L level, the charge accumulated between the gate and the source of the main FET is discharged through the discharging resistor, and the voltage generated across the current detecting resistor is applied to the gate of the sub FET. input.
As a result, the sub-FET is partially made conductive, and the charge accumulated between the gate and the source of the main FET is discharged through the sub-FET according to the load current flowing between the switch terminals. Therefore, the on-time of the main FET can be shortened as the load current increases. Therefore, by incorporating this switch circuit in a pulse width modulation circuit or the like, the difference in the output voltage between no load and load is linear. Therefore, it becomes possible to perform appropriate control by monitoring the output voltage. Thus, according to the present invention, there is provided an extremely excellent switch circuit in which the on-time becomes long when the load current is small and the on-time becomes short as the load current increases.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a switch circuit according to the present invention.

2 is an input signal, FET in the switch circuit of FIG.
3 is a time chart showing the gate voltage and the operating state of FIG.

3 is an FE for current in the switch circuit of FIG.
It is a graph which shows the operation state of T.

FIG. 4 is a circuit diagram showing another embodiment of the switch circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a pulse width modulation circuit including a conventional switch circuit.

6 is a graph showing the relationship between the output voltage and the load current in the pulse width modulation circuit of FIG.

[Explanation of symbols]

 10 Switch Circuit 11 Switch Terminal 12 Switch Terminal 13 Main FET 14 Current Detection Resistor 15 Transistor 16 Sub FET 17 Transistor 18 Power Supply 19 Resistor 20 Input Terminal 21 Discharge Resistor 22 Pulse Transformer 23 Diode 24 Capacitor 25 FET 26 Resistor 27 Resistor 28 Capacitor 29 condenser 30 resistance

Claims (1)

Claim: What is claimed is: 1. A main FET and a current detecting resistor connected in series between switch terminals to be controlled to be turned on and off, and a drain and a gate are connected to a gate and a source of the main FET, respectively. Also, a discharge sub-FET whose source is connected to the end of the resistor on the side opposite to the main FET via a first switching element, a discharge resistor connected in parallel to the sub-FET, and the main FET A drive power source connected to the gate of the second switching element via a second switching element, and an external signal is input to the first switching element and the second switching element as a trigger to turn off the first switching element. And a switch circuit comprising an input terminal for turning on the second switching element.