JPH0537337A - Buffer circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The clocks input to the gate transistors interposed between the power supply side of the inverter and the first power supply and between the ground side of the inverter and the second power supply are stopped. Even if it keeps the function of the inverter. [Structure] First inverter 2 composed of CMOS transistors
, A gate transistor GT _P interposed between the first inverter 2 and the first power source 6, a gate transistor GT _N interposed between the first inverter 2 and the second power source 7, and a gate transistor GT _P. , GT _N can be supplied with the clocks d and e, and when the clocks d and e are stopped, the clock level fixing circuit 17 can be supplied to the gate transistors GT _P and GT _N to input the clock control signal f for turning them on. Equipped with.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit which prevents noise on the input side from propagating to the output side.

[0002]

2. Description of the Related Art FIG. 1 is a circuit diagram of a buffer circuit for which the applicant of the present invention has applied for a patent on June 27, 1991. The first inverter 2 serving as a buffer is composed of a CMOS transistor composed of a P-channel transistor (hereinafter referred to as transistor) PT ₁ and an N-channel transistor (hereinafter referred to as transistor) NT ₁ , and the transistors PT ₁ and NT
Each gate of ₁ is connected to the buffer input terminal 8.

The power supply side of the transistor PT ₁ is connected to the first power supply (V _CC ) 6 via the P-channel gate transistor GT _P, and the ground side of the transistor NT ₁ is connected to the first power supply (V _CC ) 6 via the N-channel gate transistor GT _N. Two power supplies (V _SS ) 7 are connected. The gate of the gate transistor GT _P is connected to the clock input terminal 14 and the gate of the gate transistor GT _N is connected to the clock input terminal 15.

A serial connection portion of the transistors PT ₁ and NT ₁ is connected via a first inverter output line 9 to one end of a resistor 12 which constitutes a CR circuit 11. The other end of the resistor 12
A P-channel transistor (hereinafter referred to as a transistor), which is a CMOS transistor connected to the second power supply 7 via the capacitor 13 forming the CR circuit 11 and forming the second inverter 3 via the second inverter input line 9a. PT ₂ and N-channel transistor (hereinafter referred to as transistor) NT ₂ are commonly connected to each gate.

The power supply side of the transistor PT ₂ has a first power supply (V
_CC ) 6 and the ground side of the transistor NT ₂ is connected to the second power source (V _SS ) 7. Transistors PT ₂ and NT
The serial connection with ₂ is connected to the buffer output terminal 10.

Next, the operation of the buffer circuit thus configured will be described. First, a case in which the input signal a of the first inverter 2 is matched with no noise generated will be described with reference to FIG. 2 showing a timing chart of signals of respective parts.

Clocks having the same period but different phases are input to the clock input terminals 14 and 15, whereby the gate transistor GT _P is supplied with the clock d as shown in FIG. 2 (B).
Is on at the “L” level, and is turned on in the period T ₀ to connect the first power supply 6 to the first inverter 2.

Further, as shown in FIG. 2C, the gate transistor GT _N has a period T ₀ in which the clock e is at "H" level.
The second power source 7 is connected to the first inverter 2. Then, the gate transistors GT _P and GT _N are never turned on at the same time.

Now, when the input signal a of the first inverter 2 is at "L" level as shown in FIG. 2 (A), the transistor PT ₁ is turned on. As shown in FIG. 2B, the first inverter output line 9 has the first voltage during the period when the clock d is “L” and the gate transistor GT _P is on.
Connected to the power supply 6 and the capacitor of CR circuit 11
Since 13 is charged, the input signal bb of the second inverter 3 is always at "H" level as shown in FIG. 2 (D), and the output signal c of the second inverter 3 is as shown in FIG. 2 (E). It becomes the "L" level.

While the output signal c is at the "L" level, the transistor GT _N is turned on and there is a period T ₀ for connecting the first inverter 2 to the second power source 7, but the transistor NT ₁ is turned off. Since it is in the state, when the input signal a is at "L" level, the output signal b of the first inverter 2 does not become "L" level.

On the contrary, the input signal a of the first inverter 2
The If is the "H" level as shown in FIG. 2 (A), since the state of the transistor NT ₁ is turned on, the first inverter output line 9 during the period in which the gate transistors GT _N is on, the second It is connected to the power supply 7 and the CR circuit 11
Since the capacitor 13 of the second inverter 3 is discharged, the input signal bb of the second inverter 3 is always at "L" level, and the second inverter 3
The output signal c of is at "H" level.

While the input signal a is at "H" level, there is a period during which the gate transistor GT _P is turned on and the first inverter 2 is connected to the first power source 6, but the transistor PT ₁ is turned off. Therefore, the output signal b of the first inverter 2 does not become "H" level when the input signal a is "H" level.

Further, as shown in FIG. 2A, in the period in which the input signal a of the first inverter 2 is inverted from the "L" level to the "H" level, the gate transistor is first inverted after the input signal a is inverted. During the period in which GT _N is turned on and the first inverter output line 9 is connected to the second power supply 7, the CR circuit 11
Due to the time constant of, the potential of the second inverter input line 9a does not drop below the threshold voltage Vth. Then, the CR circuit 11 is opened.

Therefore, the output signal c of the second inverter 3
Holds the "L" level as shown in FIG. Then, when the gate transistor GT _N is next turned on and the first inverter output line 9 is connected to the second power supply 7, the potential of the second inverter input line 9a changes to the threshold voltage Vth.
The output signal c of the second inverter 3 decreases to the level shown in FIG.
It is inverted to the "H" level as shown in (E).

On the contrary, when the input signal a of the first inverter 2 is inverted from the "H" level to the "L" level, the gate transistor GT _P is set to 2 after the input signal a is inverted.
The output signal c of the second inverter 3 becomes the “L” level at the time of turning on the first time. After the input signal is inverted in this way, the output signal c of the second inverter 3 is not inverted until the second rising edge of the clock input to the gate transistor GT _P or GT _N.

Next, the operation when noises above and below the threshold voltage Vth occur in the input signal a to the buffer input terminal 8 will be described with reference to FIG.

First, when the input signal a of the first inverter 2 is at the "L" level as shown in FIG.
There the period "H" level as shown in FIG. 3 (C), if the threshold voltage Vth or more noise N _H is generated, the noise N _H
Is the threshold voltage Vth or higher, the transistor NT ₁
Turns on and the first inverter output line 9 is connected to the second power supply 7.

In this state, the capacitor 13 starts discharging, but the potential of the second inverter input line 9a becomes equal to or lower than the threshold voltage Vth during the period T1 when the noise N _H is equal to or higher than the threshold voltage Vth due to the time constant of the CR circuit 11. Never.

Therefore, in such a state, the output signal c of the second inverter 2 holds the "L" level as shown in FIG. 3 (E). Since the CR circuit 11 is in the open state until the clock d is inverted to the “L” level as shown in FIG. 3B after the noise N _H becomes equal to or lower than the threshold voltage Vth, The electric potential of the 2-inverter input line 9a remains as it is.

However, after the clock d is inverted to the "L" level and the gate transistor GT _P is turned on as shown in FIG. 3B, the CR circuit 11 is connected to the first power supply 6, The capacitor 13 is charged and the potential of the second inverter input line 9a rises again to the same level as the voltage of the first power source 6, that is, the "H" level.

Next, as shown in FIG. 3 (B), the period d1 during which the noise N _H equal to or higher than the threshold voltage Vth is generated is the clock d.
Is at the “L” level, the gate transistor GT _P turns on and the transistor NT ₁ turns on.
Since the PT ₁ and the gate transistor GT _N are turned off, the CR circuit 11 is released and the input signal bb of the second inverter 3 is input.
Remains at "H" level as shown in FIG. 3 (D) and does not change.

On the other hand, when the input signal a of the first inverter 2 is at "H" level and the clock d is at "L" level as shown in FIG. 3 (B), the threshold value as shown in FIG. 3 (A) is obtained. When the noise N _L that is equal to or lower than the voltage Vth occurs, the gate transistor GT _P and the transistor PT ₁ are turned on, and the first inverter output line 9 is connected to the first power supply 6. In this state, the capacitor 13 of the CR circuit 11 starts to be charged, but the time constant of the CR circuit 11 prevents the potential of the second inverter input line 9a from exceeding the threshold voltage Vth in the period T2.

Therefore, in such a state, the output signal c of the second inverter 3 maintains the "H" level state.
Since the CR circuit 11 is in the released state during the period from when the noise N _L becomes equal to or higher than the threshold voltage Vth to when the clock e is inverted to the “H” level as shown in FIG. 3 (C),
The potential of the second inverter input line 9a retains the current state.

When the clock e is inverted and the gate transistor GT _N is turned on, the CR circuit 11 is connected to the second power source 7, the capacitor 13 is discharged, and the potential of the second inverter input line 9a drops again. , And becomes the same level as the voltage of the second power supply 7.

Subsequently, when noise N _L below the threshold voltage Vth occurs again during the period when the clock e is at “H” level, the gate transistor GT _N is turned on and the transistor PT ₁ is turned on, and the gate transistor GT _P is turned on. Also, the transistor NT ₁ is turned off, the CR circuit 11 is released, and the input signal bb of the second inverter 3 holds the “L” level state up to now.

When the input signal a is inverted from the "L" level to the "H" level, the clock e rises for the second time as shown in FIG. 3C after the input signal a is inverted. When the gate transistor GT _N is turned on for the second time, the input signal bb of the second inverter 3 becomes lower than the threshold voltage Vth as shown in FIG. 3 (D), and as shown in FIG. 3 (E). The output signal c is inverted to "H" level. Similarly, when the input signal a is inverted from the “H” level to the “L” level, the output signal c is inverted to the “L” level when the clock d falls the second time after the inversion.

Here, the voltage of the first power source 6 is V ₀ (V),
The voltage of the threshold voltage level Vth is V _t (V), and the time during which the gate transistors GT _P and GT _N are in the ON state is T
₀ (seconds), the capacitance of the capacitor 13 in the CR circuit 11 is C ₀
(ΜF) and the resistance value of the resistor 12 is R ₀ (Ω), clocks d and e input to the gate transistors GT _P and GT _N
In order to invert the output signal c at the second rising time,

[0028]

[Equation 1]

It may be selected so as to satisfy the relationship of. In the buffer circuit configured as described above, when noise N _{H that} is equal to or higher than the threshold voltage occurs when the input signal a of the buffer circuit is “L” level, the output signal b of the first inverter becomes “L” level. , The gate transistor GT _P interposed between the first power source 6 and the power source side of the first inverter 2 is turned on to charge the capacitor 13 of the CR circuit 11,
Since the input signal bb of the second inverter 3 is prevented from falling below the threshold voltage Vth, the output signal c of the second inverter 3 is not inverted according to the noise N _H.

When the input signal a is at "H" level,
When noise N _L having a threshold voltage Vth or less is generated,
Although the output signal b of the inverter 2 becomes the “H” level, the gate transistor GT _N interposed between the second power supply 7 and the ground side of the first inverter 2 is turned on to turn on the capacitor 13 of the CR circuit 11. To discharge the input signal bb of the second inverter 3
Is prevented from rising above the threshold voltage Vth, the output signal c of the second inverter 3 is not inverted in response to the noise N _L.

[0031]

In the buffer circuit described above, when the clock input to the gate transistor is stopped, the operation state of the gate transistor becomes indefinite, and the first inverter loses its function as an inverter and the buffer circuit. There is a problem that the function of cannot be maintained. In view of such a problem, it is an object of the present invention to provide a buffer circuit that can hold the inverter function of the first inverter even when the clock of the gate transistor is stopped.

[0032]

In the buffer circuit according to the present invention, the clocks input to the gate transistors provided between the inverter and the first power supply and between the inverter and the second power supply are When stopped, a predetermined potential that turns on both gate transistors is applied to both gate transistors.

[0033]

The clocks having different phases in the same cycle are applied to the gate transistors interposed between the inverter and the first power supply and between the inverter and the second power supply to turn on both gate transistors alternately. When the clock is stopped, a predetermined potential for turning on both gate transistors is applied to both gate transistors to turn on both transistors. As a result, the inverter is held in a state of being connected to the first power supply and the second power supply, and the function of the inverter is held.

[0034]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 4 is a circuit diagram of a buffer circuit according to the present invention. The first inverter 2 as a buffer is composed of a P-channel transistor (hereinafter referred to as transistor) PT ₁ and an N-channel transistor (hereinafter referred to as transistor) NT _1.
Consists of CMOS transistors, transistor PT ₁
Each gate of NT ₁ and NT ₁ is connected to the buffer input terminal 8.

The power supply side of the transistor PT ₁ is connected to the first power supply (V _CC ) 6 via the P-channel gate transistor GT _P, and the ground side of the transistor NT ₁ is connected to the first power supply (V _CC ) 6 via the N-channel gate transistor GT _N. Two power supplies (V _SS ) 7 are connected. The gate of the gate transistor GT _P is connected to the clock input terminal 14 via the clock level fixing circuit 17, and the gate of the gate transistor GT _N is connected to the clock input terminal 15 via the clock level fixing circuit 17.

The clock control signal input terminal 16 is connected to the clock level fixing circuit 17. With transistor PT ₁
The series connection portion with NT ₁ is connected to one end of a resistor 12 that constitutes a CR circuit 11 via the first inverter output line 9, and the other end thereof is a capacitor 13 that constitutes the CR circuit 11.
Is connected to the second power source 7 through the second inverter 3, and the second inverter 3 is configured through the second inverter input line 9a.
The gates of P-channel transistor (hereinafter referred to as transistor) PT ₂ and N-channel transistor (hereinafter referred to as transistor) NT ₂ which are CMOS transistors are commonly connected.

The power source side of the transistor PT ₂ is the first power source (V
_CC ) 6 and the ground side of the transistor NT ₂ is connected to the second power source (V _SS ) 7. Transistors PT ₂ and NT
The serial connection with ₂ is connected to the buffer output terminal 10.

FIG. 5 is a circuit diagram of the clock level fixing circuit 17. The clock level fixing circuit 17 includes transmission gates 19a, 19b, 19c, 19d and an inverter 18. First input terminal 17a connected to clock input terminal 14
Is the first output terminal via the transmission gate 19a
Second connected to 17d and connected to clock input terminal 15
The input terminal 17b is connected to the second output terminal 17e via the transmission gate 19d.

The third input terminal 17c connected to the clock control signal input terminal 16 is connected to the first output terminal 17d via the transmission gate 19c, and also via the series circuit of the inverter 18 and the transmission gate 19d. It is connected to the second output terminal 17e. The gate of the N-channel transistor that forms the transmission gate 19a, the gate of the P-channel transistor 19c that forms the transmission gate 19c, and the gate of the N-channel transistor that forms the transmission gate 19b are connected together. 3rd input terminal 17c
Connected with.

The gate of the P-channel transistor that constitutes the transmission gate 19a, the gate of the N-channel transistor that constitutes the transmission gate 19d, and the gate of the P-channel transistor that constitutes the transmission gate 19b are common. It is connected and connected to the output side of the inverter 18. The first output terminal 17d is connected to the gate of the gate transistor GT _P and the second
The output terminal 17e is connected to the gate of the gate transistor GT _N.

Next, the operation of the buffer circuit thus configured will be described. When the clocks d and e having the same cycle but different phases are input to the clock input terminals 14 and 15, and the clocks d and e are not stopped, the clock control signal f input to the clock control signal input terminal 16 is When the clocks d and e stop at "H" level, the clock control signal f input to the clock control signal input terminal 16 becomes "L" level.

If the clocks d and e are not stopped, the clock control signal f is at "H" level, so that both transmission gates 19c and 19d are turned off and both transmission gates 19a and 19b are turned on. .. Therefore, the clocks d and e pass through the clock level fixing circuit and are input to the gates of the gate transistors GT _P and GT _N. Then, as will be described later, the propagation of noise is prevented.

On the other hand, when the clocks d and e are stopped,
Since the clock control signal f becomes "L" level, the transmission gates 19a and 19b are turned off and the transmission gates 19c and 19d are turned on. As a result, the "L" level clock control signal f is transmitted to the transmission gate 19
The “H” level inverted clock control signal ff, which is input to the gate of the gate transistor GT _P via c and inverted by the inverter 18, is input to the gate of the gate transistor GT _N ,
Both GT _P and GT _N are turned on and the transistor
Since PT ₁ is kept connected to the first power supply 6 and the transistor NT ₁ is kept connected to the second power supply 7, the first inverter 2 can keep its function as an inverter. However, in this case, since the functions of the gate transistors GT _P and GT _N are lost, noise propagation cannot be prevented.

Next, in the state where the clocks d and e are not stopped, first, with reference to FIG. 2, which shows a timing chart of each part signal in the case where the input signal a of the first inverter 2 is matched with no noise generated. explain.
As shown in FIG. 2B, the gate transistor GT _P is turned on in the period T ₀ when the clock d is at “L” level, and the first power source 6 is connected to the first inverter 2.

Further, as shown in FIG. 2 (C), the gate transistor GT _N has a period T ₀ in which the clock e is at "H" level.
The second power source 7 is connected to the first inverter 2. Then, the gate transistors GT _P and GT _N are never turned on at the same time.

Now, when the input signal a of the first inverter 2 is at "L" level as shown in FIG. 2 (A), the transistor PT ₁ is turned on. As shown in FIG. 2B, the first inverter output line 9 has the first voltage during the period when the clock d is “L” and the gate transistor GT _P is on.
Connected to the power supply 6 and the capacitor of CR circuit 11
Since 13 is charged, the input signal bb of the second inverter 3 is always at "H" level as shown in FIG. 2 (D), and the output signal c of the second inverter 3 is as shown in FIG. 2 (E). It becomes the "L" level.

While the output signal c is at "L" level, the transistor GT _N is on and there is a period T ₀ for connecting the first inverter 2 to the second power supply 7, but the transistor NT ₁ is off. Since it is in the state, when the input signal a is at "L" level, the output signal b of the first inverter 2 does not become "L" level.

On the contrary, the input signal a of the first inverter 2
Is at the “H” level as shown in FIG. 2 (A), the transistor NT ₁ is in the on state, so that the first inverter output line 9 is in the second state during the period in which the gate transistor GT _N is on. It is connected to the power supply 7 and the CR circuit 11
Since the capacitor 13 of the second inverter 3 is discharged, the input signal bb of the second inverter 3 is always at "L" level, and the second inverter 3
The output signal c of is at "H" level.

While the input signal a is at "H" level, there is a period during which the gate transistor GT _P is turned on and the first inverter 2 is connected to the first power source 6, but the transistor PT ₁ is turned off. Therefore, the output signal b of the first inverter 2 does not become "H" level when the input signal a is "H" level.

Further, as shown in FIG. 2A, in the period in which the input signal a of the first inverter 2 is inverted from the "L" level to the "H" level, the gate transistor is first inverted after the input signal a is inverted. During the period in which GT _N is turned on and the first inverter output line 9 is connected to the second power supply 7, the CR circuit 11
Due to the time constant of, the potential of the second inverter input line 9a does not drop below the threshold voltage Vth. Then, the CR circuit 11 is opened.

Therefore, the output signal c of the second inverter 3
Holds the "L" level as shown in FIG. Then, when the gate transistor GT _N is next turned on and the first inverter output line 9 is connected to the second power supply 7, the potential of the second inverter input line 9a changes to the threshold voltage Vth.
The output signal c of the second inverter 3 decreases to the level shown in FIG.
It is inverted to the "H" level as shown in (E).

On the contrary, when the input signal a of the first inverter 2 is inverted from the "H" level to the "L" level, the gate transistor GT _P is set to 2 after the input signal a is inverted.
The output signal c of the second inverter 3 becomes the “L” level at the time of turning on the first time. After the input signal is inverted in this way, the output signal c of the second inverter 3 is not inverted until the second rising edge of the clock input to the gate transistor GT _P or GT _N.

Next, the operation when the noises above and below the threshold voltage Vth occur in the input signal a to the buffer input terminal 8 will be described with reference to FIG.

First, when the input signal a of the first inverter 2 is at the "L" level as shown in FIG.
There the period "H" level as shown in FIG. 3 (C), if the threshold voltage Vth or more noise N _H is generated, the noise N _H
Is the threshold voltage Vth or higher, the transistor NT ₁
Turns on and the first inverter output line 9 is connected to the second power supply 7.

In this state, the capacitor 13 starts discharging, but the potential of the second inverter input line 9a becomes equal to or lower than the threshold voltage Vth during the period T1 when the noise N _H is equal to or higher than the threshold voltage Vth due to the time constant of the CR circuit 11. Never.

Therefore, in such a state, the output signal c of the second inverter 2 holds the "L" level as shown in FIG. 3 (E). Since the CR circuit 11 is in the open state until the clock d is inverted to the “L” level as shown in FIG. 3B after the noise N _H becomes equal to or lower than the threshold voltage Vth, The electric potential of the 2-inverter input line 9a remains as it is.

However, after the clock d is inverted to the "L" level and the gate transistor GT _P is turned on as shown in FIG. 3B, the CR circuit 11 is connected to the first power supply 6, The capacitor 13 is charged and the potential of the second inverter input line 9a rises again to the same level as the voltage of the first power source 6, that is, the "H" level.

Next, as shown in FIG. 3 (B), the period T1 in which the noise N _H of the threshold voltage Vth or more is generated is the clock d.
Is at the “L” level, the gate transistor GT _P turns on and the transistor NT ₁ turns on.
Since the PT ₁ and the gate transistor GT _N are turned off, the CR circuit 11 is released and the input signal bb of the second inverter 3 is input.
Remains at "H" level as shown in FIG. 3 (D) and does not change.

On the other hand, when the input signal a of the first inverter 2 is at the "H" level and the clock d is at the "L" level as shown in FIG. 3 (B), the threshold value is changed as shown in FIG. 3 (A). When the noise N _L that is equal to or lower than the voltage Vth occurs, the gate transistor GT _P and the transistor PT ₁ are turned on, and the first inverter output line 9 is connected to the first power supply 6. In this state, the capacitor 13 of the CR circuit 11 starts to be charged, but the time constant of the CR circuit 11 prevents the potential of the second inverter input line 9a from exceeding the threshold voltage Vth in the period T2.

Therefore, in such a state, the output signal c of the second inverter 3 maintains the "H" level state.
Since the CR circuit 11 is in the released state during the period from when the noise N _L becomes equal to or higher than the threshold voltage Vth to when the clock e is inverted to the “H” level as shown in FIG. 3 (C),
The potential of the second inverter input line 9a retains the current state.

When the clock e is inverted and the gate transistor GT _N is turned on, the CR circuit 11 is connected to the second power source 7, the capacitor 13 is discharged, and the potential of the second inverter input line 9a drops again. , And becomes the same level as the voltage of the second power supply 7.

Subsequently, when noise N _L equal to or lower than the threshold voltage Vth occurs again while the clock e is at the “H” level, the gate transistor GT _N is turned on and the transistor PT ₁ is turned on, and the gate transistor GT _P is turned on. Also, the transistor NT ₁ is turned off, the CR circuit 11 is released, and the input signal bb of the second inverter 3 holds the “L” level state up to now.

When the input signal a is inverted from the "L" level to the "H" level, after the input signal a is inverted, the clock e rises for the second time as shown in FIG. 3 (C). When the gate transistor GT _N is turned on for the second time, the input signal bb of the second inverter 3 becomes lower than the threshold voltage Vth as shown in FIG. 3 (D), and as shown in FIG. 3 (E). The output signal c is inverted to "H" level. Similarly, when the input signal a is inverted from the “H” level to the “L” level, the output signal c is inverted to the “L” level when the clock d falls the second time after the inversion.

Here, the voltage of the first power source 6 is V ₀ (V),
The voltage of the threshold voltage level Vth is V _t (V), and the time during which the gate transistors GT _P and GT _N are in the ON state is T
₀ (second), the capacitance of the capacitor 13 in the CR circuit 11 is C ₀ (μF), and the resistance value of the resistor 12 is R ₀ (Ω), the clocks d and e input to the gate transistors GT _P and GT _N are 2 clocks. In order to invert the output signal c at the time of rising the third time, it may be selected so as to satisfy the relationship of the above-mentioned expression (1).

In the buffer circuit thus configured, when the noise N _H above the threshold voltage occurs when the input signal a of the buffer circuit is at the "L" level, the output signal b of the first inverter is at the "L" level. However, the gate transistor GT _P interposed between the first power supply 6 and the power supply side of the first inverter 2 is turned on to charge the capacitor 13 of the CR circuit 11, and the input signal of the second inverter 3 is supplied. bb is the threshold voltage Vth
The output signal c of the second inverter 3 is not inverted in response to the noise N _H because it is prevented from falling below.

When the input signal a is at "H" level,
When noise N _L having a threshold voltage Vth or less is generated,
Although the output signal b of the inverter 2 becomes the “H” level, the gate transistor GT _N interposed between the second power supply 7 and the ground side of the first inverter 2 is turned on to turn on the capacitor 13 of the CR circuit 11. To discharge the input signal bb of the second inverter 3
Is prevented from rising above the threshold voltage Vth, the output signal c of the second inverter 3 is not inverted in response to the noise N _L. Therefore, the noise generated in the input signal a does not propagate to the output signal c.

[0067]

As described above in detail, the present invention is provided between the power source side of the first inverter and the first power source, and between the ground side of the first inverter and the second power source. When the clock input to the gate transistor is stopped, each of the gate transistors is fixed in the ON state, so that the first inverter is held in the state of being connected to the first power source and the second power source, The function of the first inverter can be retained. Therefore, according to the present invention, it is possible to provide an excellent effect that it is possible to provide a buffer circuit that does not propagate noise and that does not impair the function of the inverter even when the clock input to the gate transistor is stopped.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a buffer circuit that does not propagate noise.

FIG. 2 is a timing chart of signals of respective parts of the buffer circuit when noise is not generated.

FIG. 3 is a timing chart of signals at various parts of the buffer circuit when noise occurs.

FIG. 4 is a circuit diagram of a buffer circuit according to the present invention.

FIG. 5 is a circuit diagram of a clock level fixing circuit.

[Explanation of symbols]

2 1st inverter 3 2nd inverter 6 1st power supply 7 2nd power supply 8 Buffer input terminal 10 Buffer output terminal 11 CR circuit 14,15 Clock input terminal 16 Clock control signal input terminal PT ₁ , PT ₂ P channel transistor NT ₁ , NT ₂ N-channel transistor GT _P P-channel gate transistor GT _N N-channel gate transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0948 6959-5J H03K 19/094 B

Claims (1)

Claim: What is claimed is: 1. A first gate transistor is interposed between an inverter composed of a CMOS transistor and a first power supply, and a second gate transistor is interposed between the inverter and a second power supply. In a buffer circuit in which both gate transistors are on / off controlled by clocks having the same cycle and different phases to prevent the propagation of noise, when the clock is stopped, the first gate transistor and the second gate transistor are turned on. A buffer circuit, characterized in that a predetermined potential for turning on both is applied to both gate transistors.