JPH0537807A - Pulse signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of a post-stage circuit by implementing mask processing for a prescribed time length at a changeover output of a pulse signal so as to block the production of a narrow pulse at the changeover of the pulse signal. CONSTITUTION:A synchronization clock detection circuit 2 selects a desired clock among clock signals CO-Cn from a clock phase shift circuit 1 based on a timing reference signal and outputs the selected signal. Moreover, a clock mask signal generating circuit 3 receives the timing reference signal, a clock before selection changeover and a clock selected next and uses the selected clock information to output a mask signal. That is, a 1st pulse train signal selected at present based on the reference signal, after the output of the pulse of the 1st pulse train signal in response to the reference clock signal, the changeover output of the 1st and 2nd pulse train signals is inhibited by the mask signal for a predetermined time length relating to the edge of the 2nd pulse train signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal processing circuit, and more particularly to a pulse signal processing circuit for preventing the generation of spikes when switching to different pulse train signals.

[0002]

2. Description of the Prior Art During operation, of a plurality of different pulse trains,
A circuit for switching and using pulse trains having a predetermined timing relationship (for example, a relationship in which rising phases of corresponding pulses are closest to each other) is used in various fields. For example, in a time axis correction circuit (TBC) that adjusts the time axis of a luminance signal (Y signal) and a color signal (C signal) in a video device such as a still video floppy disk (SVF), a pulse signal for such pulse switching is used. A processing circuit is used. That is, in the SVF reproducing apparatus, in order to correct the fluctuation of the time axis of the Y signal and the C signal due to the jitter of the rotating system and the asynchronous signal processing, and to accurately A / D-convert the Y signal and the C signal which are not in the synchronized state. In the previous application of the applicant of the present application, Japanese Patent Application No. 1-138908, a pulse signal processing circuit as shown in FIG. 4 is proposed.

In FIG. 4, a burst signal extraction circuit 46 is shown.
Extracts the burst signal from the C signal. APC47 is
A clock of a reference frequency (14.3 MHz in this example) synchronized with the extracted burst signal is generated. The C signal is given a predetermined delay by the delay circuit 48 to be adjusted in timing, then A / D converted by the reference clock from the APC 47 in the A / D converter 49, and sent to the latch circuit 50 by the reference clock from the APC 47. Latched.
On the other hand, a sync signal is extracted from the Y signal by the sync signal extraction circuit 41 and sent to the phase modulator 44. The phase modulator 44 phase-modulates the reference clock from the APC 47 with the sync signal extracted by the sync signal extraction circuit 41 and outputs 1
A / D as a clock synchronized with the Y signal of 4.3 MHz
It is supplied to the converter 43. The Y signal delayed for a predetermined time in the delay circuit 42 is A / D converted by the clock from the phase modulator 44 in the A / D converter 43, and the latch circuit 4
5 is latched by the reference clock from the APC 47.

A concrete circuit configuration example of the phase modulator 44 is, as shown in FIG. 5, cascade-connected delay elements 441a, 441b, 441c, ..., 441n for inputting a reference clock CLK of 14.3 MHz from the APC 47. , Cn of the output clocks C0, C1, C2, ..., And Cn of the synchronizing signal from the synchronizing signal extracting circuit 46 are compared by the phase comparing section 442, and the clock signal of the phase closest to the synchronizing signal is selected. Output as modulated output. In FIG. 6, among the outputs of the delay elements 441a, 441b, ..., Output clock trains C0, C1 from the delay element at the fourth stage from the input side are shown.
, C2, C3 and a timing reference signal for switching and outputting the clock train, a desired clock train is selectively output based on the timing reference signal. In this way, both signals are output from the latch circuits 45 and 50 in a synchronized state.

[0005]

As described above, in the conventional pulse signal processing circuit of this type, a desired pulse train is selected from a plurality of different pulse trains by the timing reference signal and is switched and output. . However, when a clock train is switched based on the timing reference signal, a spike pulse having a narrow pulse width as described below occurs, which causes a problem such as a timing error and an adverse effect at the time of sampling and holding. That is, at the time of switching, if the pulse width becomes too narrow regardless of whether it is a positive pulse or a negative pulse, the minimum pulse width requirement specified in the specifications of the IC or the like cannot be satisfied, and the IC in such a situation cannot be satisfied. Since such operations are not compensated, they pose a big problem. For example, when the clock train C0 to the clock train C3 shown in FIG. 6 are selected according to the change point (falling edge) of the timing reference signal from the high level to the low level, the modulation clock obtained by the selection is as shown in FIG. The time interval T between the fall and rise of the clock before and after the switching is narrowed, so-called spike pulse occurs, which causes the problem as described above. Also,
When the time when the level of the timing reference signal changes is within the high level period of the clock train before selection, the modulation clock becomes a pulse having a narrow width and the same problem occurs. This effect becomes particularly serious when an operation using both edges of the clock is performed as in the A / D converter. It is also known that the influence of a malfunction due to a timing error does not stop at that point and continues for a certain period of time (metastable).

Therefore, an object of the present invention is to provide a pulse signal processing circuit which prevents generation of a narrow pulse (spike pulse) even when different pulse signal clock trains are switched.

[0007]

In order to solve the above-mentioned problems, a pulse signal processing circuit according to the present invention has a predetermined timing relationship with a supplied first pulse train signal among a plurality of pulse train signals having different phases. The pulse train signal to be satisfied is selected as the second pulse train signal, and the supplied first train
Is a pulse signal processing circuit for outputting an output pulse train signal in a mode in which the pulse train signal is switched to the second pulse train signal at a predetermined timing, wherein the second pulse train signal is selected from the plurality of pulse train signals. The level of the first pulse train signal at the selected first time point is maintained at least for a time period until the arrival of the first edge, which is the first edge of the first pulse train signal after the first time point, and the first edge When the second edge, which is the edge of the second pulse train signal that first arrives after the arrival of the second edge, is an edge in the same direction as the first edge, the first and second pulse train signals after the second edge arrival time. Before the edge comes, the supplied first pulse train signal is allowed to be switched to the second pulse train signal and output, and the second pulse train signal is output. Is an edge in a direction different from that of the first edge, the first edge immediately after the first edge until the third edge arrival time which is the edge of the second pulse train signal that first arrives after the arrival time of the second edge. The level of the pulse train signal is maintained, and the supplied first pulse train signal is switched to the second pulse train signal and output after the third edge arrives and before the next edge of the second pulse train signal. And a switching timing control unit for switching. Further, the pulse signal processing circuit according to the present invention includes the first pulse train signal currently selected from the plurality of different pulse train signals and the second pulse train signal selected next.
A pulse signal processing circuit for switching and outputting the pulse train signal on the basis of a reference clock signal, which is currently outputting the first pulse train signal in response to the reference clock signal or after the output of the next one pulse. , A means for inhibiting the switching output of the second pulse train signal for a predetermined time length associated with the rising or falling of the second pulse train signal.

[0008]

According to the present invention, when the first pulse train signal currently selected from the plurality of different pulse train signals and the second pulse train signal selected next are switched and output based on the reference clock signal, the reference clock signal is output. After the pulse of the first pulse train signal is output in response to the signal, the first pulse train signal and the second pulse train signal have a predetermined time length in relation to the edges such as the rising edge and the falling edge of the second pulse train signal. By providing the timing control means by the mask signal for prohibiting the switching output of the above, the stable pulse signal processing circuit which prevents the generation of the spike pulse at the time of switching the pulse train signal is obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a pulse signal processing circuit according to the present invention. Clock phase shift circuit 1
Has a circuit configuration similar to that of the cascade-connected delay elements in FIG. 5, and clocks C0, C1, C2, C3, ..., Cn-1, Cn in which the clocks are sequentially delayed by a minute time.
Is output. The synchronous clock detection circuit 2 selects and outputs a desired clock from the clocks C0 to Cn from the clock phase shift circuit 1 based on the timing reference signal. The clock mask (clip) signal generation circuit 3 receives the timing reference signal, the clock before selection switching (the clock that has been selected until then) and the clock selected next, and uses the selected clock information to generate a mask signal. Is output. The mask signal does not switch the clock immediately when the state of the timing reference signal changes (at the time of switching), but for example, masks the clock from the fall of the clock that has been selected until then to stop the generation of the modulation clock. , A signal for switching the clock in synchronization with the falling edge of the next selected clock.

The clock switching circuit 4 receives the previously selected clock from the synchronous clock detection circuit 2, a selection signal indicating the number of the next selected clock, and a switching signal, and receives the clock phase. The clock selected next from the clocks C0 to Cn from the shift circuit 1 is output. The level clip circuit 5 level clips the output clock of the clock switching circuit 4 based on the clip signal output from the clock mask signal generation circuit 3, that is, when the clip signal is at the "L" level, the modulation clock is at the "L" level. Clip to level.

FIG. 2 shows the timing relationship between the selected clock and the timing reference signal and the modulation clock in the above embodiment. In this example, the clock C0 selected until then is changed based on the timing reference signal.
This is an example of switching to the selected clock C3 and outputting as a modulation clock. The modulation clock is controlled by a clip signal from the clock mask signal generation circuit 3 as a clock mask signal. That is, in the present embodiment, when the clock C0 is switched to the clock C3 in response to the timing reference signal in the clock groups C0 to Cn, after the "H" level period T1 (or "L" level period) of the clock C0 has elapsed. The modulated clock is clipped to the "L" level (or "H" level) from the timing t1 and the clock mask signal (clip signal) is leveled so as to switch the clock at the falling timing t2 of the selected clock C3. It is sent to the clip circuit 5. By doing so, it is possible to prevent the generation of a narrow pulse (spike pulse) that occurs in the modulation output when the clock is switched. If you do not need to change the clock quickly,
The mask period T2 may be set sufficiently long and switched so as to satisfy the "H" level width (or "L" level width) of the next selected clock.

FIG. 3 shows a concrete circuit example of the clock mask signal generating circuit 3 of the embodiment circuit shown in FIG. This circuit includes D flip-flops 31 and 32 and O.
It is composed of an R gate 33, and the timing reference signal is input to the D input of the flip-flop 31, the clock C0 is input to the clock terminal, and the Q output thereof is sent to the D input terminal of the flip-flop 32 in the next stage. Flip flop 32
The clock input terminal of the
Is entered. Further, the Q output of the flip-flop 31 and the inverted Q output of the flip-flop 32 are input to the OR gate 33, and the output of the OR gate 33 is supplied to the level clip circuit 5 as a clip signal. In the circuit shown in FIG. 3, A between flip-flops 31 and 32
By inserting a delay circuit having an appropriate delay time after the point, it is possible to prevent malfunction of the circuit due to mixing of spike pulses at the time of clock switching. Also, the modulation clock can be switched at the rising edge of the output of the OR gate 33, and as a result, the spike due to the switching of the clock C3 can be masked.

[0013]

As described above, since the pulse signal processing circuit according to the present invention is configured to perform the mask processing of a predetermined time length at the switching output of the pulse signals, the narrow width generated at the switching of the pulse signals. It is possible to prevent the generation of a pulse and prevent the malfunction of the subsequent circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pulse signal processing circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment circuit shown in FIG.

FIG. 3 is a specific circuit example of a clock mask signal generation circuit of the embodiment circuit shown in FIG.

FIG. 4 is a diagram showing an example of a conventional pulse signal processing circuit.

5 is a diagram showing a circuit example of a phase modulator in the circuit of FIG.

FIG. 6 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 7 is a timing chart for explaining problems of the conventional pulse signal processing circuit.

[Explanation of symbols]

 1 Clock Phase Shift Circuit 2 Synchronous Clock Detection Circuit 3 Clock Mask (Clip) Signal Generation Circuit 4 Clock Switching Circuit 5 Level Clip Circuit 31, 32 D Flip Flop 33 OR Gate 41 Synchronous Signal Extraction Circuit 42, 48 Delay Circuit 43, 49 A / D converter 44 Phase modulator 45,50 Latch circuit 46 Burst signal extraction circuit 47 APC

Claims (2)

[Claims] 1. A pulse train signal that satisfies a predetermined timing relationship with a supplied first pulse train signal out of a plurality of pulse train signals having different phases is selected as a second pulse train signal, and the supplied first pulse train signal is selected. Is a pulse signal processing circuit for outputting an output pulse train signal in a mode in which it is switched to the second pulse train signal at a predetermined timing, wherein the second pulse train signal is selected from the plurality of pulse train signals. The level of the first pulse train signal at one time is maintained at least for a time period until the first edge, which is the first edge of the first pulse train signal after the first time, arrives, and at the time when the first edge arrives. The second pulse train signal, which is the edge of the second pulse train signal that arrives first,
When the edge is an edge in the same direction as the first edge, the supplied first pulse train signal is supplied to the second pulse before the edges of the first and second pulse train signals arrive after the arrival of the second edge. It is allowed to switch to a pulse train signal and output, and when the second edge is an edge in a direction different from that of the first edge, it is the edge of the second pulse train signal that first arrives after the arrival time of the second edge. The level of the first pulse train signal immediately after the first edge is maintained until the arrival of the third edge, and the first pulse train supplied after the arrival of the third edge and before the edge of the next second pulse train signal. A pulse signal processing circuit, comprising switching timing control means for permitting switching of a signal to the second pulse train signal and outputting the signal. 2. A pulse signal processing circuit for switching and outputting a first pulse train signal currently selected from a plurality of different pulse train signals and a second pulse train signal selected next based on a reference clock signal. And, in response to the reference clock signal, the current output of the first pulse train signal, or after the output of the next one pulse,
A pulse signal processing circuit comprising means for inhibiting switching output of the second pulse train signal for a predetermined time length in relation to rising or falling of the second pulse train signal.