JPH0538441Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a magnetic recording and reproducing device for reproducing digital signals recorded on a magnetic recording medium such as a magnetic tape. The present invention relates to a synchronization signal detection circuit for detecting the synchronization signal of each block from reproduced data in which a synchronization signal is added to the block.

[Prior art and its problems] When a video signal is digitized and recorded on a magnetic tape using a rotating magnetic head, the video data is divided into blocks for each predetermined number of samples, and a synchronization signal is added to each block to continuously record the video data on a magnetic tape. It is recorded.
When reproducing this continuously recorded data, the beginning of the block is detected in the reproduced data, and
Based on this detection, various processes are performed in the reproduction system.

As a method of detecting the first synchronization signal of the above block, a window signal of a predetermined width is formed using a detection signal indicating the rotational phase of a rotary head rotating at a field frequency or a frame frequency, or a reference vertical synchronization signal. There is a method to obtain the synchronization signal contained in the signal.

Although this method has a simple circuit configuration, it is disadvantageous against mechanical fluctuations because the window width is narrowed to improve accuracy. Also, it is possible to provide an interpolation circuit in case a synchronization signal cannot be obtained during the window signal, but if the pseudo synchronization signal obtained by the counter is missing, all data in that field will be lost. It turns out.

[Purpose of the invention] The present invention was made in view of the above-mentioned circumstances, and has a simple circuit configuration, is not affected by mechanical fluctuations,
Another object of the present invention is to provide a synchronization signal detection circuit that can reliably obtain a synchronization signal even when a pseudo synchronization signal is lost in an interpolation circuit.

[Key Points of the Invention] The present invention is a magnetic recording and reproducing device that reproduces digital signals recorded on a magnetic recording medium, in which the digital signal is divided into blocks and a synchronization signal is added to each block. A circuit that performs signal pattern matching to detect a reproduction synchronization signal, a circuit that counts the number of data bits using a clock synchronized with reproduction data and outputs a first pseudo synchronization signal, and a circuit that counts a reference clock and detects a synchronization signal. A circuit that outputs a window signal having a pulse width of multiple bits before and after the timing to be reproduced, and a circuit that outputs a second pseudo synchronization signal at the central timing of the window signal, and synchronizes the reproduction within the window signal. When the signal is detected, it is output as a synchronization signal, when it is not detected, the first pseudo synchronization signal in the window signal is output as a synchronization signal, and the playback synchronization signal and the first pseudo synchronization signal are output in the window signal. When none of the pseudo synchronization signals is detected, a second pseudo synchronization signal is output as a synchronization signal.

[Embodiment of the invention] An embodiment of the invention will be described below with reference to the drawings. When a video signal, an audio signal, etc. is digitized and recorded on a magnetic tape by a rotating magnetic head, the data is divided into blocks for each predetermined number of samples, and a synchronization signal is added to each block. That is, as shown in FIG. 1, each block has a sync pattern area 1, a block address area 2,
It is composed of a data area 3 and a parity area 4, and is continuously recorded on a magnetic recording medium such as a magnetic tape.

Each block of data sequentially output from the magnetic recording medium by the magnetic head is sent to a synchronization signal detection circuit shown in FIG. 2, where a synchronization signal is detected. In FIG. 2, 11 is a pattern matching circuit that matches the sync pattern of the reproduced data with the reference pattern, and outputs a pulse signal for one PLL clock PCK as a reproduction synchronization signal f, as shown in FIG. Input to NAND gate NA1. The PLL clock PCK is a bit clock synchronized with reproduced data extracted by a PLL circuit (not shown). 12 is a sync counter, which is reset by the detection circuit signal m output from the NAND gate NA4, which will be described later, and is reset by the PLL.
The clock PCK is counted and when a certain count is reached, the first pseudo synchronization signal g is output. This pseudo synchronization signal g is input to the NAND gate NA2. Reference numeral 13 denotes a base counter, which is set by the synchronization signal m and counts the master clock MCK used during recording, and outputs a window signal b having a certain width centered on the timing at which the playback synchronization signal f should originally be output, and a window signal b having a certain width centered on the timing at which the playback synchronization signal f should originally be output. Generates signals a and c that precede and follow the signal. In this case, the signal c
rises approximately at the center of the window signal b. and,
The window signal b output from the base counter 3 is input to NAND gates NA1 and NA2,
Signals a and c are input to edge detection circuits 14 and 15, respectively, together with master clock MCK. The edge detection circuit 14 detects the rising edge of the signal a and outputs a signal d (low level) corresponding to one master clock MCK, and outputs a signal d (low level) corresponding to one master clock MCK.
Set. Further, the edge detection circuit 15 detects the rising edge of the signal b and outputs the master clock signal.
Outputs signal e (high level) for one MCK and inputs it to NAND gate NA3. The flip-flop 16 is set by the output h of the NAND gate NA1, and its Q output i is set by the output h of the NAND gate NA1.
2. Input to NA3. flipflop 17
is set by the output j of the NAND gate NA2, and its Q output k is input to the NAND gate NA3. And the above NAND gates NA1, NA2,
The output signal of NA3 is taken out via NAND gate NA4, inputted to the reset terminal R of the sync counter 12 and base counter 13, and sent to the next stage processing circuit as a synchronizing signal m.

Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG. The pattern matching circuit 11 performs pattern matching between the reproduced data and the reference pattern, and outputs a reproduction synchronization signal f when they match. On the other hand, the sink counter 12 is
It counts up by the PLL clock PCK and outputs the first pseudo synchronization signal g at the position where the next synchronization signal is to be reproduced. In addition, the base counter 13
counts the master clock MCK and generates a window signal b with a constant time width, and also generates signals a and c with the same width before and after this signal b.
This signal c is sent to the edge detection circuit 15 together with the master clock MCK.
A second pseudo synchronization signal e having a width of 1 bit is output at the center of the window signal b.

Therefore, there are three kinds of signals: the signal f output from the pattern matching circuit 11, the first pseudo synchronization signal g output from the sync counter 12, and the second pseudo synchronization signal e output from the edge detection circuit 15. The signals are selected according to a predetermined priority order and output as a synchronization signal m. 3 with a given priority
A synchronizing signal m is obtained by a different interpolation circuit.

The above priority order is determined as follows.
The base counter 13 counts the master clock MCK as described above and outputs the signal a before the window signal b. The rising edge of signal a is detected by edge detection circuit 14, which outputs edge detection circuit d (low level) synchronized with master clock MCK, and flip-flops 16 and 17 are set. As a result, the outputs i of flip-flops 16 and 17,
k rises to a high level. Thereafter, the base counter 13 outputs a window signal b with a one-bit delay, that is, a window signal b having a constant time width centered around the reproduction synchronization signal f to be extracted by the pattern matching circuit 11, and the NAND gate NA1, Given to NA2. Therefore, while the base counter 13 is outputting the window signal b, if the pattern matching circuit 11 extracts the reproduction synchronization signal f as shown in FIG.
The output h of the NAND gate NA1 becomes low level, and as a result, the output of the NAND gate NA4 becomes high level and is output as the synchronization signal m. At this time, the signal h output from NAND gate NA1
The flip-flop 16 is reset by the fall of the flip-flop 16, its output signal i becomes low level, and the gates of the NAND gates NA2 and NA3 are closed. This prohibits the output of the first pseudo synchronization signal g from the sync counter 12 and the second pseudo synchronization signal e from the edge detection circuit 15. If the pattern matching circuit 11 extracts the playback synchronization signal f while the window signal b is output as described above, this playback synchronization signal f is taken out from the NAND gates NA1 and NA4 with priority, and synchronization is performed. signal m
is output as And the above nand gate
By outputting the synchronization signal m from NA4,
The sync counter 12 and base counter 13 are reset, and the next synchronization signal detection operation is started. Note that if the second pseudo synchronization signal g is output from the sync counter 12 before the reproduction synchronization signal f is extracted due to jitter or the like, the signal g is first output via the NAND gates NA2 and NA4.
At the time when the reproduction synchronization signal f having a high priority is extracted, the flip-flop 16 is reset, the gate of the NAND gate NA2 is closed, and the output of the second pseudo synchronization signal g is prohibited. Also, the PLL clock
3rd clock because PCK and master clock MCK are asynchronous.
As shown in the figure, the NAND gate appears before the synchronization signal f.
The signal l may be output from NA3, but there is no particular problem because the gate of NAND gate NA3 closes when the synchronization signal f or the second pseudo synchronization signal g is output, and the output l returns to the high level state. .

On the other hand, if the synchronization signal f is not extracted in the pattern matching circuit 11, the output h of the NAND gate NA1 is held at a high level,
Flip-flop 6 is not reset and Q output i
remains at a high level. Therefore, when the first pseudo synchronization signal g is output from the sync counter 12, this pseudo synchronization signal g is
It is extracted as a synchronization signal m via NA2 and NA4. Further, when the first pseudo synchronization signal g is output from the NAND gate NA2, the flip-flop 17 is reset, its Q output becomes low level, and the gate of the NAND gate NA3 is closed. As a result, even if the second pseudo synchronization signal e is output from the edge detection circuit 15, the NAND gate NA
Blocked by 3.

Further, as shown in FIG. 4, while the window signal b is being output from the base counter 13,
If neither the signals f nor g are output from the pattern matching circuit 11 or the sync counter 12 due to a burst error or the like, the flip-flops 16 and 17 are not reset and their Q outputs i, k
is maintained at a high level. Therefore, when the second pseudo synchronization signal e is output from the edge detection circuit 15, it is taken out as the synchronization signal m via the NAND gates NA3 and NA4.

[Effects of the invention] As detailed above, according to the invention, in a magnetic recording and reproducing device that reproduces digital signals recorded on a magnetic recording medium, the digital signals are divided into blocks, and a synchronization signal is assigned to each block. In the added version, both pattern matching of the bit pattern of the playback synchronization signal and determination based on the wind signal are used to detect the playback synchronization signal, so the wind signal width can sufficiently cover mechanical fluctuations. The width can be set as large as possible, and error signals caused by dropouts and the like can be removed by the window signal. Furthermore, by using the window signal, signals recorded by other devices can be easily reproduced. Furthermore, since a triple interpolation circuit is provided to obtain the synchronization signal, the synchronization signal can be reliably obtained and error data can be minimized.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the data structure of one block of recording/reproduction data, FIG. 2 is a block diagram showing the circuit configuration, and FIGS. 3 is a timing chart for explaining a synchronization signal detection operation. 11...Pattern matching circuit, 12...Sink counter, 13...Base counter, 14,
15... Edge detection circuit, 16, 17... Flip-flop, NA1 to NA4... NAND gate.

Claims (1)

[Scope of utility model registration request] In a magnetic recording and reproducing device that reproduces a digital signal recorded on a magnetic recording medium, the digital signal is divided into blocks and a synchronization signal is added to each block, and pattern matching is performed on the reproduced digital signal. A pattern matching circuit that detects a reproduction synchronization signal, a circuit that counts the number of data bits using a clock synchronized with reproduction data and outputs a first pseudo synchronization signal at the timing when the synchronization signal is to be reproduced, and a reference clock. a circuit for counting and outputting a window signal having a pulse width of a plurality of bits before and after the timing at which the synchronization signal is to be reproduced; a circuit for outputting a second pseudo synchronization signal at a central timing of the window signal; When a playback synchronization signal is detected within the signal, it is output as a synchronization signal, and when it is not detected, the first pseudo synchronization signal within the window signal is output as a synchronization signal, and the playback synchronization signal is reproduced within the window signal. A synchronization signal detection circuit comprising: a gate circuit that outputs a second pseudo synchronization signal as a synchronization signal when neither the synchronization signal nor the first pseudo synchronization signal is detected.