JPS6423765U - - Google Patents
Info
- Publication number
- JPS6423765U JPS6423765U JP11504787U JP11504787U JPS6423765U JP S6423765 U JPS6423765 U JP S6423765U JP 11504787 U JP11504787 U JP 11504787U JP 11504787 U JP11504787 U JP 11504787U JP S6423765 U JPS6423765 U JP S6423765U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- signal
- circuit
- pseudo
- reproduced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000003708 edge detection Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
図面は本考案の一実施例を示すもので、第１図
は記録／再生データの１ブロツクのデータ構成を
示す図、第２図は回路構成を示すブロツク図、第
３図及び第４図は同期信号の検出動作を説明する
ためのタイミングチヤートである。
１１…パターンマツチング回路、１２…シンク
カウンタ、１３…ベースカウンタ、１４，１５…
エツジ検出回路、１６，１７…フリツプフロツプ
、ＮＡ１〜ＮＡ４…ナンドゲート。
The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the data structure of one block of recording/reproducing data, FIG. 2 is a block diagram showing the circuit configuration, and FIGS. 3 is a timing chart for explaining a synchronization signal detection operation. 11... Pattern matching circuit, 12... Sink counter, 13... Base counter, 14, 15...
Edge detection circuit, 16, 17...flip-flop, NA1-NA4...NAND gate.
Claims (1)
生する磁気記録再生装置で、上記デジタル信号が
ブロツク化され、各ブロツクに同期信号が付加さ
れたものにおいて、再生デジタル信号のパターン
マツチングを行なつて再生同期信号を検出するパ
ターンマツチング回路と、再生データに同期した
クロツクでデータビツト数をカウントし、同期信
号が再生されるべきタイミングで第１の疑似同期
信号を出力する回路と、基準クロツクをカウント
し同期信号が再生されるべきタイミングの前後複
数ビツト分のパルス幅を有するウインド信号を出
力する回路と、該ウインド信号の中央のタイミン
グで第２の疑似同期信号を出力する回路と、上記
ウインド信号内で再生同期信号が検出された際に
これを同期信号として出力し、検出されなかつた
際に上記ウインド信号内の第１の疑似同期信号を
同期信号として出力し、上記ウインド信号内で再
生同期信号及び第１の疑似同期信号の何れも検出
されなかつた際に第２の疑似同期信号を同期信号
として出力するゲート回路とを具備したことを特
徴とする同期信号検出回路。 In a magnetic recording and reproducing device that reproduces a digital signal recorded on a magnetic recording medium, the digital signal is divided into blocks and a synchronization signal is added to each block, and pattern matching is performed on the reproduced digital signal. A pattern matching circuit that detects a reproduction synchronization signal, a circuit that counts the number of data bits using a clock synchronized with reproduction data and outputs a first pseudo synchronization signal at the timing when the synchronization signal should be reproduced, and a reference clock. a circuit for counting and outputting a window signal having a pulse width of a plurality of bits before and after the timing at which the synchronization signal is to be reproduced; a circuit for outputting a second pseudo synchronization signal at a central timing of the window signal; When a playback synchronization signal is detected within the signal, it is output as a synchronization signal, and when it is not detected, the first pseudo synchronization signal within the window signal is output as a synchronization signal, and the playback synchronization signal is reproduced within the window signal. A synchronization signal detection circuit comprising: a gate circuit that outputs a second pseudo synchronization signal as a synchronization signal when neither the synchronization signal nor the first pseudo synchronization signal is detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11504787U JPH0538441Y2 (en) | 1987-07-29 | 1987-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11504787U JPH0538441Y2 (en) | 1987-07-29 | 1987-07-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6423765U true JPS6423765U (en) | 1989-02-08 |
| JPH0538441Y2 JPH0538441Y2 (en) | 1993-09-29 |
Family
ID=31356344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11504787U Expired - Lifetime JPH0538441Y2 (en) | 1987-07-29 | 1987-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0538441Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166375A (en) * | 1987-12-23 | 1989-06-30 | Sony Corp | Detecting and protecting circuit for synchronizing signal |
-
1987
- 1987-07-29 JP JP11504787U patent/JPH0538441Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166375A (en) * | 1987-12-23 | 1989-06-30 | Sony Corp | Detecting and protecting circuit for synchronizing signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0538441Y2 (en) | 1993-09-29 |
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