JPH0538480Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field The present invention relates to an EPROM writing circuit, especially
The present invention relates to an EPROM writing circuit that can write program data to a storage capacity smaller than the total storage capacity of the EPROM.

(b) Conventional technology For example, PROM for EPROM with 32K bit configuration
We will explain the case where a writer writes program data to each address of a 64K-bit EPROM.

Assuming that one word at each address of the EPROM is a unit of 8 bits, the storage capacity of the EPROM having a 32K bit configuration is 4K bytes, that is, the number of addresses required to access each address is 4K.
Therefore, the addresses of the 32K bit EPROM are assigned from "000" to "FFF". These addresses "0" to "F" are each represented by 4-bit data, that is, "000".
It is assumed that addresses up to "FFF" are each indicated by 4×3=12 bits of address data (A ₀ to A ₁₁ , where the A ₀ bit is the least significant bit).
On the other hand, the storage capacity of an EPROM with a 64K bit configuration is 8
(=64/8) Since it is K bytes, the corresponding
The number of addresses required to access each address of EPROM is 8K. Therefore, the addresses of the 64K-bit EPROM are assigned from "0000" to "1FFF". That is, these addresses "0000" to "1FFF" are each indicated by 13-bit address data (A ₀ to A ₁₂ ).
In other words, the most significant bit of address data A ₁₂
= “0”, address data A ₀ to A ₁₂ determines whether one of the EPROMs has a 64K bit configuration.
32K bit write area (“0000” to “0FFF”)
address) is accessed and if the most significant bit _A12 of the address data = "1", the address data
A ₀ to A ₁₂ access the remaining 32K bit write area (addresses "1000" to "1FFF") in the 64K bit EPROM.

As is clear from the above, the 64K bit configuration
If the most significant bit _A12 data required to access each address of EPROM is changed to "0" or "1" by some method, even a PROM writer for EPROM with 32K bit configuration can be used with 64K bit configuration. This means that each address of the EPROM can be accessed. However, with conventional PROM writers for EPROMs with a 32K bit configuration,
It was only possible to access the ``FFF'' address, and the most significant bit _A12 of the 13-bit address data required to access each address of the 64K-bit EPROM could not be generated.

Therefore, conventionally, the most significant bit A ₁₂ is applied.
Connect the power supply V _DD to the _A12 pin of the 64K-bit EPROM.
A manual changeover switch that can be set to either (logic ``1'') or ground (logic ``0'') is provided, and by switching this manual changeover switch, a PROM writer for a 32K-bit EPROM can be used. , it was compatible with writing program data to EPROM with a 64K bit configuration.

(c) Problems to be solved by the invention However, in the above-mentioned conventional technology, the 64K bit configuration cannot be changed by changing the manual changeover switch.
The most significant bit _A12 of the 13-bit address data for accessing each address of EPROM is
Since it is changed to “0” or “1”, the applicable
It takes a lot of time to write the program data to the EPROM, and furthermore, due to incorrect switching of the manual changeover switch, writing errors may occur, such as writing the specified program data into the writing area of the EPROM where it should not be written. There was a problem.

(d) Means for solving the problem The present invention was made in order to solve the above problem, and it has a storage capacity of a predetermined bit and is capable of writing/reading program data.
EPROM and address data for accessing the specified address of the EPROM are sequentially generated and
Program data can be written to a storage capacity that is less than the total storage capacity of EPROM.
A first pulse generation circuit that generates a first pulse for a predetermined time based on a write initial address applied to the EPROM from the PROM writer, and the write initial address. a second pulse generating circuit that generates a second pulse only during the generation period of the write initial address; and a reset pulse generating circuit that generates a reset pulse when the first pulse generation period is less than the second pulse generation period. After being reset by the reset pulse generated by the reset pulse generation circuit and the reset pulse generated by the reset pulse generation circuit, it is set by a change in the most significant bit of the last address data generated from the PROM writer, and is reset or set output. a reset/set circuit that switches the write area of the EPROM by setting the most significant bit of the address of the EPROM to the most significant bit of the address of the EPROM; By setting it longer than the pulse generation period, the reset/
The reset output of the set circuit makes it possible to write program data to the storage capacity in a predetermined write area of the EPROM, and then sets the generation period of the second pulse at the initial write address to be equal to or less than the generation period of the first pulse. The EPROM write circuit is characterized in that by setting the SET output of the reset/set circuit, program data can be written into the storage capacity of the remaining write area of the EPROM.

(*) Effect The present invention is an EPROM writing circuit that can write program data into a storage capacity smaller than the total storage capacity of the EPROM, and is effective as shown below. That is, in the configuration described in item (d) above, when the initial write address to be applied to the EPROM is generated from the PROM writer,
Based on the write initial address, a first pulse is generated from the first pulse generation circuit for a predetermined period of time. Further, based on the write initial address, a second pulse is generated from the second pulse generating circuit for a period during which the write initial address is generated.

First, when the PROM writer sets the access period of the write initial address in the EPROM, that is, the generation period of the second pulse, to be longer than the generation period of the first pulse, a reset pulse is generated from the reset pulse generation circuit. The reset/set circuit is reset by the reset pulse. Therefore, the reset output from the reset/set circuit causes the most significant bit of the EPROM address data to become "0", and the PROM writer accesses the specified write area of the EPROM to write program data. It becomes possible.

Thereafter, the address data generated from the PROM writer is sequentially incremented and the last address data is counted, and if the most significant bit of the last address data changes in order to access the EPROM initial write address again, the most significant bit of the last address data changes. A reset/set circuit is set based on the change in the bit, and the most significant bit of the EPROM address data is always set to "1" by the set output from the reset/set circuit. accordingly
The remaining write area of the EPROM is accessed by the PROM writer to enable writing of program data. At this time, the second pulse generation period is shorter than the first pulse generation period, and the reset pulse generation circuit does not generate a reset pulse.

As described above, after the predetermined write area of EPROM is accessed, the remaining write area of EPROM is accessed, and from this, program data can be written to each address of EPROM quickly and reliably. Become.

(f) Examples The details of the present invention will be explained in detail with reference to illustrated examples.

FIG. 1 is a circuit diagram showing the EPROM writing circuit of the present invention, and FIG. 2 is a timing chart showing waveforms at points a, b, and c in FIG.

To explain the symbols and structure of FIG. 1, 1
is a PROM writer for 32K bit EPROM. where the 32K bit EPROM (not shown)
If one word of 8 bits is used, the total number of addresses to access each address of the EPROM is 4K.
That is, 12-bit address data A ₀ to _{A 11} (A ₀ is the least significant bit) indicating addresses "000" to "FFF" are sequentially incremented and generated from the PROM writer 1. In addition, after the address data A ₀ to A ₁₁ indicating the address “FFF” is generated, the address data “000” to
Address data A ₀ to _{A 11} indicating the “FFF” address is applicable.
It is assumed that the PROM writer 1 is configured so that the signal is generated from the PROM writer 1.

2 is a 64K bit EPROM. Applicable here
If one word of EPROM2 is 8 bits, then
EPROM2 is 8K bytes, and the total number of addresses to access each address of EPROM2 is
It will be 8K. That is, in order to access all addresses of the EPROM 2, 13-bit address data _A0 to _A12 indicating addresses "0000" to "1FFF" are required.

Reference numeral 3 designates an OR gate (second pulse generation circuit), and the address data A ₀ to A ₁₀ for the lower 11 bits from the PROM writer 1 is applied to the OR gate 3. Then, the logical sum of address data A ₀ to A ₁₀ is calculated. In other words, applicable
A second pulse of "0" is generated from the OR gate 3 while the PROM writer 1 is outputting address data indicating the address "000". 4 is a first pulse generation circuit, which receives the OR output from the OR gate 3 and generates the first pulse of ``1'' for 100 msec from the start of address ``000''. occurs. 5 is a NOR gate (reset pulse generation circuit);
The OR output of the OR gate 3 and the output from the first pulse generation circuit 4 are applied to the gate 5, and the second pulse generation period is set to be longer than the first pulse generation period. When there is a corresponding
A reset pulse of "1" is generated from the NOR gate 5. 6 is a T-type flip-flop (reset/
It is a set circuit (hereinafter referred to as T-FF),
The T (trigger) terminal is connected to the PROM writer 1.
The most significant bit _A11 of the address data output from the _A11 terminal is applied, and the R (reset) terminal is
A reset pulse from the NOR gate 5 is applied, and the Q (output) terminal is connected to the _A12 terminal for the most significant bit _A12 of the EPROM2.
That is, the reset or set output output from the Q terminal of the T-FF6 is used as the most significant bit _A12 of the 13-bit address data _A0 to _A12 for accessing each address of the EPROM2. be.

Next, in FIG. 2, AD indicates the address of the EPROM 2 that is accessed by address data A ₀ to _{A 11} generated from the PROM writer 1, and address data A ₀ indicates the first address "000". The generation period of ~ _A11 is controlled to 200 msec by the PROM writer 1 itself. Furthermore, the generation period of address data A ₀ to _{A 11} indicating addresses "001" to "FFF" and "000" to "FFF" thereafter is as follows.
In order to achieve the writing standard of EPROM2 of 50 msec,
It is controlled by the PROM writer 1 itself. Also, a is output from the OR gate 3.
It is an OR output. That is, during the access period of address "000" of the EPROM 2, from the OR gate 3,
A second pulse of "0" is generated. Further, b is the output of the first pulse generating circuit 4. That is, when the address "000" of the EPROM 2 is accessed,
From the start timing of this access T ₀ , T ₀ ′
The first pulse of "1" is generated from the first pulse generating circuit 4 for 100 msec. Furthermore, c is the NOR output of the NOR gate 5. That is,
During the access period of the first address “000” in EPROM2, the latter half when both a and b are “0”
"1" from the corresponding NOR gate 5 only for 100msec period
A reset pulse is generated. The reason why the generation period of the first pulse and the reset pulse is set to 100 msec is that the margin is set to ±25 msec when the actual write period of 50 msec for each address in the EPROM 2 deviates due to jitter. Furthermore, the first 200msec in EPROM2
During the access period for address ``000'', program data is written to address ``000'' of the EPROM 2 in the last 50 msec.

The operation shown in FIG. 1 will be explained below based on the waveforms shown in FIG. 2.

First, PROM writer 1 starts accessing each address of EPROM 2, and address data A ₀ to A ₁₁ indicating address "000" is first accessed by PROM writer 1.
The access start timing of the EPROM 2 address by 200 msec from T ₀ , the corresponding PROM writer 1
If the occurrence occurs from
A second pulse of "0" is generated. and
When the fall of the output a of the OR gate 3 at the access start timing T ₀ of the address "000" of the EPROM 2 is applied to the first pulse generation circuit 4, the address "000"
The first pulse of "1" is generated from the first pulse generating circuit 4 for 100 msec from the start of the address. Therefore, in the access period for the address "000", during the latter 100 msec period, the output a of the OR gate 3 and the output b of the first pulse generation circuit 4 are
Both become "0", and a reset pulse of "1" is generated from the NOR gate 5 during the latter 100 msec period. This "1" reset pulse is applied to the R terminal of T-FF6, and the T-FF6 reset pulse is applied to the R terminal of T-FF6.
FF6 will be reset. therefore
The most significant bit _A12 of the 13-bit address data for accessing each address of EPROM2 is T.
- It is set to "0" by the Q output of FF6. still,
The T terminal of T-FF6 is triggered by the falling edge of daughter _A11 . In other words, the address indicated by address data A ₀ to _{A 11} progresses from "000" to "FFF", and then the data continues until it changes from "FFF" to the next "000".
_A11 does not fall from "1" to "0", that is, until the access start timing _T0 ' of the next address "000",
T-FF6 is not triggered and the most significant bit _A12 of EPROM2 is held at "0".

From now on, the most significant bit _A12 of EPROM2 will always be "0" from the start timing of accessing the address of EPROM2 from _T0 to _T0 ', that is, the PROM writer 1 will write "0000" to "0FFF" of EPROM2.
The addresses will be accessed sequentially. here
Inside PROM writer 1, “0000” of EPROM 2 is stored.
A program memory (not shown) having an address corresponding to the address "1FFF" is built-in, and therefore the program data stored at the address "0000" to "0FFF" of the program memory is
It will be written to addresses "0000" to "0FFF" of EPROM2.

Thereafter, when the address indicated by the address data A ₀ to A ₁₁ generated from PROM writer 1 changes from "FFF" to "000" at timing T ₀ ', the address indicated by address data A 0 to A 11 generated from PROM writer 1 changes from "FFF" to "000". The upper bit _A11 falls from "1" to "0", and T-FF6 is set from this, and the Q of the T-FF6 is set.
As a result of the output, the most significant bit _A12 for accessing each address of the EPROM 2 becomes "1". Also, at this time, since the access period for address "000" at timing T ₀ ' is 50 msec, a reset pulse of "1" is not generated from NOR gate 5.

From this, after timing T ₀ ′, “000”
~ Address data A ₀ ~ _{A 11} indicating address “FFF” is
Periods that occur sequentially from PROM writer 1,
The most significant bit _A12 of the EPROM2 is always "1", that is, the EPOM writer 1 sequentially accesses addresses "1000" to "1FFF" of the EPROM2. Therefore, the program data stored in addresses "1000" to "1FFF" of the program memory inside the PROM writer 1 are stored in the EPROM 2, respectively.
will be written to addresses "1000" to "1FFF".

As described above, according to the present embodiment embodying the present invention, when program data is written to each address of the 64K-bit EPROM 2 using the PROM writer 1 for the 32K-bit EPROM, the corresponding
EPROM2 address is “0000” ~ “0FFF”,
"1000" to "1FFF" will be automatically accessed in the order, which will shorten the time to write program data to the EPROM 2, and furthermore, it will be possible to write the specified program data to the write area of the EPROM 2 that should not be written. It is also possible to prevent unnecessary writing errors.

(g) Effects of the invention According to the invention, a PROM writer capable of writing program data to a storage capacity smaller than the total storage capacity of the EPROM is used to write the program data.
When writing program data to EPROM, predetermined write areas of the EPROM are automatically and reliably accessed in a predetermined order, which reduces the time it takes to write program data to the EPROM. Further, it is possible to reliably prevent write errors such as writing incorrect program data into the write area of the EPROM to be written.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an EPROM writing circuit of the present invention, and FIG. 2 is a timing chart showing waveforms of various parts of FIG. 1. 1...PROM writer, 2...EPROM, 3...
...OR gate, 4...First pulse generation circuit, 5
...NOR gate, 6...T-FF.

Claims (1)

[Utility model claim] An EPROM having a memory capacity of a certain number of bits and capable of writing/reading program data,
an EPROM write circuit having a PROM writer which sequentially generates address data for accessing predetermined addresses in an EPROM and can write program data into a storage capacity smaller than the total storage capacity of the EPROM, the circuit comprising: a first pulse generating circuit which generates a first pulse for a predetermined time based on a write initial address applied to the EPROM from the PROM writer; a second pulse generating circuit which generates a second pulse based on the write initial address and for only a period during which the write initial address is generated; a reset pulse generating circuit which generates a reset pulse when the period during which the first pulse is generated is shorter than the period during which the second pulse is generated; and a reset/set circuit which is reset by a reset pulse generated by the reset pulse generating circuit and then set by a change in the most significant bit of the last address data generated by the PROM writer, and which switches the write area of the EPROM by setting a reset or set output to the most significant bit of the EPROM's address; The period during which the second pulse occurs at the write initial address is set to be longer than the period during which the first pulse occurs,
an EPROM write circuit characterized in that a reset output from a set circuit enables program data to be written to the memory capacity in a specified write area of the EPROM, and then, by setting the generation period of the second pulse at the write initial address to be equal to or shorter than the generation period of the first pulse, a set output from the reset/set circuit enables program data to be written to the memory capacity in the remaining write areas of the EPROM.